fc571a94aaf181d2c0c2ee8448d113ca6ee825c7

As per DSI HPG, pll delay should be 25usec for phy ver 4.0 and 100usec for phy ver 2.0 and 3.0. This change updates pll delay calculation during dynamic DSI clock switch accordingly. Change-Id: Ief5cbdc9304cf5ad025fe3bbe689b93834a1f710 Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
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