451f79771f
Add DSI CTL MISR support for ctl 2.2 version. Reuse the same debugfs nodes to setup/collect misr. Change-Id: I3d8dfab093659ce53817d9511999c0c03cc33f62 Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
351 行
9.1 KiB
C
351 行
9.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
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* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#include <linux/iopoll.h>
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#include "dsi_ctrl_hw.h"
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#include "dsi_ctrl_reg.h"
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#include "dsi_hw.h"
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#include "dsi_ctrl.h"
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#include "dsi_catalog.h"
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#define DISP_CC_MISC_CMD_REG_OFF 0x00
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/* register to configure DMA scheduling */
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#define DSI_DMA_SCHEDULE_CTRL 0x100
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#define DSI_DMA_SCHEDULE_CTRL2 0x0104
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/* offset addresses of MDP INTF base register, to be mapped for debug feature */
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#define MDP_INTF_TEAR_OFFSET 0x280
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#define MDP_INTF_TEAR_LINE_COUNT_OFFSET 0x30
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#define MDP_INTF_LINE_COUNT_OFFSET 0xB0
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#define DSI_MDP_MISR_CTRL 0x364
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#define DSI_MDP_MISR_SIGNATURE 0x368
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void dsi_ctrl_hw_22_setup_lane_map(struct dsi_ctrl_hw *ctrl,
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struct dsi_lane_map *lane_map)
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{
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u32 reg_value = lane_map->lane_map_v2[DSI_LOGICAL_LANE_0] |
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(lane_map->lane_map_v2[DSI_LOGICAL_LANE_1] << 4) |
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(lane_map->lane_map_v2[DSI_LOGICAL_LANE_2] << 8) |
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(lane_map->lane_map_v2[DSI_LOGICAL_LANE_3] << 12);
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DSI_W32(ctrl, DSI_LANE_SWAP_CTRL, reg_value);
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DSI_CTRL_HW_DBG(ctrl, "[DSI_%d] Lane swap setup complete\n",
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ctrl->index);
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}
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int dsi_ctrl_hw_22_wait_for_lane_idle(struct dsi_ctrl_hw *ctrl,
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u32 lanes)
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{
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int rc = 0, val = 0;
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u32 fifo_empty_mask = 0;
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u32 const sleep_us = 10;
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u32 const timeout_us = 100;
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if (lanes & DSI_DATA_LANE_0)
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fifo_empty_mask |= (BIT(12) | BIT(16));
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if (lanes & DSI_DATA_LANE_1)
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fifo_empty_mask |= BIT(20);
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if (lanes & DSI_DATA_LANE_2)
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fifo_empty_mask |= BIT(24);
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if (lanes & DSI_DATA_LANE_3)
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fifo_empty_mask |= BIT(28);
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DSI_CTRL_HW_DBG(ctrl, "%s: polling for fifo empty, mask=0x%08x\n",
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__func__, fifo_empty_mask);
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rc = DSI_READ_POLL_TIMEOUT(ctrl, DSI_FIFO_STATUS, val,
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(val & fifo_empty_mask), sleep_us, timeout_us);
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if (rc) {
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DSI_CTRL_HW_ERR(ctrl,
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"%s: fifo not empty, FIFO_STATUS=0x%08x\n",
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__func__, val);
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goto error;
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}
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error:
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return rc;
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}
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ssize_t dsi_ctrl_hw_22_reg_dump_to_buffer(struct dsi_ctrl_hw *ctrl,
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char *buf,
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u32 size)
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{
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return size;
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}
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/**
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* dsi_ctrl_hw_22_phy_reset_config() - to configure clamp control during ulps
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* @ctrl: Pointer to the controller host hardware.
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* @enable: boolean to specify enable/disable.
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*/
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void dsi_ctrl_hw_22_phy_reset_config(struct dsi_ctrl_hw *ctrl,
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bool enable)
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{
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u32 reg = 0;
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reg = DSI_DISP_CC_R32(ctrl, DISP_CC_MISC_CMD_REG_OFF);
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/* Mask/unmask disable PHY reset bit */
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if (enable)
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reg &= ~BIT(ctrl->index);
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else
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reg |= BIT(ctrl->index);
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DSI_DISP_CC_W32(ctrl, DISP_CC_MISC_CMD_REG_OFF, reg);
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}
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/**
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* dsi_ctrl_hw_22_schedule_dma_cmd() - to schedule DMA command transfer
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* @ctrl: Pointer to the controller host hardware.
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* @line_no: Line number at which command needs to be sent.
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*/
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void dsi_ctrl_hw_22_schedule_dma_cmd(struct dsi_ctrl_hw *ctrl, int line_no)
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{
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u32 reg = 0;
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reg = DSI_R32(ctrl, DSI_DMA_SCHEDULE_CTRL);
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reg |= BIT(28);
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reg |= (line_no & 0xffff);
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DSI_W32(ctrl, DSI_DMA_SCHEDULE_CTRL, reg);
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ctrl->reset_trig_ctrl = true;
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}
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/*
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* dsi_ctrl_hw_kickoff_non_embedded_mode()-Kickoff cmd in non-embedded mode
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* @ctrl: - Pointer to the controller host hardware.
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* @dsi_ctrl_cmd_dma_info: - command buffer information.
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* @flags: - DSI CTRL Flags.
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*/
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void dsi_ctrl_hw_kickoff_non_embedded_mode(struct dsi_ctrl_hw *ctrl,
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struct dsi_ctrl_cmd_dma_info *cmd,
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u32 flags)
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{
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u32 reg = 0;
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reg = DSI_R32(ctrl, DSI_COMMAND_MODE_DMA_CTRL);
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reg &= ~BIT(31);/* disable broadcast */
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reg &= ~BIT(30);
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if (cmd->use_lpm)
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reg |= BIT(26);
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else
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reg &= ~BIT(26);
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/* Select non EMBEDDED_MODE, pick the packet header from register */
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reg &= ~BIT(28);
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reg |= BIT(24);/* long packet */
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reg |= BIT(29);/* wc_sel = 1 */
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reg |= (((cmd->datatype) & 0x03f) << 16);/* data type */
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DSI_W32(ctrl, DSI_COMMAND_MODE_DMA_CTRL, reg);
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/* Enable WRITE_WATERMARK_DISABLE and READ_WATERMARK_DISABLE bits */
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reg = DSI_R32(ctrl, DSI_DMA_FIFO_CTRL);
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reg |= BIT(20);
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reg |= BIT(16);
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reg |= 0x33;/* Set READ and WRITE watermark levels to maximum */
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DSI_W32(ctrl, DSI_DMA_FIFO_CTRL, reg);
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DSI_W32(ctrl, DSI_DMA_CMD_OFFSET, cmd->offset);
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DSI_W32(ctrl, DSI_DMA_CMD_LENGTH, ((cmd->length) & 0xFFFFFF));
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/* wait for writes to complete before kick off */
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wmb();
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if (!(flags & DSI_CTRL_HW_CMD_WAIT_FOR_TRIGGER))
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DSI_W32(ctrl, DSI_CMD_MODE_DMA_SW_TRIGGER, 0x1);
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}
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/*
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* dsi_ctrl_hw_22_config_clk_gating() - enable/disable clk gating on DSI PHY
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* @ctrl: Pointer to the controller host hardware.
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* @enable: bool to notify enable/disable.
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* @clk_selection: clock to enable/disable clock gating.
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*
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*/
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void dsi_ctrl_hw_22_config_clk_gating(struct dsi_ctrl_hw *ctrl, bool enable,
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enum dsi_clk_gate_type clk_selection)
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{
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u32 reg = 0;
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u32 enable_select = 0;
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reg = DSI_DISP_CC_R32(ctrl, DISP_CC_MISC_CMD_REG_OFF);
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if (clk_selection & PIXEL_CLK)
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enable_select |= ctrl->index ? BIT(6) : BIT(5);
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if (clk_selection & BYTE_CLK)
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enable_select |= ctrl->index ? BIT(8) : BIT(7);
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if (clk_selection & DSI_PHY)
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enable_select |= ctrl->index ? BIT(10) : BIT(9);
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if (enable)
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reg |= enable_select;
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else
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reg &= ~enable_select;
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DSI_DISP_CC_W32(ctrl, DISP_CC_MISC_CMD_REG_OFF, reg);
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}
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/**
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* dsi_ctrl_hw_22_configure_cmddma_window() - configure DMA window for CMD TX
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* @ctrl: Pointer to the controller host hardware.
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* @cmd: Pointer to the DSI DMA command info.
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* @line_no: Line number at which the CMD needs to be triggered.
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* @window: Width of the DMA CMD window.
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*/
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void dsi_ctrl_hw_22_configure_cmddma_window(struct dsi_ctrl_hw *ctrl,
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struct dsi_ctrl_cmd_dma_info *cmd,
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u32 line_no, u32 window)
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{
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u32 reg = 0;
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if (cmd->en_broadcast) {
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reg = DSI_R32(ctrl, DSI_TRIG_CTRL);
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if (cmd->is_master) {
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reg &= ~0xF;
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reg |= 0xc;
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} else {
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reg &= ~0xF;
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reg |= BIT(16);
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}
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DSI_W32(ctrl, DSI_TRIG_CTRL, reg);
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if (cmd->is_master) {
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reg = 0;
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reg |= line_no;
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reg |= window << 16;
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DSI_W32(ctrl, DSI_DMA_SCHEDULE_CTRL2, reg);
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}
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} else {
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reg = DSI_R32(ctrl, DSI_TRIG_CTRL);
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reg &= ~0xF;
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reg |= 0xc;
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DSI_W32(ctrl, DSI_TRIG_CTRL, reg);
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reg = 0;
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reg |= line_no;
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reg |= window << 16;
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DSI_W32(ctrl, DSI_DMA_SCHEDULE_CTRL2, reg);
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}
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ctrl->reset_trig_ctrl = true;
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}
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/**
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* dsi_ctrl_hw_22_reset_trigger_controls() - reset dsi trigger configurations
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* @ctrl: Pointer to the controller host hardware.
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* @cfg: DSI host configuration that is common to both video and
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* command modes.
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*/
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void dsi_ctrl_hw_22_reset_trigger_controls(struct dsi_ctrl_hw *ctrl,
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struct dsi_host_common_cfg *cfg)
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{
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u32 reg = 0;
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const u8 trigger_map[DSI_TRIGGER_MAX] = {
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0x0, 0x2, 0x1, 0x4, 0x5, 0x6 };
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reg |= (cfg->te_mode == DSI_TE_ON_EXT_PIN) ? BIT(31) : 0;
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reg |= (trigger_map[cfg->dma_cmd_trigger] & 0x7);
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reg |= (trigger_map[cfg->mdp_cmd_trigger] & 0x7) << 4;
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DSI_W32(ctrl, DSI_TRIG_CTRL, reg);
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DSI_W32(ctrl, DSI_DMA_SCHEDULE_CTRL2, 0x0);
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DSI_W32(ctrl, DSI_DMA_SCHEDULE_CTRL, 0x0);
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ctrl->reset_trig_ctrl = false;
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}
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/**
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* dsi_ctrl_hw_22_log_line_count() - reads the MDP interface line count
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* registers.
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* @ctrl: Pointer to the controller host hardware.
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* @cmd_mode: Boolean to indicate command mode operation.
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*
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* Return: INTF register value.
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*/
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u32 dsi_ctrl_hw_22_log_line_count(struct dsi_ctrl_hw *ctrl, bool cmd_mode)
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{
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u32 reg = 0;
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if (IS_ERR_OR_NULL(ctrl->mdp_intf_base))
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return reg;
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if (cmd_mode)
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reg = DSI_MDP_INTF_R32(ctrl, MDP_INTF_TEAR_OFFSET
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+ MDP_INTF_TEAR_LINE_COUNT_OFFSET);
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else
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reg = DSI_MDP_INTF_R32(ctrl, MDP_INTF_LINE_COUNT_OFFSET);
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return reg;
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}
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void dsi_ctrl_hw_22_configure_splitlink(struct dsi_ctrl_hw *ctrl,
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struct dsi_host_common_cfg *common_cfg, u32 flags)
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{
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u32 reg = 0;
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reg = DSI_R32(ctrl, DSI_SPLIT_LINK);
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/* DMA_LINK_SEL */
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reg &= ~(0x7 << 12);
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/* Send command to both sublinks unless specified */
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if (flags & DSI_CTRL_CMD_SUBLINK0)
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reg |= BIT(12);
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else if (flags & DSI_CTRL_CMD_SUBLINK1)
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reg |= BIT(13);
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else
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reg |= (BIT(12) | BIT(13));
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/**
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* Avoid dma trigger on sublink1 for read commands. This can be
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* enabled in future if panel supports sending read command on sublink1.
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*/
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if (flags & DSI_CTRL_CMD_READ) {
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reg = reg & ~BIT(13);
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}
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DSI_W32(ctrl, DSI_SPLIT_LINK, reg);
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/* Make sure the split link config is updated */
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wmb();
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}
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void dsi_ctrl_hw_22_setup_misr(struct dsi_ctrl_hw *ctrl, enum dsi_op_mode panel_mode,
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bool enable, u32 frame_count)
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{
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u32 config = 0;
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DSI_W32(ctrl, DSI_MDP_MISR_CTRL, config);
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wmb(); /* clear misr data */
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if (enable) {
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config = (frame_count & 0xffff);
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config |= BIT(8) | BIT(24) | BIT(31); /* enable, panel data-only, free run mode */
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}
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DSI_CTRL_HW_DBG(ctrl, "MISR enable:%d, frame_count:%d, config:0x%x\n",
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enable, frame_count, config);
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DSI_W32(ctrl, DSI_MDP_MISR_CTRL, config);
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wmb(); /* make sure MISR is configured */
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}
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u32 dsi_ctrl_hw_22_collect_misr(struct dsi_ctrl_hw *ctrl, enum dsi_op_mode panel_mode)
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{
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u32 enabled;
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u32 misr = 0;
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enabled = DSI_R32(ctrl, DSI_MDP_MISR_CTRL) & BIT(8);
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if (enabled)
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misr = DSI_R32(ctrl, DSI_MDP_MISR_SIGNATURE);
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DSI_CTRL_HW_DBG(ctrl, "MISR enabled:%d value:0x%x\n", enabled, misr);
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return misr;
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}
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