disp: msm: dsi: add MISR support for ctl 2.2 version

Add DSI CTL MISR support for ctl 2.2 version. Reuse the same
debugfs nodes to setup/collect misr.

Change-Id: I3d8dfab093659ce53817d9511999c0c03cc33f62
Signed-off-by: Veera Sundaram Sankaran <[email protected]>

msm/dsi/dsi_catalog.c

@@ -96,6 +96,8 @@ static void dsi_catalog_cmn_init(struct dsi_ctrl_hw *ctrl,
 			dsi_ctrl_hw_22_reset_trigger_controls;
 		ctrl->ops.log_line_count = dsi_ctrl_hw_22_log_line_count;
 		ctrl->ops.splitlink_cmd_setup = dsi_ctrl_hw_22_configure_splitlink;
+		ctrl->ops.setup_misr = dsi_ctrl_hw_22_setup_misr;
+		ctrl->ops.collect_misr = dsi_ctrl_hw_22_collect_misr;
 		break;
 	default:
 		break;

msm/dsi/dsi_catalog.h

@@ -275,6 +275,10 @@ void dsi_ctrl_hw_22_config_clk_gating(struct dsi_ctrl_hw *ctrl, bool enable,
 void dsi_ctrl_hw_cmn_set_continuous_clk(struct dsi_ctrl_hw *ctrl, bool enable);
 void dsi_ctrl_hw_cmn_hs_req_sel(struct dsi_ctrl_hw *ctrl, bool sel_phy);
 
+void dsi_ctrl_hw_22_setup_misr(struct dsi_ctrl_hw *ctrl, enum dsi_op_mode panel_mode,
+			bool enable, u32 frame_count);
+u32 dsi_ctrl_hw_22_collect_misr(struct dsi_ctrl_hw *ctrl, enum dsi_op_mode panel_mode);
+
 /* dynamic refresh specific functions */
 void dsi_phy_hw_v3_0_dyn_refresh_helper(struct dsi_phy_hw *phy, u32 offset);
 void dsi_phy_hw_v3_0_dyn_refresh_config(struct dsi_phy_hw *phy,

msm/dsi/dsi_ctrl_hw_2_2.c

@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 #include <linux/iopoll.h>
 #include "dsi_ctrl_hw.h"
@@ -20,6 +21,9 @@
 #define MDP_INTF_TEAR_LINE_COUNT_OFFSET 0x30
 #define MDP_INTF_LINE_COUNT_OFFSET 0xB0
 
+#define DSI_MDP_MISR_CTRL 0x364
+#define DSI_MDP_MISR_SIGNATURE 0x368
+
 void dsi_ctrl_hw_22_setup_lane_map(struct dsi_ctrl_hw *ctrl,
 		       struct dsi_lane_map *lane_map)
 {
@@ -312,3 +316,35 @@ void dsi_ctrl_hw_22_configure_splitlink(struct dsi_ctrl_hw *ctrl,
 	/* Make sure the split link config is updated */
 	wmb();
 }
+
+void dsi_ctrl_hw_22_setup_misr(struct dsi_ctrl_hw *ctrl, enum dsi_op_mode panel_mode,
+			bool enable, u32 frame_count)
+{
+	u32 config = 0;
+
+	DSI_W32(ctrl, DSI_MDP_MISR_CTRL, config);
+	wmb(); /* clear misr data */
+
+	if (enable) {
+		config = (frame_count & 0xffff);
+		config |= BIT(8) | BIT(24) | BIT(31); /* enable, panel data-only, free run mode */
+	}
+
+	DSI_CTRL_HW_DBG(ctrl, "MISR enable:%d, frame_count:%d, config:0x%x\n",
+			enable, frame_count, config);
+	DSI_W32(ctrl, DSI_MDP_MISR_CTRL, config);
+	wmb(); /* make sure MISR is configured */
+}
+
+u32 dsi_ctrl_hw_22_collect_misr(struct dsi_ctrl_hw *ctrl, enum dsi_op_mode panel_mode)
+{
+	u32 enabled;
+	u32 misr = 0;
+
+	enabled = DSI_R32(ctrl, DSI_MDP_MISR_CTRL) & BIT(8);
+	if (enabled)
+		misr = DSI_R32(ctrl, DSI_MDP_MISR_SIGNATURE);
+
+	DSI_CTRL_HW_DBG(ctrl, "MISR enabled:%d value:0x%x\n", enabled, misr);
+	return misr;
+}