123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716 |
-
-
-
-
-
-
-
- #ifndef _EXPECTED_RESPONSE_H_
- #define _EXPECTED_RESPONSE_H_
- #if !defined(__ASSEMBLER__)
- #endif
- #define NUM_OF_DWORDS_EXPECTED_RESPONSE 6
- #define NUM_OF_QWORDS_EXPECTED_RESPONSE 3
- struct expected_response {
- #ifndef WIFI_BIT_ORDER_BIG_ENDIAN
- uint32_t tx_ad2_31_0 : 32;
- uint32_t tx_ad2_47_32 : 16,
- expected_response_type : 5,
- response_to_response : 3,
- su_ba_user_number : 1,
- response_info_part2_required : 1,
- transmitted_bssid_check_en : 1,
- reserved_1 : 5;
- uint32_t ndp_sta_partial_aid_2_8_0 : 11,
- reserved_2 : 10,
- ndp_sta_partial_aid1_8_0 : 11;
- uint32_t ast_index : 16,
- capture_ack_ba_sounding : 1,
- capture_sounding_1str_20mhz : 1,
- capture_sounding_1str_40mhz : 1,
- capture_sounding_1str_80mhz : 1,
- capture_sounding_1str_160mhz : 1,
- capture_sounding_1str_240mhz : 1,
- capture_sounding_1str_320mhz : 1,
- reserved_3a : 9;
- uint32_t fcs : 9,
- reserved_4a : 1,
- crc : 4,
- scrambler_seed : 7,
- reserved_4b : 11;
- uint32_t tlv64_padding : 32;
- #else
- uint32_t tx_ad2_31_0 : 32;
- uint32_t reserved_1 : 5,
- transmitted_bssid_check_en : 1,
- response_info_part2_required : 1,
- su_ba_user_number : 1,
- response_to_response : 3,
- expected_response_type : 5,
- tx_ad2_47_32 : 16;
- uint32_t ndp_sta_partial_aid1_8_0 : 11,
- reserved_2 : 10,
- ndp_sta_partial_aid_2_8_0 : 11;
- uint32_t reserved_3a : 9,
- capture_sounding_1str_320mhz : 1,
- capture_sounding_1str_240mhz : 1,
- capture_sounding_1str_160mhz : 1,
- capture_sounding_1str_80mhz : 1,
- capture_sounding_1str_40mhz : 1,
- capture_sounding_1str_20mhz : 1,
- capture_ack_ba_sounding : 1,
- ast_index : 16;
- uint32_t reserved_4b : 11,
- scrambler_seed : 7,
- crc : 4,
- reserved_4a : 1,
- fcs : 9;
- uint32_t tlv64_padding : 32;
- #endif
- };
- #define EXPECTED_RESPONSE_TX_AD2_31_0_OFFSET 0x0000000000000000
- #define EXPECTED_RESPONSE_TX_AD2_31_0_LSB 0
- #define EXPECTED_RESPONSE_TX_AD2_31_0_MSB 31
- #define EXPECTED_RESPONSE_TX_AD2_31_0_MASK 0x00000000ffffffff
- #define EXPECTED_RESPONSE_TX_AD2_47_32_OFFSET 0x0000000000000000
- #define EXPECTED_RESPONSE_TX_AD2_47_32_LSB 32
- #define EXPECTED_RESPONSE_TX_AD2_47_32_MSB 47
- #define EXPECTED_RESPONSE_TX_AD2_47_32_MASK 0x0000ffff00000000
- #define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_OFFSET 0x0000000000000000
- #define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_LSB 48
- #define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MSB 52
- #define EXPECTED_RESPONSE_EXPECTED_RESPONSE_TYPE_MASK 0x001f000000000000
- #define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_OFFSET 0x0000000000000000
- #define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_LSB 53
- #define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MSB 55
- #define EXPECTED_RESPONSE_RESPONSE_TO_RESPONSE_MASK 0x00e0000000000000
- #define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_OFFSET 0x0000000000000000
- #define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_LSB 56
- #define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MSB 56
- #define EXPECTED_RESPONSE_SU_BA_USER_NUMBER_MASK 0x0100000000000000
- #define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_OFFSET 0x0000000000000000
- #define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_LSB 57
- #define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MSB 57
- #define EXPECTED_RESPONSE_RESPONSE_INFO_PART2_REQUIRED_MASK 0x0200000000000000
- #define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_OFFSET 0x0000000000000000
- #define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_LSB 58
- #define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MSB 58
- #define EXPECTED_RESPONSE_TRANSMITTED_BSSID_CHECK_EN_MASK 0x0400000000000000
- #define EXPECTED_RESPONSE_RESERVED_1_OFFSET 0x0000000000000000
- #define EXPECTED_RESPONSE_RESERVED_1_LSB 59
- #define EXPECTED_RESPONSE_RESERVED_1_MSB 63
- #define EXPECTED_RESPONSE_RESERVED_1_MASK 0xf800000000000000
- #define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_OFFSET 0x0000000000000008
- #define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_LSB 0
- #define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MSB 10
- #define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID_2_8_0_MASK 0x00000000000007ff
- #define EXPECTED_RESPONSE_RESERVED_2_OFFSET 0x0000000000000008
- #define EXPECTED_RESPONSE_RESERVED_2_LSB 11
- #define EXPECTED_RESPONSE_RESERVED_2_MSB 20
- #define EXPECTED_RESPONSE_RESERVED_2_MASK 0x00000000001ff800
- #define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_OFFSET 0x0000000000000008
- #define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_LSB 21
- #define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MSB 31
- #define EXPECTED_RESPONSE_NDP_STA_PARTIAL_AID1_8_0_MASK 0x00000000ffe00000
- #define EXPECTED_RESPONSE_AST_INDEX_OFFSET 0x0000000000000008
- #define EXPECTED_RESPONSE_AST_INDEX_LSB 32
- #define EXPECTED_RESPONSE_AST_INDEX_MSB 47
- #define EXPECTED_RESPONSE_AST_INDEX_MASK 0x0000ffff00000000
- #define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_OFFSET 0x0000000000000008
- #define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_LSB 48
- #define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MSB 48
- #define EXPECTED_RESPONSE_CAPTURE_ACK_BA_SOUNDING_MASK 0x0001000000000000
- #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_OFFSET 0x0000000000000008
- #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_LSB 49
- #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MSB 49
- #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_20MHZ_MASK 0x0002000000000000
- #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_OFFSET 0x0000000000000008
- #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_LSB 50
- #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MSB 50
- #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_40MHZ_MASK 0x0004000000000000
- #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_OFFSET 0x0000000000000008
- #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_LSB 51
- #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MSB 51
- #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_80MHZ_MASK 0x0008000000000000
- #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_OFFSET 0x0000000000000008
- #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_LSB 52
- #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MSB 52
- #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_160MHZ_MASK 0x0010000000000000
- #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_OFFSET 0x0000000000000008
- #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_LSB 53
- #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MSB 53
- #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_240MHZ_MASK 0x0020000000000000
- #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_OFFSET 0x0000000000000008
- #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_LSB 54
- #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MSB 54
- #define EXPECTED_RESPONSE_CAPTURE_SOUNDING_1STR_320MHZ_MASK 0x0040000000000000
- #define EXPECTED_RESPONSE_RESERVED_3A_OFFSET 0x0000000000000008
- #define EXPECTED_RESPONSE_RESERVED_3A_LSB 55
- #define EXPECTED_RESPONSE_RESERVED_3A_MSB 63
- #define EXPECTED_RESPONSE_RESERVED_3A_MASK 0xff80000000000000
- #define EXPECTED_RESPONSE_FCS_OFFSET 0x0000000000000010
- #define EXPECTED_RESPONSE_FCS_LSB 0
- #define EXPECTED_RESPONSE_FCS_MSB 8
- #define EXPECTED_RESPONSE_FCS_MASK 0x00000000000001ff
- #define EXPECTED_RESPONSE_RESERVED_4A_OFFSET 0x0000000000000010
- #define EXPECTED_RESPONSE_RESERVED_4A_LSB 9
- #define EXPECTED_RESPONSE_RESERVED_4A_MSB 9
- #define EXPECTED_RESPONSE_RESERVED_4A_MASK 0x0000000000000200
- #define EXPECTED_RESPONSE_CRC_OFFSET 0x0000000000000010
- #define EXPECTED_RESPONSE_CRC_LSB 10
- #define EXPECTED_RESPONSE_CRC_MSB 13
- #define EXPECTED_RESPONSE_CRC_MASK 0x0000000000003c00
- #define EXPECTED_RESPONSE_SCRAMBLER_SEED_OFFSET 0x0000000000000010
- #define EXPECTED_RESPONSE_SCRAMBLER_SEED_LSB 14
- #define EXPECTED_RESPONSE_SCRAMBLER_SEED_MSB 20
- #define EXPECTED_RESPONSE_SCRAMBLER_SEED_MASK 0x00000000001fc000
- #define EXPECTED_RESPONSE_RESERVED_4B_OFFSET 0x0000000000000010
- #define EXPECTED_RESPONSE_RESERVED_4B_LSB 21
- #define EXPECTED_RESPONSE_RESERVED_4B_MSB 31
- #define EXPECTED_RESPONSE_RESERVED_4B_MASK 0x00000000ffe00000
- #define EXPECTED_RESPONSE_TLV64_PADDING_OFFSET 0x0000000000000010
- #define EXPECTED_RESPONSE_TLV64_PADDING_LSB 32
- #define EXPECTED_RESPONSE_TLV64_PADDING_MSB 63
- #define EXPECTED_RESPONSE_TLV64_PADDING_MASK 0xffffffff00000000
- #endif
|