dp_be_rx.c 41 KB

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  1. /*
  2. * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
  3. * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
  4. *
  5. * Permission to use, copy, modify, and/or distribute this software for
  6. * any purpose with or without fee is hereby granted, provided that the
  7. * above copyright notice and this permission notice appear in all
  8. * copies.
  9. *
  10. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  11. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  12. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  13. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  14. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  15. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  16. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  17. * PERFORMANCE OF THIS SOFTWARE.
  18. */
  19. #include "cdp_txrx_cmn_struct.h"
  20. #include "hal_hw_headers.h"
  21. #include "dp_types.h"
  22. #include "dp_rx.h"
  23. #include "dp_tx.h"
  24. #include "dp_be_rx.h"
  25. #include "dp_peer.h"
  26. #include "hal_rx.h"
  27. #include "hal_be_rx.h"
  28. #include "hal_api.h"
  29. #include "hal_be_api.h"
  30. #include "qdf_nbuf.h"
  31. #include "hal_be_rx_tlv.h"
  32. #ifdef MESH_MODE_SUPPORT
  33. #include "if_meta_hdr.h"
  34. #endif
  35. #include "dp_internal.h"
  36. #include "dp_ipa.h"
  37. #ifdef FEATURE_WDS
  38. #include "dp_txrx_wds.h"
  39. #endif
  40. #include "dp_hist.h"
  41. #include "dp_rx_buffer_pool.h"
  42. #ifndef AST_OFFLOAD_ENABLE
  43. static void
  44. dp_rx_wds_learn(struct dp_soc *soc,
  45. struct dp_vdev *vdev,
  46. uint8_t *rx_tlv_hdr,
  47. struct dp_txrx_peer *txrx_peer,
  48. qdf_nbuf_t nbuf,
  49. struct hal_rx_msdu_metadata msdu_metadata)
  50. {
  51. /* WDS Source Port Learning */
  52. if (qdf_likely(vdev->wds_enabled))
  53. dp_rx_wds_srcport_learn(soc,
  54. rx_tlv_hdr,
  55. txrx_peer,
  56. nbuf,
  57. msdu_metadata);
  58. }
  59. #else
  60. #ifdef QCA_SUPPORT_WDS_EXTENDED
  61. /**
  62. * dp_wds_ext_peer_learn_be() - function to send event to control
  63. * path on receiving 1st 4-address frame from backhaul.
  64. * @soc: DP soc
  65. * @ta_txrx_peer: WDS repeater txrx peer
  66. * @rx_tlv_hdr : start address of rx tlvs
  67. *
  68. * Return: void
  69. */
  70. static inline void dp_wds_ext_peer_learn_be(struct dp_soc *soc,
  71. struct dp_txrx_peer *ta_txrx_peer,
  72. uint8_t *rx_tlv_hdr)
  73. {
  74. uint8_t wds_ext_src_mac[QDF_MAC_ADDR_SIZE];
  75. struct dp_peer *ta_base_peer;
  76. /* instead of checking addr4 is valid or not in per packet path
  77. * check for init bit, which will be set on reception of
  78. * first addr4 valid packet.
  79. */
  80. if (!ta_txrx_peer->vdev->wds_ext_enabled ||
  81. qdf_atomic_test_bit(WDS_EXT_PEER_INIT_BIT,
  82. &ta_txrx_peer->wds_ext.init))
  83. return;
  84. if (hal_rx_get_mpdu_mac_ad4_valid_be(rx_tlv_hdr)) {
  85. qdf_atomic_test_and_set_bit(WDS_EXT_PEER_INIT_BIT,
  86. &ta_txrx_peer->wds_ext.init);
  87. ta_base_peer = dp_peer_get_ref_by_id(soc, ta_txrx_peer->peer_id,
  88. DP_MOD_ID_RX);
  89. if (!ta_base_peer)
  90. return;
  91. qdf_mem_copy(wds_ext_src_mac, &ta_base_peer->mac_addr.raw[0],
  92. QDF_MAC_ADDR_SIZE);
  93. dp_peer_unref_delete(ta_base_peer, DP_MOD_ID_RX);
  94. soc->cdp_soc.ol_ops->rx_wds_ext_peer_learn(
  95. soc->ctrl_psoc,
  96. ta_txrx_peer->peer_id,
  97. ta_txrx_peer->vdev->vdev_id,
  98. wds_ext_src_mac);
  99. }
  100. }
  101. #else
  102. static inline void dp_wds_ext_peer_learn_be(struct dp_soc *soc,
  103. struct dp_txrx_peer *ta_txrx_peer,
  104. uint8_t *rx_tlv_hdr)
  105. {
  106. }
  107. #endif
  108. static void
  109. dp_rx_wds_learn(struct dp_soc *soc,
  110. struct dp_vdev *vdev,
  111. uint8_t *rx_tlv_hdr,
  112. struct dp_txrx_peer *ta_txrx_peer,
  113. qdf_nbuf_t nbuf,
  114. struct hal_rx_msdu_metadata msdu_metadata)
  115. {
  116. dp_wds_ext_peer_learn_be(soc, ta_txrx_peer, rx_tlv_hdr);
  117. }
  118. #endif
  119. /**
  120. * dp_rx_process_be() - Brain of the Rx processing functionality
  121. * Called from the bottom half (tasklet/NET_RX_SOFTIRQ)
  122. * @int_ctx: per interrupt context
  123. * @hal_ring: opaque pointer to the HAL Rx Ring, which will be serviced
  124. * @reo_ring_num: ring number (0, 1, 2 or 3) of the reo ring.
  125. * @quota: No. of units (packets) that can be serviced in one shot.
  126. *
  127. * This function implements the core of Rx functionality. This is
  128. * expected to handle only non-error frames.
  129. *
  130. * Return: uint32_t: No. of elements processed
  131. */
  132. uint32_t dp_rx_process_be(struct dp_intr *int_ctx,
  133. hal_ring_handle_t hal_ring_hdl, uint8_t reo_ring_num,
  134. uint32_t quota)
  135. {
  136. hal_ring_desc_t ring_desc;
  137. hal_soc_handle_t hal_soc;
  138. struct dp_rx_desc *rx_desc = NULL;
  139. qdf_nbuf_t nbuf, next;
  140. bool near_full;
  141. union dp_rx_desc_list_elem_t *head[MAX_PDEV_CNT];
  142. union dp_rx_desc_list_elem_t *tail[MAX_PDEV_CNT];
  143. uint32_t num_pending;
  144. uint32_t rx_bufs_used = 0, rx_buf_cookie;
  145. uint16_t msdu_len = 0;
  146. uint16_t peer_id;
  147. uint8_t vdev_id;
  148. struct dp_txrx_peer *txrx_peer;
  149. dp_txrx_ref_handle txrx_ref_handle = NULL;
  150. struct dp_vdev *vdev;
  151. uint32_t pkt_len = 0;
  152. struct hal_rx_mpdu_desc_info mpdu_desc_info;
  153. struct hal_rx_msdu_desc_info msdu_desc_info;
  154. enum hal_reo_error_status error;
  155. uint32_t peer_mdata;
  156. uint8_t *rx_tlv_hdr;
  157. uint32_t rx_bufs_reaped[MAX_PDEV_CNT];
  158. uint8_t mac_id = 0;
  159. struct dp_pdev *rx_pdev;
  160. bool enh_flag;
  161. struct dp_srng *dp_rxdma_srng;
  162. struct rx_desc_pool *rx_desc_pool;
  163. struct dp_soc *soc = int_ctx->soc;
  164. uint8_t core_id = 0;
  165. struct cdp_tid_rx_stats *tid_stats;
  166. qdf_nbuf_t nbuf_head;
  167. qdf_nbuf_t nbuf_tail;
  168. qdf_nbuf_t deliver_list_head;
  169. qdf_nbuf_t deliver_list_tail;
  170. uint32_t num_rx_bufs_reaped = 0;
  171. uint32_t intr_id;
  172. struct hif_opaque_softc *scn;
  173. int32_t tid = 0;
  174. bool is_prev_msdu_last = true;
  175. uint32_t num_entries_avail = 0;
  176. uint32_t rx_ol_pkt_cnt = 0;
  177. uint32_t num_entries = 0;
  178. struct hal_rx_msdu_metadata msdu_metadata;
  179. QDF_STATUS status;
  180. qdf_nbuf_t ebuf_head;
  181. qdf_nbuf_t ebuf_tail;
  182. uint8_t pkt_capture_offload = 0;
  183. struct dp_srng *rx_ring = &soc->reo_dest_ring[reo_ring_num];
  184. int max_reap_limit, ring_near_full;
  185. struct dp_soc *replenish_soc;
  186. DP_HIST_INIT();
  187. qdf_assert_always(soc && hal_ring_hdl);
  188. hal_soc = soc->hal_soc;
  189. qdf_assert_always(hal_soc);
  190. scn = soc->hif_handle;
  191. hif_pm_runtime_mark_dp_rx_busy(scn);
  192. intr_id = int_ctx->dp_intr_id;
  193. num_entries = hal_srng_get_num_entries(hal_soc, hal_ring_hdl);
  194. more_data:
  195. /* reset local variables here to be re-used in the function */
  196. nbuf_head = NULL;
  197. nbuf_tail = NULL;
  198. deliver_list_head = NULL;
  199. deliver_list_tail = NULL;
  200. txrx_peer = NULL;
  201. vdev = NULL;
  202. num_rx_bufs_reaped = 0;
  203. ebuf_head = NULL;
  204. ebuf_tail = NULL;
  205. ring_near_full = 0;
  206. max_reap_limit = dp_rx_get_loop_pkt_limit(soc);
  207. qdf_mem_zero(rx_bufs_reaped, sizeof(rx_bufs_reaped));
  208. qdf_mem_zero(&mpdu_desc_info, sizeof(mpdu_desc_info));
  209. qdf_mem_zero(&msdu_desc_info, sizeof(msdu_desc_info));
  210. qdf_mem_zero(head, sizeof(head));
  211. qdf_mem_zero(tail, sizeof(tail));
  212. ring_near_full = _dp_srng_test_and_update_nf_params(soc, rx_ring,
  213. &max_reap_limit);
  214. if (qdf_unlikely(dp_rx_srng_access_start(int_ctx, soc, hal_ring_hdl))) {
  215. /*
  216. * Need API to convert from hal_ring pointer to
  217. * Ring Type / Ring Id combo
  218. */
  219. DP_STATS_INC(soc, rx.err.hal_ring_access_fail, 1);
  220. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
  221. FL("HAL RING Access Failed -- %pK"), hal_ring_hdl);
  222. goto done;
  223. }
  224. /*
  225. * start reaping the buffers from reo ring and queue
  226. * them in per vdev queue.
  227. * Process the received pkts in a different per vdev loop.
  228. */
  229. while (qdf_likely(quota &&
  230. (ring_desc = hal_srng_dst_peek(hal_soc,
  231. hal_ring_hdl)))) {
  232. error = HAL_RX_ERROR_STATUS_GET(ring_desc);
  233. if (qdf_unlikely(error == HAL_REO_ERROR_DETECTED)) {
  234. dp_rx_err("%pK: HAL RING 0x%pK:error %d",
  235. soc, hal_ring_hdl, error);
  236. DP_STATS_INC(soc, rx.err.hal_reo_error[reo_ring_num],
  237. 1);
  238. /* Don't know how to deal with this -- assert */
  239. qdf_assert(0);
  240. }
  241. dp_rx_ring_record_entry(soc, reo_ring_num, ring_desc);
  242. rx_buf_cookie = HAL_RX_REO_BUF_COOKIE_GET(ring_desc);
  243. status = dp_rx_cookie_check_and_invalidate(ring_desc);
  244. if (qdf_unlikely(QDF_IS_STATUS_ERROR(status))) {
  245. DP_STATS_INC(soc, rx.err.stale_cookie, 1);
  246. break;
  247. }
  248. rx_desc = (struct dp_rx_desc *)
  249. hal_rx_get_reo_desc_va(ring_desc);
  250. dp_rx_desc_sw_cc_check(soc, rx_buf_cookie, &rx_desc);
  251. status = dp_rx_desc_sanity(soc, hal_soc, hal_ring_hdl,
  252. ring_desc, rx_desc);
  253. if (QDF_IS_STATUS_ERROR(status)) {
  254. if (qdf_unlikely(rx_desc && rx_desc->nbuf)) {
  255. qdf_assert_always(!rx_desc->unmapped);
  256. dp_rx_nbuf_unmap(soc, rx_desc, reo_ring_num);
  257. rx_desc->unmapped = 1;
  258. dp_rx_buffer_pool_nbuf_free(soc, rx_desc->nbuf,
  259. rx_desc->pool_id);
  260. dp_rx_add_to_free_desc_list(
  261. &head[rx_desc->pool_id],
  262. &tail[rx_desc->pool_id],
  263. rx_desc);
  264. }
  265. hal_srng_dst_get_next(hal_soc, hal_ring_hdl);
  266. continue;
  267. }
  268. /*
  269. * this is a unlikely scenario where the host is reaping
  270. * a descriptor which it already reaped just a while ago
  271. * but is yet to replenish it back to HW.
  272. * In this case host will dump the last 128 descriptors
  273. * including the software descriptor rx_desc and assert.
  274. */
  275. if (qdf_unlikely(!rx_desc->in_use)) {
  276. DP_STATS_INC(soc, rx.err.hal_reo_dest_dup, 1);
  277. dp_info_rl("Reaping rx_desc not in use!");
  278. dp_rx_dump_info_and_assert(soc, hal_ring_hdl,
  279. ring_desc, rx_desc);
  280. /* ignore duplicate RX desc and continue to process */
  281. /* Pop out the descriptor */
  282. hal_srng_dst_get_next(hal_soc, hal_ring_hdl);
  283. continue;
  284. }
  285. status = dp_rx_desc_nbuf_sanity_check(soc, ring_desc, rx_desc);
  286. if (qdf_unlikely(QDF_IS_STATUS_ERROR(status))) {
  287. DP_STATS_INC(soc, rx.err.nbuf_sanity_fail, 1);
  288. dp_info_rl("Nbuf sanity check failure!");
  289. dp_rx_dump_info_and_assert(soc, hal_ring_hdl,
  290. ring_desc, rx_desc);
  291. rx_desc->in_err_state = 1;
  292. hal_srng_dst_get_next(hal_soc, hal_ring_hdl);
  293. continue;
  294. }
  295. if (qdf_unlikely(!dp_rx_desc_check_magic(rx_desc))) {
  296. dp_err("Invalid rx_desc cookie=%d", rx_buf_cookie);
  297. DP_STATS_INC(soc, rx.err.rx_desc_invalid_magic, 1);
  298. dp_rx_dump_info_and_assert(soc, hal_ring_hdl,
  299. ring_desc, rx_desc);
  300. }
  301. /* Get MPDU DESC info */
  302. hal_rx_mpdu_desc_info_get_be(ring_desc, &mpdu_desc_info);
  303. /* Get MSDU DESC info */
  304. hal_rx_msdu_desc_info_get_be(ring_desc, &msdu_desc_info);
  305. if (qdf_unlikely(msdu_desc_info.msdu_flags &
  306. HAL_MSDU_F_MSDU_CONTINUATION)) {
  307. /* previous msdu has end bit set, so current one is
  308. * the new MPDU
  309. */
  310. if (is_prev_msdu_last) {
  311. /* Get number of entries available in HW ring */
  312. num_entries_avail =
  313. hal_srng_dst_num_valid(hal_soc,
  314. hal_ring_hdl, 1);
  315. /* For new MPDU check if we can read complete
  316. * MPDU by comparing the number of buffers
  317. * available and number of buffers needed to
  318. * reap this MPDU
  319. */
  320. if ((msdu_desc_info.msdu_len /
  321. (RX_DATA_BUFFER_SIZE -
  322. soc->rx_pkt_tlv_size) + 1) >
  323. num_entries_avail) {
  324. DP_STATS_INC(soc,
  325. rx.msdu_scatter_wait_break,
  326. 1);
  327. dp_rx_cookie_reset_invalid_bit(
  328. ring_desc);
  329. break;
  330. }
  331. is_prev_msdu_last = false;
  332. }
  333. }
  334. core_id = smp_processor_id();
  335. DP_STATS_INC(soc, rx.ring_packets[core_id][reo_ring_num], 1);
  336. if (mpdu_desc_info.mpdu_flags & HAL_MPDU_F_RETRY_BIT)
  337. qdf_nbuf_set_rx_retry_flag(rx_desc->nbuf, 1);
  338. if (qdf_unlikely(mpdu_desc_info.mpdu_flags &
  339. HAL_MPDU_F_RAW_AMPDU))
  340. qdf_nbuf_set_raw_frame(rx_desc->nbuf, 1);
  341. if (!is_prev_msdu_last &&
  342. msdu_desc_info.msdu_flags & HAL_MSDU_F_LAST_MSDU_IN_MPDU)
  343. is_prev_msdu_last = true;
  344. /* Pop out the descriptor*/
  345. hal_srng_dst_get_next(hal_soc, hal_ring_hdl);
  346. rx_bufs_reaped[rx_desc->pool_id]++;
  347. peer_mdata = mpdu_desc_info.peer_meta_data;
  348. QDF_NBUF_CB_RX_PEER_ID(rx_desc->nbuf) =
  349. dp_rx_peer_metadata_peer_id_get_be(soc, peer_mdata);
  350. QDF_NBUF_CB_RX_VDEV_ID(rx_desc->nbuf) =
  351. dp_rx_peer_metadata_vdev_id_get_be(soc, peer_mdata);
  352. /* to indicate whether this msdu is rx offload */
  353. pkt_capture_offload =
  354. DP_PEER_METADATA_OFFLOAD_GET_BE(peer_mdata);
  355. /*
  356. * save msdu flags first, last and continuation msdu in
  357. * nbuf->cb, also save mcbc, is_da_valid, is_sa_valid and
  358. * length to nbuf->cb. This ensures the info required for
  359. * per pkt processing is always in the same cache line.
  360. * This helps in improving throughput for smaller pkt
  361. * sizes.
  362. */
  363. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_FIRST_MSDU_IN_MPDU)
  364. qdf_nbuf_set_rx_chfrag_start(rx_desc->nbuf, 1);
  365. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_MSDU_CONTINUATION)
  366. qdf_nbuf_set_rx_chfrag_cont(rx_desc->nbuf, 1);
  367. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_LAST_MSDU_IN_MPDU)
  368. qdf_nbuf_set_rx_chfrag_end(rx_desc->nbuf, 1);
  369. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_DA_IS_MCBC)
  370. qdf_nbuf_set_da_mcbc(rx_desc->nbuf, 1);
  371. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_DA_IS_VALID)
  372. qdf_nbuf_set_da_valid(rx_desc->nbuf, 1);
  373. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_SA_IS_VALID)
  374. qdf_nbuf_set_sa_valid(rx_desc->nbuf, 1);
  375. if (msdu_desc_info.msdu_flags & HAL_MSDU_F_INTRA_BSS)
  376. qdf_nbuf_set_intra_bss(rx_desc->nbuf, 1);
  377. if (qdf_likely(mpdu_desc_info.mpdu_flags &
  378. HAL_MPDU_F_QOS_CONTROL_VALID))
  379. qdf_nbuf_set_tid_val(rx_desc->nbuf, mpdu_desc_info.tid);
  380. /* set sw exception */
  381. qdf_nbuf_set_rx_reo_dest_ind_or_sw_excpt(
  382. rx_desc->nbuf,
  383. hal_rx_sw_exception_get_be(ring_desc));
  384. QDF_NBUF_CB_RX_PKT_LEN(rx_desc->nbuf) = msdu_desc_info.msdu_len;
  385. QDF_NBUF_CB_RX_CTX_ID(rx_desc->nbuf) = reo_ring_num;
  386. /*
  387. * move unmap after scattered msdu waiting break logic
  388. * in case double skb unmap happened.
  389. */
  390. rx_desc_pool = &soc->rx_desc_buf[rx_desc->pool_id];
  391. dp_rx_nbuf_unmap(soc, rx_desc, reo_ring_num);
  392. rx_desc->unmapped = 1;
  393. DP_RX_PROCESS_NBUF(soc, nbuf_head, nbuf_tail, ebuf_head,
  394. ebuf_tail, rx_desc);
  395. /*
  396. * if continuation bit is set then we have MSDU spread
  397. * across multiple buffers, let us not decrement quota
  398. * till we reap all buffers of that MSDU.
  399. */
  400. if (qdf_likely(!qdf_nbuf_is_rx_chfrag_cont(rx_desc->nbuf)))
  401. quota -= 1;
  402. dp_rx_add_to_free_desc_list(&head[rx_desc->pool_id],
  403. &tail[rx_desc->pool_id], rx_desc);
  404. num_rx_bufs_reaped++;
  405. /*
  406. * only if complete msdu is received for scatter case,
  407. * then allow break.
  408. */
  409. if (is_prev_msdu_last &&
  410. dp_rx_reap_loop_pkt_limit_hit(soc, num_rx_bufs_reaped,
  411. max_reap_limit))
  412. break;
  413. }
  414. done:
  415. dp_rx_srng_access_end(int_ctx, soc, hal_ring_hdl);
  416. replenish_soc = dp_rx_replensih_soc_get(soc, reo_ring_num);
  417. for (mac_id = 0; mac_id < MAX_PDEV_CNT; mac_id++) {
  418. /*
  419. * continue with next mac_id if no pkts were reaped
  420. * from that pool
  421. */
  422. if (!rx_bufs_reaped[mac_id])
  423. continue;
  424. dp_rxdma_srng = &replenish_soc->rx_refill_buf_ring[mac_id];
  425. rx_desc_pool = &replenish_soc->rx_desc_buf[mac_id];
  426. dp_rx_buffers_replenish(replenish_soc, mac_id, dp_rxdma_srng,
  427. rx_desc_pool, rx_bufs_reaped[mac_id],
  428. &head[mac_id], &tail[mac_id]);
  429. }
  430. dp_verbose_debug("replenished %u\n", rx_bufs_reaped[0]);
  431. /* Peer can be NULL is case of LFR */
  432. if (qdf_likely(txrx_peer))
  433. vdev = NULL;
  434. /*
  435. * BIG loop where each nbuf is dequeued from global queue,
  436. * processed and queued back on a per vdev basis. These nbufs
  437. * are sent to stack as and when we run out of nbufs
  438. * or a new nbuf dequeued from global queue has a different
  439. * vdev when compared to previous nbuf.
  440. */
  441. nbuf = nbuf_head;
  442. while (nbuf) {
  443. next = nbuf->next;
  444. if (qdf_unlikely(dp_rx_is_raw_frame_dropped(nbuf))) {
  445. nbuf = next;
  446. DP_STATS_INC(soc, rx.err.raw_frm_drop, 1);
  447. continue;
  448. }
  449. rx_tlv_hdr = qdf_nbuf_data(nbuf);
  450. vdev_id = QDF_NBUF_CB_RX_VDEV_ID(nbuf);
  451. peer_id = QDF_NBUF_CB_RX_PEER_ID(nbuf);
  452. if (dp_rx_is_list_ready(deliver_list_head, vdev, txrx_peer,
  453. peer_id, vdev_id)) {
  454. dp_rx_deliver_to_stack(soc, vdev, txrx_peer,
  455. deliver_list_head,
  456. deliver_list_tail);
  457. deliver_list_head = NULL;
  458. deliver_list_tail = NULL;
  459. }
  460. /* Get TID from struct cb->tid_val, save to tid */
  461. if (qdf_nbuf_is_rx_chfrag_start(nbuf))
  462. tid = qdf_nbuf_get_tid_val(nbuf);
  463. if (qdf_unlikely(!txrx_peer)) {
  464. txrx_peer = dp_txrx_peer_get_ref_by_id(soc, peer_id,
  465. &txrx_ref_handle,
  466. DP_MOD_ID_RX);
  467. } else if (txrx_peer && txrx_peer->peer_id != peer_id) {
  468. dp_txrx_peer_unref_delete(txrx_ref_handle,
  469. DP_MOD_ID_RX);
  470. txrx_peer = dp_txrx_peer_get_ref_by_id(soc, peer_id,
  471. &txrx_ref_handle,
  472. DP_MOD_ID_RX);
  473. }
  474. if (txrx_peer) {
  475. QDF_NBUF_CB_DP_TRACE_PRINT(nbuf) = false;
  476. qdf_dp_trace_set_track(nbuf, QDF_RX);
  477. QDF_NBUF_CB_RX_DP_TRACE(nbuf) = 1;
  478. QDF_NBUF_CB_RX_PACKET_TRACK(nbuf) =
  479. QDF_NBUF_RX_PKT_DATA_TRACK;
  480. }
  481. rx_bufs_used++;
  482. if (qdf_likely(txrx_peer)) {
  483. vdev = txrx_peer->vdev;
  484. } else {
  485. nbuf->next = NULL;
  486. dp_rx_deliver_to_pkt_capture_no_peer(
  487. soc, nbuf, pkt_capture_offload);
  488. if (!pkt_capture_offload)
  489. dp_rx_deliver_to_stack_no_peer(soc, nbuf);
  490. nbuf = next;
  491. continue;
  492. }
  493. if (qdf_unlikely(!vdev)) {
  494. dp_rx_nbuf_free(nbuf);
  495. nbuf = next;
  496. DP_STATS_INC(soc, rx.err.invalid_vdev, 1);
  497. continue;
  498. }
  499. /* when hlos tid override is enabled, save tid in
  500. * skb->priority
  501. */
  502. if (qdf_unlikely(vdev->skip_sw_tid_classification &
  503. DP_TXRX_HLOS_TID_OVERRIDE_ENABLED))
  504. qdf_nbuf_set_priority(nbuf, tid);
  505. rx_pdev = vdev->pdev;
  506. DP_RX_TID_SAVE(nbuf, tid);
  507. if (qdf_unlikely(rx_pdev->delay_stats_flag) ||
  508. qdf_unlikely(wlan_cfg_is_peer_ext_stats_enabled(
  509. soc->wlan_cfg_ctx)) ||
  510. dp_rx_pkt_tracepoints_enabled())
  511. qdf_nbuf_set_timestamp(nbuf);
  512. enh_flag = rx_pdev->enhanced_stats_en;
  513. tid_stats =
  514. &rx_pdev->stats.tid_stats.tid_rx_stats[reo_ring_num][tid];
  515. /*
  516. * Check if DMA completed -- msdu_done is the last bit
  517. * to be written
  518. */
  519. if (qdf_unlikely(!qdf_nbuf_is_rx_chfrag_cont(nbuf) &&
  520. !hal_rx_tlv_msdu_done_get_be(rx_tlv_hdr))) {
  521. dp_err("MSDU DONE failure");
  522. DP_STATS_INC(soc, rx.err.msdu_done_fail, 1);
  523. hal_rx_dump_pkt_tlvs(hal_soc, rx_tlv_hdr,
  524. QDF_TRACE_LEVEL_INFO);
  525. tid_stats->fail_cnt[MSDU_DONE_FAILURE]++;
  526. dp_rx_nbuf_free(nbuf);
  527. qdf_assert(0);
  528. nbuf = next;
  529. continue;
  530. }
  531. DP_HIST_PACKET_COUNT_INC(vdev->pdev->pdev_id);
  532. /*
  533. * First IF condition:
  534. * 802.11 Fragmented pkts are reinjected to REO
  535. * HW block as SG pkts and for these pkts we only
  536. * need to pull the RX TLVS header length.
  537. * Second IF condition:
  538. * The below condition happens when an MSDU is spread
  539. * across multiple buffers. This can happen in two cases
  540. * 1. The nbuf size is smaller then the received msdu.
  541. * ex: we have set the nbuf size to 2048 during
  542. * nbuf_alloc. but we received an msdu which is
  543. * 2304 bytes in size then this msdu is spread
  544. * across 2 nbufs.
  545. *
  546. * 2. AMSDUs when RAW mode is enabled.
  547. * ex: 1st MSDU is in 1st nbuf and 2nd MSDU is spread
  548. * across 1st nbuf and 2nd nbuf and last MSDU is
  549. * spread across 2nd nbuf and 3rd nbuf.
  550. *
  551. * for these scenarios let us create a skb frag_list and
  552. * append these buffers till the last MSDU of the AMSDU
  553. * Third condition:
  554. * This is the most likely case, we receive 802.3 pkts
  555. * decapsulated by HW, here we need to set the pkt length.
  556. */
  557. hal_rx_msdu_packet_metadata_get_generic_be(rx_tlv_hdr,
  558. &msdu_metadata);
  559. if (qdf_unlikely(qdf_nbuf_is_frag(nbuf))) {
  560. bool is_mcbc, is_sa_vld, is_da_vld;
  561. is_mcbc = hal_rx_msdu_end_da_is_mcbc_get(soc->hal_soc,
  562. rx_tlv_hdr);
  563. is_sa_vld =
  564. hal_rx_msdu_end_sa_is_valid_get(soc->hal_soc,
  565. rx_tlv_hdr);
  566. is_da_vld =
  567. hal_rx_msdu_end_da_is_valid_get(soc->hal_soc,
  568. rx_tlv_hdr);
  569. qdf_nbuf_set_da_mcbc(nbuf, is_mcbc);
  570. qdf_nbuf_set_da_valid(nbuf, is_da_vld);
  571. qdf_nbuf_set_sa_valid(nbuf, is_sa_vld);
  572. qdf_nbuf_pull_head(nbuf, soc->rx_pkt_tlv_size);
  573. } else if (qdf_nbuf_is_rx_chfrag_cont(nbuf)) {
  574. msdu_len = QDF_NBUF_CB_RX_PKT_LEN(nbuf);
  575. nbuf = dp_rx_sg_create(soc, nbuf);
  576. next = nbuf->next;
  577. if (qdf_nbuf_is_raw_frame(nbuf)) {
  578. DP_STATS_INC(vdev->pdev, rx_raw_pkts, 1);
  579. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  580. rx.raw, 1,
  581. msdu_len);
  582. } else {
  583. dp_rx_nbuf_free(nbuf);
  584. DP_STATS_INC(soc, rx.err.scatter_msdu, 1);
  585. dp_info_rl("scatter msdu len %d, dropped",
  586. msdu_len);
  587. nbuf = next;
  588. continue;
  589. }
  590. } else {
  591. msdu_len = QDF_NBUF_CB_RX_PKT_LEN(nbuf);
  592. pkt_len = msdu_len +
  593. msdu_metadata.l3_hdr_pad +
  594. soc->rx_pkt_tlv_size;
  595. qdf_nbuf_set_pktlen(nbuf, pkt_len);
  596. dp_rx_skip_tlvs(soc, nbuf, msdu_metadata.l3_hdr_pad);
  597. }
  598. /*
  599. * process frame for mulitpass phrase processing
  600. */
  601. if (qdf_unlikely(vdev->multipass_en)) {
  602. if (dp_rx_multipass_process(txrx_peer, nbuf,
  603. tid) == false) {
  604. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  605. rx.multipass_rx_pkt_drop,
  606. 1);
  607. dp_rx_nbuf_free(nbuf);
  608. nbuf = next;
  609. continue;
  610. }
  611. }
  612. if (!dp_wds_rx_policy_check(rx_tlv_hdr, vdev, txrx_peer)) {
  613. dp_rx_err("%pK: Policy Check Drop pkt", soc);
  614. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  615. rx.policy_check_drop, 1);
  616. tid_stats->fail_cnt[POLICY_CHECK_DROP]++;
  617. /* Drop & free packet */
  618. dp_rx_nbuf_free(nbuf);
  619. /* Statistics */
  620. nbuf = next;
  621. continue;
  622. }
  623. if (qdf_unlikely(txrx_peer && (txrx_peer->nawds_enabled) &&
  624. (qdf_nbuf_is_da_mcbc(nbuf)) &&
  625. (hal_rx_get_mpdu_mac_ad4_valid_be(rx_tlv_hdr)
  626. == false))) {
  627. tid_stats->fail_cnt[NAWDS_MCAST_DROP]++;
  628. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  629. rx.nawds_mcast_drop, 1);
  630. dp_rx_nbuf_free(nbuf);
  631. nbuf = next;
  632. continue;
  633. }
  634. /*
  635. * Drop non-EAPOL frames from unauthorized peer.
  636. */
  637. if (qdf_likely(txrx_peer) &&
  638. qdf_unlikely(!txrx_peer->authorize) &&
  639. !qdf_nbuf_is_raw_frame(nbuf)) {
  640. bool is_eapol = qdf_nbuf_is_ipv4_eapol_pkt(nbuf) ||
  641. qdf_nbuf_is_ipv4_wapi_pkt(nbuf);
  642. if (!is_eapol) {
  643. DP_PEER_PER_PKT_STATS_INC(txrx_peer,
  644. rx.peer_unauth_rx_pkt_drop,
  645. 1);
  646. dp_rx_nbuf_free(nbuf);
  647. nbuf = next;
  648. continue;
  649. }
  650. }
  651. if (soc->process_rx_status)
  652. dp_rx_cksum_offload(vdev->pdev, nbuf, rx_tlv_hdr);
  653. /* Update the protocol tag in SKB based on CCE metadata */
  654. dp_rx_update_protocol_tag(soc, vdev, nbuf, rx_tlv_hdr,
  655. reo_ring_num, false, true);
  656. /* Update the flow tag in SKB based on FSE metadata */
  657. dp_rx_update_flow_tag(soc, vdev, nbuf, rx_tlv_hdr, true);
  658. dp_rx_msdu_stats_update(soc, nbuf, rx_tlv_hdr, txrx_peer,
  659. reo_ring_num, tid_stats);
  660. if (qdf_unlikely(vdev->mesh_vdev)) {
  661. if (dp_rx_filter_mesh_packets(vdev, nbuf, rx_tlv_hdr)
  662. == QDF_STATUS_SUCCESS) {
  663. dp_rx_info("%pK: mesh pkt filtered", soc);
  664. tid_stats->fail_cnt[MESH_FILTER_DROP]++;
  665. DP_STATS_INC(vdev->pdev, dropped.mesh_filter,
  666. 1);
  667. dp_rx_nbuf_free(nbuf);
  668. nbuf = next;
  669. continue;
  670. }
  671. dp_rx_fill_mesh_stats(vdev, nbuf, rx_tlv_hdr,
  672. txrx_peer);
  673. }
  674. if (qdf_likely(vdev->rx_decap_type ==
  675. htt_cmn_pkt_type_ethernet) &&
  676. qdf_likely(!vdev->mesh_vdev)) {
  677. dp_rx_wds_learn(soc, vdev,
  678. rx_tlv_hdr,
  679. txrx_peer,
  680. nbuf,
  681. msdu_metadata);
  682. /* Intrabss-fwd */
  683. if (dp_rx_check_ap_bridge(vdev))
  684. if (dp_rx_intrabss_fwd_be(soc, txrx_peer,
  685. rx_tlv_hdr,
  686. nbuf,
  687. msdu_metadata)) {
  688. nbuf = next;
  689. tid_stats->intrabss_cnt++;
  690. continue; /* Get next desc */
  691. }
  692. }
  693. dp_rx_fill_gro_info(soc, rx_tlv_hdr, nbuf, &rx_ol_pkt_cnt);
  694. dp_rx_mark_first_packet_after_wow_wakeup(vdev->pdev, rx_tlv_hdr,
  695. nbuf);
  696. dp_rx_update_stats(soc, nbuf);
  697. DP_RX_LIST_APPEND(deliver_list_head,
  698. deliver_list_tail,
  699. nbuf);
  700. DP_PEER_TO_STACK_INCC_PKT(txrx_peer, 1,
  701. QDF_NBUF_CB_RX_PKT_LEN(nbuf),
  702. enh_flag);
  703. if (qdf_unlikely(txrx_peer->in_twt))
  704. DP_PEER_PER_PKT_STATS_INC_PKT(txrx_peer,
  705. rx.to_stack_twt, 1,
  706. QDF_NBUF_CB_RX_PKT_LEN(nbuf));
  707. tid_stats->delivered_to_stack++;
  708. nbuf = next;
  709. }
  710. if (qdf_likely(deliver_list_head)) {
  711. if (qdf_likely(txrx_peer)) {
  712. dp_rx_deliver_to_pkt_capture(soc, vdev->pdev, peer_id,
  713. pkt_capture_offload,
  714. deliver_list_head);
  715. if (!pkt_capture_offload)
  716. dp_rx_deliver_to_stack(soc, vdev, txrx_peer,
  717. deliver_list_head,
  718. deliver_list_tail);
  719. } else {
  720. nbuf = deliver_list_head;
  721. while (nbuf) {
  722. next = nbuf->next;
  723. nbuf->next = NULL;
  724. dp_rx_deliver_to_stack_no_peer(soc, nbuf);
  725. nbuf = next;
  726. }
  727. }
  728. }
  729. if (qdf_likely(txrx_peer))
  730. dp_txrx_peer_unref_delete(txrx_ref_handle, DP_MOD_ID_RX);
  731. /*
  732. * If we are processing in near-full condition, there are 3 scenario
  733. * 1) Ring entries has reached critical state
  734. * 2) Ring entries are still near high threshold
  735. * 3) Ring entries are below the safe level
  736. *
  737. * One more loop will move the state to normal processing and yield
  738. */
  739. if (ring_near_full && quota)
  740. goto more_data;
  741. if (dp_rx_enable_eol_data_check(soc) && rx_bufs_used) {
  742. if (quota) {
  743. num_pending =
  744. dp_rx_srng_get_num_pending(hal_soc,
  745. hal_ring_hdl,
  746. num_entries,
  747. &near_full);
  748. if (num_pending) {
  749. DP_STATS_INC(soc, rx.hp_oos2, 1);
  750. if (!hif_exec_should_yield(scn, intr_id))
  751. goto more_data;
  752. if (qdf_unlikely(near_full)) {
  753. DP_STATS_INC(soc, rx.near_full, 1);
  754. goto more_data;
  755. }
  756. }
  757. }
  758. if (vdev && vdev->osif_fisa_flush)
  759. vdev->osif_fisa_flush(soc, reo_ring_num);
  760. if (vdev && vdev->osif_gro_flush && rx_ol_pkt_cnt) {
  761. vdev->osif_gro_flush(vdev->osif_vdev,
  762. reo_ring_num);
  763. }
  764. }
  765. /* Update histogram statistics by looping through pdev's */
  766. DP_RX_HIST_STATS_PER_PDEV();
  767. return rx_bufs_used; /* Assume no scale factor for now */
  768. }
  769. #ifdef RX_DESC_MULTI_PAGE_ALLOC
  770. /**
  771. * dp_rx_desc_pool_init_be_cc() - initial RX desc pool for cookie conversion
  772. * @soc: Handle to DP Soc structure
  773. * @rx_desc_pool: Rx descriptor pool handler
  774. * @pool_id: Rx descriptor pool ID
  775. *
  776. * Return: QDF_STATUS_SUCCESS - succeeded, others - failed
  777. */
  778. static QDF_STATUS
  779. dp_rx_desc_pool_init_be_cc(struct dp_soc *soc,
  780. struct rx_desc_pool *rx_desc_pool,
  781. uint32_t pool_id)
  782. {
  783. struct dp_hw_cookie_conversion_t *cc_ctx;
  784. struct dp_soc_be *be_soc;
  785. union dp_rx_desc_list_elem_t *rx_desc_elem;
  786. struct dp_spt_page_desc *page_desc;
  787. uint32_t ppt_idx = 0;
  788. uint32_t avail_entry_index = 0;
  789. if (!rx_desc_pool->pool_size) {
  790. dp_err("desc_num 0 !!");
  791. return QDF_STATUS_E_FAILURE;
  792. }
  793. be_soc = dp_get_be_soc_from_dp_soc(soc);
  794. cc_ctx = &be_soc->rx_cc_ctx[pool_id];
  795. page_desc = &cc_ctx->page_desc_base[0];
  796. rx_desc_elem = rx_desc_pool->freelist;
  797. while (rx_desc_elem) {
  798. if (avail_entry_index == 0) {
  799. if (ppt_idx >= cc_ctx->total_page_num) {
  800. dp_alert("insufficient secondary page tables");
  801. qdf_assert_always(0);
  802. }
  803. page_desc = &cc_ctx->page_desc_base[ppt_idx++];
  804. }
  805. /* put each RX Desc VA to SPT pages and
  806. * get corresponding ID
  807. */
  808. DP_CC_SPT_PAGE_UPDATE_VA(page_desc->page_v_addr,
  809. avail_entry_index,
  810. &rx_desc_elem->rx_desc);
  811. rx_desc_elem->rx_desc.cookie =
  812. dp_cc_desc_id_generate(page_desc->ppt_index,
  813. avail_entry_index);
  814. rx_desc_elem->rx_desc.pool_id = pool_id;
  815. rx_desc_elem->rx_desc.in_use = 0;
  816. rx_desc_elem = rx_desc_elem->next;
  817. avail_entry_index = (avail_entry_index + 1) &
  818. DP_CC_SPT_PAGE_MAX_ENTRIES_MASK;
  819. }
  820. return QDF_STATUS_SUCCESS;
  821. }
  822. #else
  823. static QDF_STATUS
  824. dp_rx_desc_pool_init_be_cc(struct dp_soc *soc,
  825. struct rx_desc_pool *rx_desc_pool,
  826. uint32_t pool_id)
  827. {
  828. struct dp_hw_cookie_conversion_t *cc_ctx;
  829. struct dp_soc_be *be_soc;
  830. struct dp_spt_page_desc *page_desc;
  831. uint32_t ppt_idx = 0;
  832. uint32_t avail_entry_index = 0;
  833. int i = 0;
  834. if (!rx_desc_pool->pool_size) {
  835. dp_err("desc_num 0 !!");
  836. return QDF_STATUS_E_FAILURE;
  837. }
  838. be_soc = dp_get_be_soc_from_dp_soc(soc);
  839. cc_ctx = &be_soc->rx_cc_ctx[pool_id];
  840. page_desc = &cc_ctx->page_desc_base[0];
  841. for (i = 0; i <= rx_desc_pool->pool_size - 1; i++) {
  842. if (i == rx_desc_pool->pool_size - 1)
  843. rx_desc_pool->array[i].next = NULL;
  844. else
  845. rx_desc_pool->array[i].next =
  846. &rx_desc_pool->array[i + 1];
  847. if (avail_entry_index == 0) {
  848. if (ppt_idx >= cc_ctx->total_page_num) {
  849. dp_alert("insufficient secondary page tables");
  850. qdf_assert_always(0);
  851. }
  852. page_desc = &cc_ctx->page_desc_base[ppt_idx++];
  853. }
  854. /* put each RX Desc VA to SPT pages and
  855. * get corresponding ID
  856. */
  857. DP_CC_SPT_PAGE_UPDATE_VA(page_desc->page_v_addr,
  858. avail_entry_index,
  859. &rx_desc_pool->array[i].rx_desc);
  860. rx_desc_pool->array[i].rx_desc.cookie =
  861. dp_cc_desc_id_generate(page_desc->ppt_index,
  862. avail_entry_index);
  863. rx_desc_pool->array[i].rx_desc.pool_id = pool_id;
  864. rx_desc_pool->array[i].rx_desc.in_use = 0;
  865. avail_entry_index = (avail_entry_index + 1) &
  866. DP_CC_SPT_PAGE_MAX_ENTRIES_MASK;
  867. }
  868. return QDF_STATUS_SUCCESS;
  869. }
  870. #endif
  871. static void
  872. dp_rx_desc_pool_deinit_be_cc(struct dp_soc *soc,
  873. struct rx_desc_pool *rx_desc_pool,
  874. uint32_t pool_id)
  875. {
  876. struct dp_spt_page_desc *page_desc;
  877. struct dp_soc_be *be_soc;
  878. int i = 0;
  879. struct dp_hw_cookie_conversion_t *cc_ctx;
  880. be_soc = dp_get_be_soc_from_dp_soc(soc);
  881. cc_ctx = &be_soc->rx_cc_ctx[pool_id];
  882. for (i = 0; i < cc_ctx->total_page_num; i++) {
  883. page_desc = &cc_ctx->page_desc_base[i];
  884. qdf_mem_zero(page_desc->page_v_addr, qdf_page_size);
  885. }
  886. }
  887. QDF_STATUS dp_rx_desc_pool_init_be(struct dp_soc *soc,
  888. struct rx_desc_pool *rx_desc_pool,
  889. uint32_t pool_id)
  890. {
  891. QDF_STATUS status = QDF_STATUS_SUCCESS;
  892. /* Only regular RX buffer desc pool use HW cookie conversion */
  893. if (rx_desc_pool->desc_type == DP_RX_DESC_BUF_TYPE) {
  894. dp_info("rx_desc_buf pool init");
  895. status = dp_rx_desc_pool_init_be_cc(soc,
  896. rx_desc_pool,
  897. pool_id);
  898. } else {
  899. dp_info("non_rx_desc_buf_pool init");
  900. status = dp_rx_desc_pool_init_generic(soc, rx_desc_pool,
  901. pool_id);
  902. }
  903. return status;
  904. }
  905. void dp_rx_desc_pool_deinit_be(struct dp_soc *soc,
  906. struct rx_desc_pool *rx_desc_pool,
  907. uint32_t pool_id)
  908. {
  909. if (rx_desc_pool->desc_type == DP_RX_DESC_BUF_TYPE)
  910. dp_rx_desc_pool_deinit_be_cc(soc, rx_desc_pool, pool_id);
  911. }
  912. #ifdef DP_FEATURE_HW_COOKIE_CONVERSION
  913. #ifdef DP_HW_COOKIE_CONVERT_EXCEPTION
  914. QDF_STATUS dp_wbm_get_rx_desc_from_hal_desc_be(struct dp_soc *soc,
  915. void *ring_desc,
  916. struct dp_rx_desc **r_rx_desc)
  917. {
  918. if (hal_rx_wbm_get_cookie_convert_done(ring_desc)) {
  919. /* HW cookie conversion done */
  920. *r_rx_desc = (struct dp_rx_desc *)
  921. hal_rx_wbm_get_desc_va(ring_desc);
  922. } else {
  923. /* SW do cookie conversion */
  924. uint32_t cookie = HAL_RX_BUF_COOKIE_GET(ring_desc);
  925. *r_rx_desc = (struct dp_rx_desc *)
  926. dp_cc_desc_find(soc, cookie);
  927. }
  928. return QDF_STATUS_SUCCESS;
  929. }
  930. #else
  931. QDF_STATUS dp_wbm_get_rx_desc_from_hal_desc_be(struct dp_soc *soc,
  932. void *ring_desc,
  933. struct dp_rx_desc **r_rx_desc)
  934. {
  935. *r_rx_desc = (struct dp_rx_desc *)
  936. hal_rx_wbm_get_desc_va(ring_desc);
  937. return QDF_STATUS_SUCCESS;
  938. }
  939. #endif /* DP_HW_COOKIE_CONVERT_EXCEPTION */
  940. #else
  941. QDF_STATUS dp_wbm_get_rx_desc_from_hal_desc_be(struct dp_soc *soc,
  942. void *ring_desc,
  943. struct dp_rx_desc **r_rx_desc)
  944. {
  945. /* SW do cookie conversion */
  946. uint32_t cookie = HAL_RX_BUF_COOKIE_GET(ring_desc);
  947. *r_rx_desc = (struct dp_rx_desc *)
  948. dp_cc_desc_find(soc, cookie);
  949. return QDF_STATUS_SUCCESS;
  950. }
  951. #endif /* DP_FEATURE_HW_COOKIE_CONVERSION */
  952. struct dp_rx_desc *dp_rx_desc_cookie_2_va_be(struct dp_soc *soc,
  953. uint32_t cookie)
  954. {
  955. return (struct dp_rx_desc *)dp_cc_desc_find(soc, cookie);
  956. }
  957. #if defined(WLAN_FEATURE_11BE_MLO)
  958. #if defined(WLAN_MLO_MULTI_CHIP) && defined(WLAN_MCAST_MLO)
  959. static inline void dp_rx_dummy_src_mac(qdf_nbuf_t nbuf)
  960. {
  961. qdf_ether_header_t *eh =
  962. (qdf_ether_header_t *)qdf_nbuf_data(nbuf);
  963. eh->ether_shost[0] = 0x4d; /* M */
  964. eh->ether_shost[1] = 0x4c; /* L */
  965. eh->ether_shost[2] = 0x4d; /* M */
  966. eh->ether_shost[3] = 0x43; /* C */
  967. eh->ether_shost[4] = 0x41; /* A */
  968. eh->ether_shost[5] = 0x53; /* S */
  969. }
  970. bool dp_rx_mlo_igmp_handler(struct dp_soc *soc,
  971. struct dp_vdev *vdev,
  972. struct dp_txrx_peer *peer,
  973. qdf_nbuf_t nbuf)
  974. {
  975. struct dp_vdev *mcast_primary_vdev = NULL;
  976. struct dp_vdev_be *be_vdev = dp_get_be_vdev_from_dp_vdev(vdev);
  977. struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
  978. if (!(qdf_nbuf_is_ipv4_igmp_pkt(buf) ||
  979. qdf_nbuf_is_ipv6_igmp_pkt(buf)))
  980. return false;
  981. if (vdev->mcast_enhancement_en || be_vdev->mcast_primary)
  982. goto send_pkt;
  983. mcast_primary_vdev = dp_mlo_get_mcast_primary_vdev(be_soc, be_vdev,
  984. DP_MOD_ID_RX);
  985. if (!mcast_primary_vdev) {
  986. dp_rx_debug("Non mlo vdev");
  987. goto send_pkt;
  988. }
  989. dp_rx_dummy_src_mac(nbuf);
  990. dp_rx_deliver_to_stack(mcast_primary_vdev->pdev->soc,
  991. mcast_primary_vdev,
  992. peer,
  993. nbuf,
  994. NULL);
  995. dp_vdev_unref_delete(mcast_primary_vdev->pdev->soc,
  996. mcast_primary_vdev,
  997. DP_MOD_ID_RX);
  998. return true;
  999. send_pkt:
  1000. dp_rx_deliver_to_stack(be_vdev->vdev.pdev->soc,
  1001. &be_vdev->vdev,
  1002. peer,
  1003. nbuf,
  1004. NULL);
  1005. return true;
  1006. }
  1007. #else
  1008. bool dp_rx_mlo_igmp_handler(struct dp_soc *soc,
  1009. struct dp_vdev *vdev,
  1010. struct dp_peer *peer,
  1011. qdf_nbuf_t nbuf)
  1012. {
  1013. return false;
  1014. }
  1015. #endif
  1016. #endif
  1017. #ifdef WLAN_FEATURE_NEAR_FULL_IRQ
  1018. uint32_t dp_rx_nf_process(struct dp_intr *int_ctx,
  1019. hal_ring_handle_t hal_ring_hdl,
  1020. uint8_t reo_ring_num,
  1021. uint32_t quota)
  1022. {
  1023. struct dp_soc *soc = int_ctx->soc;
  1024. struct dp_srng *rx_ring = &soc->reo_dest_ring[reo_ring_num];
  1025. uint32_t work_done = 0;
  1026. if (dp_srng_get_near_full_level(soc, rx_ring) <
  1027. DP_SRNG_THRESH_NEAR_FULL)
  1028. return 0;
  1029. qdf_atomic_set(&rx_ring->near_full, 1);
  1030. work_done++;
  1031. return work_done;
  1032. }
  1033. #endif
  1034. #ifndef QCA_HOST_MODE_WIFI_DISABLED
  1035. #ifdef WLAN_FEATURE_11BE_MLO
  1036. /**
  1037. * dp_rx_intrabss_fwd_mlo_allow() - check if MLO forwarding is allowed
  1038. * @ta_peer: transmitter peer handle
  1039. * @da_peer: destination peer handle
  1040. *
  1041. * Return: true - MLO forwarding case, false: not
  1042. */
  1043. static inline bool
  1044. dp_rx_intrabss_fwd_mlo_allow(struct dp_txrx_peer *ta_peer,
  1045. struct dp_txrx_peer *da_peer)
  1046. {
  1047. /* one of TA/DA peer should belong to MLO connection peer,
  1048. * only MLD peer type is as expected
  1049. */
  1050. if (!IS_MLO_DP_MLD_TXRX_PEER(ta_peer) &&
  1051. !IS_MLO_DP_MLD_TXRX_PEER(da_peer))
  1052. return false;
  1053. /* TA peer and DA peer's vdev should be partner MLO vdevs */
  1054. if (dp_peer_find_mac_addr_cmp(&ta_peer->vdev->mld_mac_addr,
  1055. &da_peer->vdev->mld_mac_addr))
  1056. return false;
  1057. return true;
  1058. }
  1059. #else
  1060. static inline bool
  1061. dp_rx_intrabss_fwd_mlo_allow(struct dp_txrx_peer *ta_peer,
  1062. struct dp_txrx_peer *da_peer)
  1063. {
  1064. return false;
  1065. }
  1066. #endif
  1067. #ifdef INTRA_BSS_FWD_OFFLOAD
  1068. /**
  1069. * dp_rx_intrabss_ucast_check_be() - Check if intrabss is allowed
  1070. for unicast frame
  1071. * @soc: SOC hanlde
  1072. * @nbuf: RX packet buffer
  1073. * @ta_peer: transmitter DP peer handle
  1074. * @msdu_metadata: MSDU meta data info
  1075. * @p_tx_vdev_id: get vdev id for Intra-BSS TX
  1076. *
  1077. * Return: true - intrabss allowed
  1078. false - not allow
  1079. */
  1080. static bool
  1081. dp_rx_intrabss_ucast_check_be(qdf_nbuf_t nbuf,
  1082. struct dp_txrx_peer *ta_peer,
  1083. struct hal_rx_msdu_metadata *msdu_metadata,
  1084. struct dp_be_intrabss_params *params)
  1085. {
  1086. uint16_t da_peer_id;
  1087. struct dp_txrx_peer *da_peer;
  1088. dp_txrx_ref_handle txrx_ref_handle = NULL;
  1089. if (!qdf_nbuf_is_intra_bss(nbuf))
  1090. return false;
  1091. da_peer_id = dp_rx_peer_metadata_peer_id_get_be(
  1092. params->dest_soc,
  1093. msdu_metadata->da_idx);
  1094. da_peer = dp_txrx_peer_get_ref_by_id(params->dest_soc, da_peer_id,
  1095. &txrx_ref_handle, DP_MOD_ID_RX);
  1096. if (!da_peer)
  1097. return false;
  1098. params->tx_vdev_id = da_peer->vdev->vdev_id;
  1099. dp_txrx_peer_unref_delete(txrx_ref_handle, DP_MOD_ID_RX);
  1100. return true;
  1101. }
  1102. #else
  1103. #ifdef WLAN_MLO_MULTI_CHIP
  1104. static bool
  1105. dp_rx_intrabss_ucast_check_be(qdf_nbuf_t nbuf,
  1106. struct dp_txrx_peer *ta_peer,
  1107. struct hal_rx_msdu_metadata *msdu_metadata,
  1108. struct dp_be_intrabss_params *params)
  1109. {
  1110. uint16_t da_peer_id;
  1111. struct dp_txrx_peer *da_peer;
  1112. bool ret = false;
  1113. uint8_t dest_chip_id;
  1114. uint8_t soc_idx;
  1115. dp_txrx_ref_handle txrx_ref_handle = NULL;
  1116. struct dp_vdev_be *be_vdev =
  1117. dp_get_be_vdev_from_dp_vdev(ta_peer->vdev);
  1118. struct dp_soc_be *be_soc =
  1119. dp_get_be_soc_from_dp_soc(params->dest_soc);
  1120. if (!(qdf_nbuf_is_da_valid(nbuf) || qdf_nbuf_is_da_mcbc(nbuf)))
  1121. return false;
  1122. dest_chip_id = HAL_RX_DEST_CHIP_ID_GET(msdu_metadata);
  1123. qdf_assert_always(dest_chip_id <= (DP_MLO_MAX_DEST_CHIP_ID - 1));
  1124. if (be_soc->mlo_enabled) {
  1125. /* validate chip_id, get a ref, and re-assign soc */
  1126. params->dest_soc =
  1127. dp_mlo_get_soc_ref_by_chip_id(be_soc->ml_ctxt,
  1128. dest_chip_id);
  1129. if (!params->dest_soc)
  1130. return false;
  1131. }
  1132. da_peer_id = dp_rx_peer_metadata_peer_id_get_be(params->dest_soc,
  1133. msdu_metadata->da_idx);
  1134. da_peer = dp_txrx_peer_get_ref_by_id(params->dest_soc, da_peer_id,
  1135. &txrx_ref_handle, DP_MOD_ID_RX);
  1136. if (!da_peer)
  1137. return false;
  1138. /* soc unref if needed */
  1139. params->tx_vdev_id = da_peer->vdev->vdev_id;
  1140. /* If the source or destination peer in the isolation
  1141. * list then dont forward instead push to bridge stack.
  1142. */
  1143. if (dp_get_peer_isolation(ta_peer) ||
  1144. dp_get_peer_isolation(da_peer))
  1145. goto rel_da_peer;
  1146. if (da_peer->bss_peer || da_peer == ta_peer)
  1147. goto rel_da_peer;
  1148. /* Same vdev, support Inra-BSS */
  1149. if (da_peer->vdev == ta_peer->vdev) {
  1150. ret = true;
  1151. goto rel_da_peer;
  1152. }
  1153. /* MLO specific Intra-BSS check */
  1154. if (dp_rx_intrabss_fwd_mlo_allow(ta_peer, da_peer)) {
  1155. /* index of soc in the array */
  1156. soc_idx = dest_chip_id << DP_MLO_DEST_CHIP_ID_SHIFT;
  1157. if (!(be_vdev->partner_vdev_list[soc_idx][0] ==
  1158. params->tx_vdev_id) &&
  1159. !(be_vdev->partner_vdev_list[soc_idx][1] ==
  1160. params->tx_vdev_id)) {
  1161. /*dp_soc_unref_delete(soc);*/
  1162. goto rel_da_peer;
  1163. }
  1164. ret = true;
  1165. }
  1166. rel_da_peer:
  1167. dp_txrx_peer_unref_delete(txrx_ref_handle, DP_MOD_ID_RX);
  1168. return ret;
  1169. }
  1170. #else
  1171. static bool
  1172. dp_rx_intrabss_ucast_check_be(qdf_nbuf_t nbuf,
  1173. struct dp_txrx_peer *ta_peer,
  1174. struct hal_rx_msdu_metadata *msdu_metadata,
  1175. struct dp_be_intrabss_params *params)
  1176. {
  1177. uint16_t da_peer_id;
  1178. struct dp_txrx_peer *da_peer;
  1179. bool ret = false;
  1180. dp_txrx_ref_handle txrx_ref_handle = NULL;
  1181. if (!qdf_nbuf_is_da_valid(nbuf) || qdf_nbuf_is_da_mcbc(nbuf))
  1182. return false;
  1183. da_peer_id = dp_rx_peer_metadata_peer_id_get_be(
  1184. params->dest_soc,
  1185. msdu_metadata->da_idx);
  1186. da_peer = dp_txrx_peer_get_ref_by_id(params->dest_soc, da_peer_id,
  1187. &txrx_ref_handle, DP_MOD_ID_RX);
  1188. if (!da_peer)
  1189. return false;
  1190. params->tx_vdev_id = da_peer->vdev->vdev_id;
  1191. /* If the source or destination peer in the isolation
  1192. * list then dont forward instead push to bridge stack.
  1193. */
  1194. if (dp_get_peer_isolation(ta_peer) ||
  1195. dp_get_peer_isolation(da_peer))
  1196. goto rel_da_peer;
  1197. if (da_peer->bss_peer || da_peer == ta_peer)
  1198. goto rel_da_peer;
  1199. /* Same vdev, support Inra-BSS */
  1200. if (da_peer->vdev == ta_peer->vdev) {
  1201. ret = true;
  1202. goto rel_da_peer;
  1203. }
  1204. /* MLO specific Intra-BSS check */
  1205. if (dp_rx_intrabss_fwd_mlo_allow(ta_peer, da_peer)) {
  1206. ret = true;
  1207. goto rel_da_peer;
  1208. }
  1209. rel_da_peer:
  1210. dp_txrx_peer_unref_delete(txrx_ref_handle, DP_MOD_ID_RX);
  1211. return ret;
  1212. }
  1213. #endif /* WLAN_MLO_MULTI_CHIP */
  1214. #endif /* INTRA_BSS_FWD_OFFLOAD */
  1215. /*
  1216. * dp_rx_intrabss_handle_nawds_be() - Forward mcbc intrabss pkts in nawds case
  1217. * @soc: core txrx main context
  1218. * @ta_txrx_peer: source txrx_peer entry
  1219. * @nbuf_copy: nbuf that has to be intrabss forwarded
  1220. * @tid_stats: tid_stats structure
  1221. *
  1222. * Return: true if it is forwarded else false
  1223. */
  1224. bool
  1225. dp_rx_intrabss_handle_nawds_be(struct dp_soc *soc,
  1226. struct dp_txrx_peer *ta_txrx_peer,
  1227. qdf_nbuf_t nbuf_copy,
  1228. struct cdp_tid_rx_stats *tid_stats)
  1229. {
  1230. if (qdf_unlikely(ta_txrx_peer->vdev->nawds_enabled)) {
  1231. struct cdp_tx_exception_metadata tx_exc_metadata = {0};
  1232. uint16_t len = QDF_NBUF_CB_RX_PKT_LEN(nbuf_copy);
  1233. tx_exc_metadata.peer_id = ta_txrx_peer->peer_id;
  1234. tx_exc_metadata.is_intrabss_fwd = 1;
  1235. tx_exc_metadata.tid = HTT_TX_EXT_TID_INVALID;
  1236. if (dp_tx_send_exception((struct cdp_soc_t *)soc,
  1237. ta_txrx_peer->vdev->vdev_id,
  1238. nbuf_copy,
  1239. &tx_exc_metadata)) {
  1240. DP_PEER_PER_PKT_STATS_INC_PKT(ta_txrx_peer,
  1241. rx.intra_bss.fail, 1,
  1242. len);
  1243. tid_stats->fail_cnt[INTRABSS_DROP]++;
  1244. qdf_nbuf_free(nbuf_copy);
  1245. } else {
  1246. DP_PEER_PER_PKT_STATS_INC_PKT(ta_txrx_peer,
  1247. rx.intra_bss.pkts, 1,
  1248. len);
  1249. tid_stats->intrabss_cnt++;
  1250. }
  1251. return true;
  1252. }
  1253. return false;
  1254. }
  1255. /*
  1256. * dp_rx_intrabss_fwd_be() - API for intrabss fwd. For EAPOL
  1257. * pkt with DA not equal to vdev mac addr, fwd is not allowed.
  1258. * @soc: core txrx main context
  1259. * @ta_peer: source peer entry
  1260. * @rx_tlv_hdr: start address of rx tlvs
  1261. * @nbuf: nbuf that has to be intrabss forwarded
  1262. * @msdu_metadata: msdu metadata
  1263. *
  1264. * Return: true if it is forwarded else false
  1265. */
  1266. bool dp_rx_intrabss_fwd_be(struct dp_soc *soc, struct dp_txrx_peer *ta_peer,
  1267. uint8_t *rx_tlv_hdr, qdf_nbuf_t nbuf,
  1268. struct hal_rx_msdu_metadata msdu_metadata)
  1269. {
  1270. uint8_t tid = qdf_nbuf_get_tid_val(nbuf);
  1271. uint8_t ring_id = QDF_NBUF_CB_RX_CTX_ID(nbuf);
  1272. struct cdp_tid_rx_stats *tid_stats = &ta_peer->vdev->pdev->stats.
  1273. tid_stats.tid_rx_stats[ring_id][tid];
  1274. bool ret = false;
  1275. struct dp_be_intrabss_params params;
  1276. /* if it is a broadcast pkt (eg: ARP) and it is not its own
  1277. * source, then clone the pkt and send the cloned pkt for
  1278. * intra BSS forwarding and original pkt up the network stack
  1279. * Note: how do we handle multicast pkts. do we forward
  1280. * all multicast pkts as is or let a higher layer module
  1281. * like igmpsnoop decide whether to forward or not with
  1282. * Mcast enhancement.
  1283. */
  1284. if (qdf_nbuf_is_da_mcbc(nbuf) && !ta_peer->bss_peer) {
  1285. return dp_rx_intrabss_mcbc_fwd(soc, ta_peer, rx_tlv_hdr,
  1286. nbuf, tid_stats);
  1287. }
  1288. if (dp_rx_intrabss_eapol_drop_check(soc, ta_peer, rx_tlv_hdr,
  1289. nbuf))
  1290. return true;
  1291. params.dest_soc = soc;
  1292. if (dp_rx_intrabss_ucast_check_be(nbuf, ta_peer,
  1293. &msdu_metadata, &params)) {
  1294. ret = dp_rx_intrabss_ucast_fwd(params.dest_soc, ta_peer,
  1295. params.tx_vdev_id,
  1296. rx_tlv_hdr, nbuf, tid_stats);
  1297. }
  1298. return ret;
  1299. }
  1300. #endif