Dhaval Patel c281b3a879 disp: msm: reserve core clock rate during display disable ...

Userspace module may not trigger the atomic check and it
can cause the commit failure. In such case, always reserve
the minimum core clock rate on mmrm module for built-in
displays to avoid the power ON failure.

Change-Id: Iafd92a7b7d1b35befe70b041cbedaec2add40de4
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>

2021-09-27 13:44:12 -07:00

12 KiB

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