Satya Rama Aditya Pinapala d575e0cb37 disp: msm: dsi: add HW programming for split link clock ctrl ...

There is a new clock lane that is used for the sublink when
split link is enabled. The following change adds programming
to control the sublink clock lane.

Change-Id: I1af370cd39e02130569815766fb748ae6bad72d0
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>

2021-06-14 13:09:03 -07:00

config

disp: enable qseecom hdcp for display port

2021-05-05 23:42:19 -07:00

Documentation/devicetree/bindings/drm/msm

disp: msm: dp: add dp-mst sideband simulator

2021-02-10 22:34:33 -05:00

hdcp

disp: msm: make msm_drm as module for GKI

2020-04-28 15:52:49 -07:00

include

disp: msm: add helper to retrieve gpio address mappings

2021-06-03 22:57:06 -07:00

msm

disp: msm: dsi: add HW programming for split link clock ctrl

2021-06-14 13:09:03 -07:00

rotator

Merge "disp: msm: sde: update smmu fault handler to print debug info"

2021-04-02 18:50:47 -07:00

Android.bp

display: get unifdef explicitly

2021-02-17 09:14:03 -08:00

Android.mk

display-drivers: Fix for hermetic builds

2021-05-07 12:49:37 -07:00

display_driver_board.mk

disp: enable display dlkm to be part of recovery image

2021-05-10 13:49:57 -07:00

display_driver_product.mk

disp: enable display driver compilation in vendor SI

2021-01-15 10:13:54 -08:00

display_kernel_headers.py

display: get unifdef explicitly

2021-02-17 09:14:03 -08:00

Kbuild

disp: add changes to generate display dlkm in android

2021-01-15 00:32:42 -08:00

Makefile

disp: add changes to generate display dlkm in android

2021-01-15 00:32:42 -08:00

Makefile.am

disp: msm: add Makefile.am for standalone dlkm compilation

2021-02-23 17:51:19 -08:00

NOTICE

disp: msm: dp: Move required drm_dp_link functions to downstream

2020-12-17 10:06:32 -05:00

Description

No description provided

184 MiB

Languages

C 98.7%

C++ 0.9%

Makefile 0.3%

Starlark 0.1%