3709853456
This change brings msm display driver including sde, dp, dsi, rotator, dsi pll and dp pll from base 4.19 kernel project. It is first source code snapshot from base kernel project. Change-Id: Iec864c064ce5ea04e170f24414c728684002f284 Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
546 lines
14 KiB
C
546 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2012-2019, The Linux Foundation. All rights reserved.
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*/
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#define pr_fmt(fmt) "%s: " fmt, __func__
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/delay.h>
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#include <dt-bindings/clock/mdss-28nm-pll-clk.h>
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#include "pll_drv.h"
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#include "dsi_pll.h"
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#include "dsi_pll_28nm.h"
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#define VCO_DELAY_USEC 1000
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enum {
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DSI_PLL_0,
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DSI_PLL_1,
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DSI_PLL_MAX
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};
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static struct lpfr_cfg lpfr_lut_struct[] = {
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{479500000, 8},
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{480000000, 11},
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{575500000, 8},
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{576000000, 12},
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{610500000, 8},
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{659500000, 9},
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{671500000, 10},
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{672000000, 14},
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{708500000, 10},
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{750000000, 11},
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};
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static void dsi_pll_sw_reset(struct mdss_pll_resources *rsc)
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{
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/*
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* DSI PLL software reset. Add HW recommended delays after toggling
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* the software reset bit off and back on.
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*/
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MDSS_PLL_REG_W(rsc->pll_base,
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DSI_PHY_PLL_UNIPHY_PLL_TEST_CFG, 0x01);
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ndelay(500);
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MDSS_PLL_REG_W(rsc->pll_base,
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DSI_PHY_PLL_UNIPHY_PLL_TEST_CFG, 0x00);
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}
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static void dsi_pll_toggle_lock_detect(
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struct mdss_pll_resources *rsc)
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{
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/* DSI PLL toggle lock detect setting */
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MDSS_PLL_REG_W(rsc->pll_base,
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DSI_PHY_PLL_UNIPHY_PLL_LKDET_CFG2, 0x04);
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ndelay(500);
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MDSS_PLL_REG_W(rsc->pll_base,
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DSI_PHY_PLL_UNIPHY_PLL_LKDET_CFG2, 0x05);
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udelay(512);
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}
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static int dsi_pll_check_lock_status(
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struct mdss_pll_resources *rsc)
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{
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int rc = 0;
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rc = dsi_pll_lock_status(rsc);
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if (rc)
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pr_debug("PLL Locked\n");
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else
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pr_err("PLL failed to lock\n");
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return rc;
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}
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static int dsi_pll_enable_seq_gf2(struct mdss_pll_resources *rsc)
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{
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int pll_locked = 0;
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dsi_pll_sw_reset(rsc);
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/*
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* GF PART 2 PLL power up sequence.
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* Add necessary delays recommended by hardware.
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*/
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MDSS_PLL_REG_W(rsc->pll_base,
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DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG1, 0x04);
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MDSS_PLL_REG_W(rsc->pll_base,
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DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x01);
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MDSS_PLL_REG_W(rsc->pll_base,
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DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x05);
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udelay(3);
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MDSS_PLL_REG_W(rsc->pll_base,
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DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x0f);
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udelay(500);
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dsi_pll_toggle_lock_detect(rsc);
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pll_locked = dsi_pll_check_lock_status(rsc);
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return pll_locked ? 0 : -EINVAL;
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}
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static int dsi_pll_enable_seq_gf1(struct mdss_pll_resources *rsc)
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{
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int pll_locked = 0;
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dsi_pll_sw_reset(rsc);
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/*
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* GF PART 1 PLL power up sequence.
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* Add necessary delays recommended by hardware.
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*/
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MDSS_PLL_REG_W(rsc->pll_base,
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DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG1, 0x14);
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MDSS_PLL_REG_W(rsc->pll_base,
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DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x01);
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MDSS_PLL_REG_W(rsc->pll_base,
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DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x05);
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udelay(3);
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MDSS_PLL_REG_W(rsc->pll_base,
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DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x0f);
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udelay(500);
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dsi_pll_toggle_lock_detect(rsc);
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pll_locked = dsi_pll_check_lock_status(rsc);
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return pll_locked ? 0 : -EINVAL;
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}
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static int dsi_pll_enable_seq_tsmc(struct mdss_pll_resources *rsc)
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{
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int pll_locked = 0;
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dsi_pll_sw_reset(rsc);
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/*
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* TSMC PLL power up sequence.
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* Add necessary delays recommended by hardware.
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*/
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MDSS_PLL_REG_W(rsc->pll_base,
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DSI_PHY_PLL_UNIPHY_PLL_CAL_CFG1, 0x34);
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MDSS_PLL_REG_W(rsc->pll_base,
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DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x01);
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MDSS_PLL_REG_W(rsc->pll_base,
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DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x05);
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MDSS_PLL_REG_W(rsc->pll_base,
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DSI_PHY_PLL_UNIPHY_PLL_GLB_CFG, 0x0f);
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udelay(500);
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dsi_pll_toggle_lock_detect(rsc);
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pll_locked = dsi_pll_check_lock_status(rsc);
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return pll_locked ? 0 : -EINVAL;
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}
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static struct regmap_config dsi_pll_28lpm_config = {
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.reg_bits = 32,
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.reg_stride = 4,
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.val_bits = 32,
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.max_register = 0xF4,
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};
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static struct regmap_bus analog_postdiv_regmap_bus = {
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.reg_write = analog_postdiv_reg_write,
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.reg_read = analog_postdiv_reg_read,
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};
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static struct regmap_bus byteclk_src_mux_regmap_bus = {
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.reg_write = byteclk_mux_write_sel,
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.reg_read = byteclk_mux_read_sel,
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};
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static struct regmap_bus pclk_src_regmap_bus = {
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.reg_write = pixel_clk_set_div,
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.reg_read = pixel_clk_get_div,
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};
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static const struct clk_ops clk_ops_vco_28lpm = {
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.recalc_rate = vco_28nm_recalc_rate,
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.set_rate = vco_28nm_set_rate,
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.round_rate = vco_28nm_round_rate,
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.prepare = vco_28nm_prepare,
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.unprepare = vco_28nm_unprepare,
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};
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static struct dsi_pll_vco_clk dsi0pll_vco_clk = {
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.ref_clk_rate = 19200000UL,
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.min_rate = 350000000UL,
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.max_rate = 750000000UL,
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.pll_en_seq_cnt = 9,
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.pll_enable_seqs[0] = dsi_pll_enable_seq_tsmc,
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.pll_enable_seqs[1] = dsi_pll_enable_seq_tsmc,
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.pll_enable_seqs[2] = dsi_pll_enable_seq_tsmc,
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.pll_enable_seqs[3] = dsi_pll_enable_seq_gf1,
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.pll_enable_seqs[4] = dsi_pll_enable_seq_gf1,
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.pll_enable_seqs[5] = dsi_pll_enable_seq_gf1,
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.pll_enable_seqs[6] = dsi_pll_enable_seq_gf2,
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.pll_enable_seqs[7] = dsi_pll_enable_seq_gf2,
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.pll_enable_seqs[8] = dsi_pll_enable_seq_gf2,
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.lpfr_lut_size = 10,
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.lpfr_lut = lpfr_lut_struct,
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.hw.init = &(struct clk_init_data){
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.name = "dsi0pll_vco_clk",
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.parent_names = (const char *[]){"cxo"},
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.num_parents = 1,
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.ops = &clk_ops_vco_28lpm,
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.flags = CLK_GET_RATE_NOCACHE,
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},
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};
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static struct dsi_pll_vco_clk dsi1pll_vco_clk = {
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.ref_clk_rate = 19200000UL,
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.min_rate = 350000000UL,
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.max_rate = 750000000UL,
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.pll_en_seq_cnt = 9,
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.pll_enable_seqs[0] = dsi_pll_enable_seq_tsmc,
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.pll_enable_seqs[1] = dsi_pll_enable_seq_tsmc,
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.pll_enable_seqs[2] = dsi_pll_enable_seq_tsmc,
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.pll_enable_seqs[3] = dsi_pll_enable_seq_gf1,
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.pll_enable_seqs[4] = dsi_pll_enable_seq_gf1,
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.pll_enable_seqs[5] = dsi_pll_enable_seq_gf1,
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.pll_enable_seqs[6] = dsi_pll_enable_seq_gf2,
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.pll_enable_seqs[7] = dsi_pll_enable_seq_gf2,
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.pll_enable_seqs[8] = dsi_pll_enable_seq_gf2,
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.lpfr_lut_size = 10,
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.lpfr_lut = lpfr_lut_struct,
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.hw.init = &(struct clk_init_data){
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.name = "dsi1pll_vco_clk",
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.parent_names = (const char *[]){"cxo"},
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.num_parents = 1,
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.ops = &clk_ops_vco_28lpm,
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.flags = CLK_GET_RATE_NOCACHE,
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},
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};
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static struct clk_regmap_div dsi0pll_analog_postdiv = {
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.reg = DSI_PHY_PLL_UNIPHY_PLL_POSTDIV1_CFG,
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.shift = 0,
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.width = 4,
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "dsi0pll_analog_postdiv",
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.parent_names = (const char *[]){"dsi0pll_vco_clk"},
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.num_parents = 1,
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.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
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.ops = &clk_regmap_div_ops,
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},
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},
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};
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static struct clk_regmap_div dsi1pll_analog_postdiv = {
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.reg = DSI_PHY_PLL_UNIPHY_PLL_POSTDIV1_CFG,
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.shift = 0,
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.width = 4,
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "dsi1pll_analog_postdiv",
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.parent_names = (const char *[]){"dsi1pll_vco_clk"},
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.num_parents = 1,
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.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
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.ops = &clk_regmap_div_ops,
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},
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},
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};
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static struct clk_fixed_factor dsi0pll_indirect_path_src = {
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.div = 2,
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.mult = 1,
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.hw.init = &(struct clk_init_data){
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.name = "dsi0pll_indirect_path_src",
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.parent_names = (const char *[]){"dsi0pll_analog_postdiv"},
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.num_parents = 1,
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.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
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.ops = &clk_fixed_factor_ops,
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},
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};
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static struct clk_fixed_factor dsi1pll_indirect_path_src = {
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.div = 2,
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.mult = 1,
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.hw.init = &(struct clk_init_data){
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.name = "dsi1pll_indirect_path_src",
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.parent_names = (const char *[]){"dsi1pll_analog_postdiv"},
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.num_parents = 1,
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.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
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.ops = &clk_fixed_factor_ops,
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},
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};
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static struct clk_regmap_mux dsi0pll_byteclk_src_mux = {
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.reg = DSI_PHY_PLL_UNIPHY_PLL_VREG_CFG,
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.shift = 1,
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.width = 1,
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "dsi0pll_byteclk_src_mux",
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.parent_names = (const char *[]){
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"dsi0pll_vco_clk",
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"dsi0pll_indirect_path_src"},
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.num_parents = 2,
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.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
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.ops = &clk_regmap_mux_closest_ops,
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},
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},
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};
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static struct clk_regmap_mux dsi1pll_byteclk_src_mux = {
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.reg = DSI_PHY_PLL_UNIPHY_PLL_VREG_CFG,
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.shift = 1,
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.width = 1,
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "dsi1pll_byteclk_src_mux",
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.parent_names = (const char *[]){
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"dsi1pll_vco_clk",
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"dsi1pll_indirect_path_src"},
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.num_parents = 2,
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.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
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.ops = &clk_regmap_mux_closest_ops,
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},
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},
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};
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static struct clk_fixed_factor dsi0pll_byteclk_src = {
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.div = 4,
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.mult = 1,
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.hw.init = &(struct clk_init_data){
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.name = "dsi0pll_byteclk_src",
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.parent_names = (const char *[]){
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"dsi0pll_byteclk_src_mux"},
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.num_parents = 1,
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.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
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.ops = &clk_fixed_factor_ops,
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},
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};
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static struct clk_fixed_factor dsi1pll_byteclk_src = {
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.div = 4,
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.mult = 1,
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.hw.init = &(struct clk_init_data){
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.name = "dsi1pll_byteclk_src",
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.parent_names = (const char *[]){
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"dsi1pll_byteclk_src_mux"},
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.num_parents = 1,
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.flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
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.ops = &clk_fixed_factor_ops,
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},
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};
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static struct clk_regmap_div dsi0pll_pclk_src = {
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.reg = DSI_PHY_PLL_UNIPHY_PLL_POSTDIV3_CFG,
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.shift = 0,
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.width = 8,
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "dsi0pll_pclk_src",
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.parent_names = (const char *[]){"dsi0pll_vco_clk"},
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.num_parents = 1,
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.flags = CLK_GET_RATE_NOCACHE,
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.ops = &clk_regmap_div_ops,
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},
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},
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};
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static struct clk_regmap_div dsi1pll_pclk_src = {
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.reg = DSI_PHY_PLL_UNIPHY_PLL_POSTDIV3_CFG,
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.shift = 0,
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.width = 8,
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "dsi1pll_pclk_src",
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.parent_names = (const char *[]){"dsi1pll_vco_clk"},
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.num_parents = 1,
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.flags = CLK_GET_RATE_NOCACHE,
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.ops = &clk_regmap_div_ops,
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},
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},
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};
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static struct clk_hw *mdss_dsi_pllcc_28lpm[] = {
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[VCO_CLK_0] = &dsi0pll_vco_clk.hw,
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[ANALOG_POSTDIV_0_CLK] = &dsi0pll_analog_postdiv.clkr.hw,
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[INDIRECT_PATH_SRC_0_CLK] = &dsi0pll_indirect_path_src.hw,
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[BYTECLK_SRC_MUX_0_CLK] = &dsi0pll_byteclk_src_mux.clkr.hw,
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[BYTECLK_SRC_0_CLK] = &dsi0pll_byteclk_src.hw,
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[PCLK_SRC_0_CLK] = &dsi0pll_pclk_src.clkr.hw,
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[VCO_CLK_1] = &dsi1pll_vco_clk.hw,
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[ANALOG_POSTDIV_1_CLK] = &dsi1pll_analog_postdiv.clkr.hw,
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[INDIRECT_PATH_SRC_1_CLK] = &dsi1pll_indirect_path_src.hw,
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[BYTECLK_SRC_MUX_1_CLK] = &dsi1pll_byteclk_src_mux.clkr.hw,
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[BYTECLK_SRC_1_CLK] = &dsi1pll_byteclk_src.hw,
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[PCLK_SRC_1_CLK] = &dsi1pll_pclk_src.clkr.hw,
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};
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int dsi_pll_clock_register_28lpm(struct platform_device *pdev,
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struct mdss_pll_resources *pll_res)
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{
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int rc = 0, ndx, i;
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struct clk *clk;
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struct clk_onecell_data *clk_data;
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int num_clks = ARRAY_SIZE(mdss_dsi_pllcc_28lpm);
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struct regmap *rmap;
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int const ssc_freq_min = 30000; /* min. recommended freq. value */
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int const ssc_freq_max = 33000; /* max. recommended freq. value */
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int const ssc_ppm_max = 5000; /* max. recommended ppm */
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ndx = pll_res->index;
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if (ndx >= DSI_PLL_MAX) {
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pr_err("pll index(%d) NOT supported\n", ndx);
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return -EINVAL;
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}
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pll_res->vco_delay = VCO_DELAY_USEC;
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if (pll_res->ssc_en) {
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if (!pll_res->ssc_freq || (pll_res->ssc_freq < ssc_freq_min) ||
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(pll_res->ssc_freq > ssc_freq_max)) {
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pll_res->ssc_freq = ssc_freq_min;
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pr_debug("SSC frequency out of recommended range. Set to default=%d\n",
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pll_res->ssc_freq);
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}
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if (!pll_res->ssc_ppm || (pll_res->ssc_ppm > ssc_ppm_max)) {
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pll_res->ssc_ppm = ssc_ppm_max;
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pr_debug("SSC PPM out of recommended range. Set to default=%d\n",
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pll_res->ssc_ppm);
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}
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}
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clk_data = devm_kzalloc(&pdev->dev, sizeof(*clk_data),
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GFP_KERNEL);
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if (!clk_data)
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return -ENOMEM;
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clk_data->clks = devm_kcalloc(&pdev->dev, num_clks,
|
|
sizeof(struct clk *), GFP_KERNEL);
|
|
if (!clk_data->clks)
|
|
return -ENOMEM;
|
|
|
|
clk_data->clk_num = num_clks;
|
|
|
|
/* Establish client data */
|
|
if (ndx == 0) {
|
|
rmap = devm_regmap_init(&pdev->dev, &byteclk_src_mux_regmap_bus,
|
|
pll_res, &dsi_pll_28lpm_config);
|
|
if (IS_ERR(rmap)) {
|
|
pr_err("regmap init failed for DSI clock:%d\n",
|
|
pll_res->index);
|
|
return -EINVAL;
|
|
}
|
|
dsi0pll_byteclk_src_mux.clkr.regmap = rmap;
|
|
|
|
rmap = devm_regmap_init(&pdev->dev, &analog_postdiv_regmap_bus,
|
|
pll_res, &dsi_pll_28lpm_config);
|
|
if (IS_ERR(rmap)) {
|
|
pr_err("regmap init failed for DSI clock:%d\n",
|
|
pll_res->index);
|
|
return -EINVAL;
|
|
}
|
|
dsi0pll_analog_postdiv.clkr.regmap = rmap;
|
|
|
|
rmap = devm_regmap_init(&pdev->dev, &pclk_src_regmap_bus,
|
|
pll_res, &dsi_pll_28lpm_config);
|
|
if (IS_ERR(rmap)) {
|
|
pr_err("regmap init failed for DSI clock:%d\n",
|
|
pll_res->index);
|
|
return -EINVAL;
|
|
}
|
|
dsi0pll_pclk_src.clkr.regmap = rmap;
|
|
|
|
dsi0pll_vco_clk.priv = pll_res;
|
|
for (i = VCO_CLK_0; i <= PCLK_SRC_0_CLK; i++) {
|
|
clk = devm_clk_register(&pdev->dev,
|
|
mdss_dsi_pllcc_28lpm[i]);
|
|
if (IS_ERR(clk)) {
|
|
pr_err("clk registration failed for DSI clock:%d\n",
|
|
pll_res->index);
|
|
rc = -EINVAL;
|
|
goto clk_register_fail;
|
|
}
|
|
clk_data->clks[i] = clk;
|
|
|
|
}
|
|
|
|
rc = of_clk_add_provider(pdev->dev.of_node,
|
|
of_clk_src_onecell_get, clk_data);
|
|
|
|
} else {
|
|
rmap = devm_regmap_init(&pdev->dev, &byteclk_src_mux_regmap_bus,
|
|
pll_res, &dsi_pll_28lpm_config);
|
|
if (IS_ERR(rmap)) {
|
|
pr_err("regmap init failed for DSI clock:%d\n",
|
|
pll_res->index);
|
|
return -EINVAL;
|
|
}
|
|
dsi1pll_byteclk_src_mux.clkr.regmap = rmap;
|
|
|
|
rmap = devm_regmap_init(&pdev->dev, &analog_postdiv_regmap_bus,
|
|
pll_res, &dsi_pll_28lpm_config);
|
|
if (IS_ERR(rmap)) {
|
|
pr_err("regmap init failed for DSI clock:%d\n",
|
|
pll_res->index);
|
|
return -EINVAL;
|
|
}
|
|
dsi1pll_analog_postdiv.clkr.regmap = rmap;
|
|
|
|
rmap = devm_regmap_init(&pdev->dev, &pclk_src_regmap_bus,
|
|
pll_res, &dsi_pll_28lpm_config);
|
|
if (IS_ERR(rmap)) {
|
|
pr_err("regmap init failed for DSI clock:%d\n",
|
|
pll_res->index);
|
|
return -EINVAL;
|
|
}
|
|
dsi1pll_pclk_src.clkr.regmap = rmap;
|
|
|
|
dsi1pll_vco_clk.priv = pll_res;
|
|
for (i = VCO_CLK_1; i <= PCLK_SRC_1_CLK; i++) {
|
|
clk = devm_clk_register(&pdev->dev,
|
|
mdss_dsi_pllcc_28lpm[i]);
|
|
if (IS_ERR(clk)) {
|
|
pr_err("clk registration failed for DSI clock:%d\n",
|
|
pll_res->index);
|
|
rc = -EINVAL;
|
|
goto clk_register_fail;
|
|
}
|
|
clk_data->clks[i] = clk;
|
|
|
|
}
|
|
|
|
rc = of_clk_add_provider(pdev->dev.of_node,
|
|
of_clk_src_onecell_get, clk_data);
|
|
}
|
|
if (!rc) {
|
|
pr_info("Registered DSI PLL ndx=%d, clocks successfully\n",
|
|
ndx);
|
|
|
|
return rc;
|
|
}
|
|
|
|
clk_register_fail:
|
|
return rc;
|
|
}
|