
The current pll driver models the entire DP clock hierarchy using the clock framework. This creates unnecessary dependency between the dp driver and the clock driver and also limits the flexibility to dp driver when configuring the DP clocks. This change models these clocks as single nodes and provide full control to the dp driver and also minimizes the dependency on the clock driver. Change-Id: Id5221441ea33b576e7c543396a12cbeb7b44d319 Signed-off-by: Yuan Zhao <yzhao@codeaurora.org>
1.5 KiB
1.5 KiB