
During clock switch, Pll delay is calculated considering escape clock to be in KHz. But escape clock is in Hz. This leads to wrong pll delay calculation. Change-Id: I616d16cc3d775a37e77c7c35bb860c23b1f9e37a Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
9.6 KiB
9.6 KiB