Shashank Babu Chinta Venkata 213d490593 disp: msm: dsi: fix pll lane count in split link usecase ...

In split link usecase with single DSI and dual sublink, the
pixel clock rate should  be calculated based on effective lanes
rather than cumulative lanes on that DSI PHY. This effective lanes
can be expressed as number of lanes being used per sublink.

Change-Id: Ia534e816cc64b62c5fe0b9fcaabb9ba52d05bab0
Signed-off-by: Shashank Babu Chinta Venkata <sbchin@codeaurora.org>

2021-10-27 11:50:59 -07:00

34 KiB

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