Satya Rama Aditya Pinapala 1317b11bc2 disp: msm: dsi: implement ESD recovery cleanup ...

After an ESD failure, the PHY lanes and controller can be stuck in
an unknown state. This can result in interrupt storms and watchdog
failures, if these error states are not handled correctly. The following
change implements the below mechanism to avoid failures.

1) Disable error interrupts during an ESD reg read, which are re-enabled once
ESD check is successful.
2) On ESD failure, before turning off LP clocks, reset the PHY lanes and DSI
controller.
3) After the HS clocks are turned off, issue a PHY hard reset.
4) Before enabling/disabling error interrupts, clear the error status registers
as they are not cleared as part of controller reset.

Change-Id: If10e4edf095a334a9416d109ec4b1401d1a84505
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>

2021-10-21 16:25:44 -07:00

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