0a93edbae6
Change avoids clock framework APIs to configure the DSI PHY PLL. It follows HW recommendation to set the byte and pclk dividers. Change-Id: I8c110f3997e4ec4c2eaa28778b70091855725ab8 Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
425 lines
14 KiB
C
425 lines
14 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DSI_PHY_HW_H_
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#define _DSI_PHY_HW_H_
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#include "dsi_defs.h"
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#define DSI_MAX_SETTINGS 8
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#define DSI_PHY_TIMING_V3_SIZE 12
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#define DSI_PHY_TIMING_V4_SIZE 14
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#define DSI_PHY_DBG(p, fmt, ...) DRM_DEV_DEBUG(NULL, "[msm-dsi-debug]: DSI_%d: "\
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fmt, p ? p->index : -1, ##__VA_ARGS__)
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#define DSI_PHY_ERR(p, fmt, ...) DRM_DEV_ERROR(NULL, "[msm-dsi-error]: DSI_%d: "\
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fmt, p ? p->index : -1, ##__VA_ARGS__)
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#define DSI_PHY_INFO(p, fmt, ...) DRM_DEV_INFO(NULL, "[msm-dsi-info]: DSI_%d: "\
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fmt, p ? p->index : -1, ##__VA_ARGS__)
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#define DSI_PHY_WARN(p, fmt, ...) DRM_WARN("[msm-dsi-warn]: DSI_%d: " fmt,\
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p ? p->index : -1, ##__VA_ARGS__)
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/**
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* enum dsi_phy_version - DSI PHY version enumeration
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* @DSI_PHY_VERSION_UNKNOWN: Unknown version.
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* @DSI_PHY_VERSION_0_0_HPM: 28nm-HPM.
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* @DSI_PHY_VERSION_0_0_LPM: 28nm-HPM.
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* @DSI_PHY_VERSION_1_0: 20nm
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* @DSI_PHY_VERSION_2_0: 14nm
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* @DSI_PHY_VERSION_3_0: 10nm
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* @DSI_PHY_VERSION_4_0: 7nm
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* @DSI_PHY_VERSION_4_1: 7nm
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* @DSI_PHY_VERSION_4_2: 5nm
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* @DSI_PHY_VERSION_MAX:
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*/
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enum dsi_phy_version {
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DSI_PHY_VERSION_UNKNOWN,
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DSI_PHY_VERSION_0_0_HPM, /* 28nm-HPM */
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DSI_PHY_VERSION_0_0_LPM, /* 28nm-LPM */
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DSI_PHY_VERSION_1_0, /* 20nm */
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DSI_PHY_VERSION_2_0, /* 14nm */
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DSI_PHY_VERSION_3_0, /* 10nm */
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DSI_PHY_VERSION_4_0, /* 7nm */
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DSI_PHY_VERSION_4_1, /* 7nm */
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DSI_PHY_VERSION_4_2, /* 5nm */
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DSI_PHY_VERSION_MAX
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};
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/**
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* enum dsi_pll_version - DSI PHY PLL version enumeration
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* @DSI_PLL_VERSION_5NM: 5nm PLL
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* @DSI_PLL_VERSION_10NM: 10nm PLL
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* @DSI_PLL_VERSION_UNKNOWN: Unknown PLL version
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*/
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enum dsi_pll_version {
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DSI_PLL_VERSION_5NM,
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DSI_PLL_VERSION_10NM,
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DSI_PLL_VERSION_UNKNOWN
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};
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/**
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* enum dsi_phy_hw_features - features supported by DSI PHY hardware
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* @DSI_PHY_DPHY: Supports DPHY
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* @DSI_PHY_CPHY: Supports CPHY
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* @DSI_PHY_SPLIT_LINK: Supports Split Link
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* @DSI_PHY_MAX_FEATURES:
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*/
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enum dsi_phy_hw_features {
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DSI_PHY_DPHY,
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DSI_PHY_CPHY,
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DSI_PHY_SPLIT_LINK,
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DSI_PHY_MAX_FEATURES
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};
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/**
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* enum dsi_phy_pll_source - pll clock source for PHY.
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* @DSI_PLL_SOURCE_STANDALONE: Clock is sourced from native PLL and is not
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* shared by other PHYs.
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* @DSI_PLL_SOURCE_NATIVE: Clock is sourced from native PLL and is
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* shared by other PHYs.
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* @DSI_PLL_SOURCE_NON_NATIVE: Clock is sourced from other PHYs.
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* @DSI_PLL_SOURCE_MAX:
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*/
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enum dsi_phy_pll_source {
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DSI_PLL_SOURCE_STANDALONE = 0,
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DSI_PLL_SOURCE_NATIVE,
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DSI_PLL_SOURCE_NON_NATIVE,
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DSI_PLL_SOURCE_MAX
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};
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/**
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* struct dsi_phy_per_lane_cfgs - Holds register values for PHY parameters
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* @lane: A set of maximum 8 values for each lane.
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* @lane_v3: A set of maximum 12 values for each lane.
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* @count_per_lane: Number of values per each lane.
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*/
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struct dsi_phy_per_lane_cfgs {
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u8 lane[DSI_LANE_MAX][DSI_MAX_SETTINGS];
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u8 lane_v3[DSI_PHY_TIMING_V3_SIZE];
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u8 lane_v4[DSI_PHY_TIMING_V4_SIZE];
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u32 count_per_lane;
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};
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/**
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* struct dsi_phy_cfg - DSI PHY configuration
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* @lanecfg: Lane configuration settings.
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* @strength: Strength settings for lanes.
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* @timing: Timing parameters for lanes.
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* @is_phy_timing_present: Boolean whether phy timings are defined.
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* @regulators: Regulator settings for lanes.
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* @pll_source: PLL source.
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* @lane_map: DSI logical to PHY lane mapping.
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* @force_clk_lane_hs:Boolean whether to force clock lane in HS mode.
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* @phy_type: Phy-type (Dphy/Cphy).
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* @bit_clk_rate_hz: DSI bit clk rate in HZ.
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*/
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struct dsi_phy_cfg {
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struct dsi_phy_per_lane_cfgs lanecfg;
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struct dsi_phy_per_lane_cfgs strength;
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struct dsi_phy_per_lane_cfgs timing;
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bool is_phy_timing_present;
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struct dsi_phy_per_lane_cfgs regulators;
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enum dsi_phy_pll_source pll_source;
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struct dsi_lane_map lane_map;
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bool force_clk_lane_hs;
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enum dsi_phy_type phy_type;
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unsigned long bit_clk_rate_hz;
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};
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struct dsi_phy_hw;
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struct phy_ulps_config_ops {
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/**
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* wait_for_lane_idle() - wait for DSI lanes to go to idle state
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* @phy: Pointer to DSI PHY hardware instance.
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* @lanes: ORed list of lanes (enum dsi_data_lanes) which need
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* to be checked to be in idle state.
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*/
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int (*wait_for_lane_idle)(struct dsi_phy_hw *phy, u32 lanes);
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/**
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* ulps_request() - request ulps entry for specified lanes
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* @phy: Pointer to DSI PHY hardware instance.
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* @cfg: Per lane configurations for timing, strength and lane
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* configurations.
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* @lanes: ORed list of lanes (enum dsi_data_lanes) which need
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* to enter ULPS.
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*
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* Caller should check if lanes are in ULPS mode by calling
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* get_lanes_in_ulps() operation.
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*/
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void (*ulps_request)(struct dsi_phy_hw *phy,
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struct dsi_phy_cfg *cfg, u32 lanes);
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/**
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* ulps_exit() - exit ULPS on specified lanes
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* @phy: Pointer to DSI PHY hardware instance.
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* @cfg: Per lane configurations for timing, strength and lane
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* configurations.
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* @lanes: ORed list of lanes (enum dsi_data_lanes) which need
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* to exit ULPS.
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*
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* Caller should check if lanes are in active mode by calling
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* get_lanes_in_ulps() operation.
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*/
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void (*ulps_exit)(struct dsi_phy_hw *phy,
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struct dsi_phy_cfg *cfg, u32 lanes);
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/**
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* get_lanes_in_ulps() - returns the list of lanes in ULPS mode
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* @phy: Pointer to DSI PHY hardware instance.
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*
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* Returns an ORed list of lanes (enum dsi_data_lanes) that are in ULPS
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* state.
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*
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* Return: List of lanes in ULPS state.
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*/
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u32 (*get_lanes_in_ulps)(struct dsi_phy_hw *phy);
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/**
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* is_lanes_in_ulps() - checks if the given lanes are in ulps
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* @lanes: lanes to be checked.
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* @ulps_lanes: lanes in ulps currenly.
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*
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* Return: true if all the given lanes are in ulps; false otherwise.
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*/
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bool (*is_lanes_in_ulps)(u32 ulps, u32 ulps_lanes);
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};
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struct phy_dyn_refresh_ops {
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/**
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* dyn_refresh_helper - helper function to config particular registers
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* @phy: Pointer to DSI PHY hardware instance.
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* @offset: register offset to program.
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*/
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void (*dyn_refresh_helper)(struct dsi_phy_hw *phy, u32 offset);
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/**
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* dyn_refresh_trigger_sel - configure trigger_sel to frame flush
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* @phy: Pointer to DSI PHY hardware instance.
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* @is_master: Boolean to indicate whether master or slave.
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*/
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void (*dyn_refresh_trigger_sel)(struct dsi_phy_hw *phy,
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bool is_master);
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/**
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* dyn_refresh_config - configure dynamic refresh ctrl registers
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* @phy: Pointer to DSI PHY hardware instance.
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* @cfg: Pointer to DSI PHY timings.
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* @is_master: Boolean to indicate whether for master or slave.
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*/
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void (*dyn_refresh_config)(struct dsi_phy_hw *phy,
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struct dsi_phy_cfg *cfg, bool is_master);
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/**
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* dyn_refresh_pipe_delay - configure pipe delay registers for dynamic
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* refresh.
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* @phy: Pointer to DSI PHY hardware instance.
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* @delay: structure containing all the delays to be programed.
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*/
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void (*dyn_refresh_pipe_delay)(struct dsi_phy_hw *phy,
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struct dsi_dyn_clk_delay *delay);
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/**
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* cache_phy_timings - cache the phy timings calculated as part of
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* dynamic refresh.
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* @timings: Pointer to calculated phy timing parameters.
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* @dst: Pointer to cache location.
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* @size: Number of phy lane settings.
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*/
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int (*cache_phy_timings)(struct dsi_phy_per_lane_cfgs *timings,
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u32 *dst, u32 size);
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};
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/**
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* struct dsi_phy_hw_ops - Operations for DSI PHY hardware.
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* @regulator_enable: Enable PHY regulators.
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* @regulator_disable: Disable PHY regulators.
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* @enable: Enable PHY.
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* @disable: Disable PHY.
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* @calculate_timing_params: Calculate PHY timing params from mode information
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*/
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struct dsi_phy_hw_ops {
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/**
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* regulator_enable() - enable regulators for DSI PHY
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* @phy: Pointer to DSI PHY hardware object.
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* @reg_cfg: Regulator configuration for all DSI lanes.
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*/
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void (*regulator_enable)(struct dsi_phy_hw *phy,
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struct dsi_phy_per_lane_cfgs *reg_cfg);
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/**
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* regulator_disable() - disable regulators
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* @phy: Pointer to DSI PHY hardware object.
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*/
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void (*regulator_disable)(struct dsi_phy_hw *phy);
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/**
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* enable() - Enable PHY hardware
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* @phy: Pointer to DSI PHY hardware object.
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* @cfg: Per lane configurations for timing, strength and lane
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* configurations.
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*/
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void (*enable)(struct dsi_phy_hw *phy, struct dsi_phy_cfg *cfg);
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/**
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* disable() - Disable PHY hardware
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* @phy: Pointer to DSI PHY hardware object.
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* @cfg: Per lane configurations for timing, strength and lane
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* configurations.
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*/
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void (*disable)(struct dsi_phy_hw *phy, struct dsi_phy_cfg *cfg);
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/**
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* phy_idle_on() - Enable PHY hardware when entering idle screen
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* @phy: Pointer to DSI PHY hardware object.
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* @cfg: Per lane configurations for timing, strength and lane
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* configurations.
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*/
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void (*phy_idle_on)(struct dsi_phy_hw *phy, struct dsi_phy_cfg *cfg);
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/**
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* phy_idle_off() - Disable PHY hardware when exiting idle screen
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* @phy: Pointer to DSI PHY hardware object.
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*/
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void (*phy_idle_off)(struct dsi_phy_hw *phy);
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/**
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* calculate_timing_params() - calculates timing parameters.
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* @phy: Pointer to DSI PHY hardware object.
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* @mode: Mode information for which timing has to be calculated.
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* @config: DSI host configuration for this mode.
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* @timing: Timing parameters for each lane which will be returned.
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* @use_mode_bit_clk: Boolean to indicate whether reacalculate dsi
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* bitclk or use the existing bitclk(for dynamic clk case).
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*/
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int (*calculate_timing_params)(struct dsi_phy_hw *phy,
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struct dsi_mode_info *mode,
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struct dsi_host_common_cfg *config,
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struct dsi_phy_per_lane_cfgs *timing,
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bool use_mode_bit_clk);
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/**
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* phy_timing_val() - Gets PHY timing values.
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* @timing_val: Timing parameters for each lane which will be returned.
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* @timing: Array containing PHY timing values
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* @size: Size of the array
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*/
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int (*phy_timing_val)(struct dsi_phy_per_lane_cfgs *timing_val,
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u32 *timing, u32 size);
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/**
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* clamp_ctrl() - configure clamps for DSI lanes
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* @phy: DSI PHY handle.
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* @enable: boolean to specify clamp enable/disable.
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* Return: error code.
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*/
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void (*clamp_ctrl)(struct dsi_phy_hw *phy, bool enable);
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/**
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* phy_lane_reset() - Reset dsi phy lanes in case of error.
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* @phy: Pointer to DSI PHY hardware object.
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* Return: error code.
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*/
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int (*phy_lane_reset)(struct dsi_phy_hw *phy);
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/**
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* toggle_resync_fifo() - toggle resync retime FIFO to sync data paths
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* @phy: Pointer to DSI PHY hardware object.
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* Return: error code.
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*/
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void (*toggle_resync_fifo)(struct dsi_phy_hw *phy);
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/**
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* reset_clk_en_sel() - reset clk_en_sel on phy cmn_clk_cfg1 register
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* @phy: Pointer to DSI PHY hardware object.
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*/
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void (*reset_clk_en_sel)(struct dsi_phy_hw *phy);
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/**
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* set_continuous_clk() - Set continuous clock
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* @phy: Pointer to DSI PHY hardware object
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* @enable: Bool to control continuous clock request.
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*/
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void (*set_continuous_clk)(struct dsi_phy_hw *phy, bool enable);
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/**
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* commit_phy_timing() - Commit PHY timing
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* @phy: Pointer to DSI PHY hardware object.
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* @timing: Pointer to PHY timing array
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*/
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void (*commit_phy_timing)(struct dsi_phy_hw *phy,
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struct dsi_phy_per_lane_cfgs *timing);
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void *timing_ops;
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struct phy_ulps_config_ops ulps_ops;
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struct phy_dyn_refresh_ops dyn_refresh_ops;
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/**
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* configure() - Configure the DSI PHY PLL
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* @pll: Pointer to DSI PLL.
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* @commit: boolean to specify if calculated PHY configuration
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needs to be committed. Set to false in case of
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dynamic clock switch.
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*/
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int (*configure)(void *pll, bool commit);
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/**
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* pll_toggle() - Toggle the DSI PHY PLL
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* @pll: Pointer to DSI PLL.
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* @prepare: specify if PLL needs to be turned on or off.
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*/
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int (*pll_toggle)(void *pll, bool prepare);
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};
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/**
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* struct dsi_phy_hw - DSI phy hardware object specific to an instance
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* @base: VA for the DSI PHY base address.
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* @length: Length of the DSI PHY register base map.
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* @dyn_pll_base: VA for the DSI dynamic refresh base address.
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* @length: Length of the DSI dynamic refresh register base map.
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* @index: Instance ID of the controller.
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* @version: DSI PHY version.
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* @phy_clamp_base: Base address of phy clamp register map.
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* @feature_map: Features supported by DSI PHY.
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* @ops: Function pointer to PHY operations.
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*/
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struct dsi_phy_hw {
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void __iomem *base;
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u32 length;
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void __iomem *dyn_pll_base;
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u32 dyn_refresh_len;
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u32 index;
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enum dsi_phy_version version;
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void __iomem *phy_clamp_base;
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DECLARE_BITMAP(feature_map, DSI_PHY_MAX_FEATURES);
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struct dsi_phy_hw_ops ops;
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};
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/**
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* dsi_phy_conv_phy_to_logical_lane() - Convert physical to logical lane
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* @lane_map: logical lane
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* @phy_lane: physical lane
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*
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* Return: Error code on failure. Lane number on success.
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*/
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int dsi_phy_conv_phy_to_logical_lane(
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struct dsi_lane_map *lane_map, enum dsi_phy_data_lanes phy_lane);
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/**
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* dsi_phy_conv_logical_to_phy_lane() - Convert logical to physical lane
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* @lane_map: physical lane
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* @lane: logical lane
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*
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* Return: Error code on failure. Lane number on success.
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*/
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int dsi_phy_conv_logical_to_phy_lane(
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struct dsi_lane_map *lane_map, enum dsi_logical_lane lane);
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#endif /* _DSI_PHY_HW_H_ */
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