Satya Rama Aditya Pinapala 0a93edbae6 disp: msm: dsi: rework DSI PLL to be configured within PHY ...

Change avoids clock framework APIs to configure the DSI PHY
PLL. It follows HW recommendation to set the byte and pclk
dividers.

Change-Id: I8c110f3997e4ec4c2eaa28778b70091855725ab8
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>

2021-01-12 23:49:11 -08:00

config

disp: msm: enable SDE rotator driver configs for GKI

2020-09-25 14:32:24 +05:30

hdcp

disp: msm: make msm_drm as module for GKI

2020-04-28 15:52:49 -07:00

include

disp: msm: add support to request mdp core clk through mmrm

2021-01-12 14:07:00 -08:00

msm

disp: msm: dsi: rework DSI PLL to be configured within PHY

2021-01-12 23:49:11 -08:00

rotator

disp: msm: replace PTR_RET with PTR_ERR_OR_ZERO

2020-12-17 09:58:38 -05:00

Makefile

Merge "Revert "disp: fix compilation issue with trusted VM config""

2020-07-21 13:18:32 -07:00

NOTICE

disp: msm: dp: Move required drm_dp_link functions to downstream

2020-12-17 10:06:32 -05:00

Kuvaus

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184 MiB

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