b4429e8278
In case the bus is in low power mode, the register writes (followed by a memory barrier) may take a long time (~4ms). This can cause the caller to block till the PCIe write is completed. Thus, even though PCI writes are posted, it can still block the caller. Hence, in case the bus is in low power mode (not in M0), or not in high throughput scenarios, queue the register write in a workqueue. The register write will happen in the delayed work context. In other cases, i.e ,when the bus is not in low power mode or in high thoughput scenarios, do the register writes in caller context. Change-Id: Idf218e4581545bc6ac67b91d0f70d495387ca90e CRs-Fixed: 2602029
The below qca6290 and qca8074 folder has c files defining functions and structures to hold target specific definitions to handle differences between chips with respect to hal. Please ensure changes get applied to all platform specific files if the fixes are generic and applicable to all the folders. qca6290 hal_6290_rx.c - rx related target specific function hal_6290_srng_table.c - holds hw srng table and hal hw reg offsets array hal_6290_tx.c - tx related target specific function qca8074 hal_8074_rx.c - rx related target specific function hal_8074_srng_table.c - holds hw srng table and hal hw reg offsets array hal_8074_tx.c - tx related target specific function