sde_plane.c 148 KB

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  1. /*
  2. * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
  3. * Copyright (C) 2014-2021 The Linux Foundation. All rights reserved.
  4. * Copyright (C) 2013 Red Hat
  5. * Author: Rob Clark <[email protected]>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License version 2 as published by
  9. * the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but WITHOUT
  12. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  14. * more details.
  15. *
  16. * You should have received a copy of the GNU General Public License along with
  17. * this program. If not, see <http://www.gnu.org/licenses/>.
  18. */
  19. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  20. #include <linux/debugfs.h>
  21. #include <linux/dma-buf.h>
  22. #include <drm/sde_drm.h>
  23. #include <drm/msm_drm_pp.h>
  24. #include <linux/version.h>
  25. #include <drm/drm_blend.h>
  26. #include "msm_prop.h"
  27. #include "msm_drv.h"
  28. #include "sde_kms.h"
  29. #include "sde_fence.h"
  30. #include "sde_formats.h"
  31. #include "sde_hw_sspp.h"
  32. #include "sde_hw_catalog_format.h"
  33. #include "sde_trace.h"
  34. #include "sde_crtc.h"
  35. #include "sde_vbif.h"
  36. #include "sde_plane.h"
  37. #include "sde_color_processing.h"
  38. #define SDE_DEBUG_PLANE(pl, fmt, ...) SDE_DEBUG("plane%d " fmt,\
  39. (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
  40. #define SDE_ERROR_PLANE(pl, fmt, ...) SDE_ERROR("plane%d " fmt,\
  41. (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
  42. #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci))
  43. #define PHASE_STEP_SHIFT 21
  44. #define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT))
  45. #define PHASE_RESIDUAL 15
  46. #define SHARP_STRENGTH_DEFAULT 32
  47. #define SHARP_EDGE_THR_DEFAULT 112
  48. #define SHARP_SMOOTH_THR_DEFAULT 8
  49. #define SHARP_NOISE_THR_DEFAULT 2
  50. #define SDE_NAME_SIZE 12
  51. #define SDE_PLANE_COLOR_FILL_FLAG BIT(31)
  52. #define TIME_MULTIPLEX_RECT(r0, r1, buffer_lines) \
  53. ((r0).y >= ((r1).y + (r1).h + buffer_lines))
  54. #define SDE_QSEED_DEFAULT_DYN_EXP 0x0
  55. /**
  56. * enum sde_plane_qos - Different qos configurations for each pipe
  57. *
  58. * @SDE_PLANE_QOS_VBLANK_CTRL: Setup VBLANK qos for the pipe.
  59. * @SDE_PLANE_QOS_VBLANK_AMORTIZE: Enables Amortization within pipe.
  60. * this configuration is mutually exclusive from VBLANK_CTRL.
  61. * @SDE_PLANE_QOS_PANIC_CTRL: Setup panic for the pipe.
  62. */
  63. enum sde_plane_qos {
  64. SDE_PLANE_QOS_VBLANK_CTRL = BIT(0),
  65. SDE_PLANE_QOS_VBLANK_AMORTIZE = BIT(1),
  66. SDE_PLANE_QOS_PANIC_CTRL = BIT(2),
  67. };
  68. static int plane_prop_array[PLANE_PROP_COUNT] = {SDE_PLANE_DIRTY_ALL};
  69. static struct sde_kms *_sde_plane_get_kms(struct drm_plane *plane)
  70. {
  71. struct msm_drm_private *priv;
  72. if (!plane || !plane->dev)
  73. return NULL;
  74. priv = plane->dev->dev_private;
  75. if (!priv)
  76. return NULL;
  77. return to_sde_kms(priv->kms);
  78. }
  79. static struct sde_hw_ctl *_sde_plane_get_hw_ctl(const struct drm_plane *plane)
  80. {
  81. struct drm_plane_state *pstate = NULL;
  82. struct drm_crtc *drm_crtc = NULL;
  83. struct sde_crtc *sde_crtc = NULL;
  84. struct sde_crtc_mixer *mixer = NULL;
  85. struct sde_hw_ctl *ctl = NULL;
  86. if (!plane) {
  87. DRM_ERROR("Invalid plane %pK\n", plane);
  88. return NULL;
  89. }
  90. pstate = plane->state;
  91. if (!pstate) {
  92. DRM_ERROR("Invalid plane state %pK\n", pstate);
  93. return NULL;
  94. }
  95. drm_crtc = pstate->crtc;
  96. if (!drm_crtc) {
  97. DRM_ERROR("Invalid drm_crtc %pK\n", drm_crtc);
  98. return NULL;
  99. }
  100. sde_crtc = to_sde_crtc(drm_crtc);
  101. if (!sde_crtc) {
  102. DRM_ERROR("invalid sde_crtc %pK\n", sde_crtc);
  103. return NULL;
  104. }
  105. /* it will always return the first mixer and single CTL */
  106. mixer = sde_crtc->mixers;
  107. if (!mixer) {
  108. DRM_ERROR("invalid mixer %pK\n", mixer);
  109. return NULL;
  110. }
  111. ctl = mixer->hw_ctl;
  112. if (!mixer) {
  113. DRM_ERROR("invalid ctl %pK\n", ctl);
  114. return NULL;
  115. }
  116. return ctl;
  117. }
  118. static void _sde_plane_setup_panel_stacking(struct sde_plane *psde,
  119. struct sde_plane_state *pstate)
  120. {
  121. struct sde_hw_pipe_line_insertion_cfg *cfg;
  122. struct sde_crtc_state *cstate;
  123. u32 h_start = 0, h_total = 0, y_start = 0;
  124. struct drm_plane_state *dpstate = NULL;
  125. struct drm_crtc *drm_crtc = NULL;
  126. if (!psde || !psde->base.state || !psde->base.state->crtc) {
  127. SDE_ERROR("Invalid plane psde %p or drm plane state or drm crtc\n", psde);
  128. return;
  129. }
  130. dpstate = psde->base.state;
  131. drm_crtc = dpstate->crtc;
  132. cstate = to_sde_crtc_state(drm_crtc->state);
  133. pstate->lineinsertion_feature = cstate->line_insertion.panel_line_insertion_enable;
  134. if ((!test_bit(SDE_SSPP_LINE_INSERTION, (unsigned long *)&psde->features)) ||
  135. !cstate->line_insertion.panel_line_insertion_enable)
  136. return;
  137. cfg = &pstate->line_insertion_cfg;
  138. memset(cfg, 0, sizeof(*cfg));
  139. if (!cstate->line_insertion.padding_height)
  140. return;
  141. sde_crtc_calc_vpadding_param(psde->base.state->crtc->state,
  142. pstate->base.crtc_y, pstate->base.crtc_h,
  143. &y_start, &h_start, &h_total);
  144. cfg->enable = true;
  145. cfg->dummy_lines = cstate->line_insertion.padding_dummy;
  146. cfg->active_lines = cstate->line_insertion.padding_active;
  147. cfg->first_active_lines = h_start;
  148. cfg->dst_h = h_total;
  149. psde->pipe_cfg.dst_rect.y += y_start - pstate->base.crtc_y;
  150. }
  151. static bool sde_plane_enabled(const struct drm_plane_state *state)
  152. {
  153. return state && state->fb && state->crtc;
  154. }
  155. bool sde_plane_is_sec_ui_allowed(struct drm_plane *plane)
  156. {
  157. struct sde_plane *psde;
  158. if (!plane)
  159. return false;
  160. psde = to_sde_plane(plane);
  161. return !(psde->features & BIT(SDE_SSPP_BLOCK_SEC_UI));
  162. }
  163. void sde_plane_setup_src_split_order(struct drm_plane *plane,
  164. enum sde_sspp_multirect_index rect_mode, bool enable)
  165. {
  166. struct sde_plane *psde;
  167. if (!plane)
  168. return;
  169. psde = to_sde_plane(plane);
  170. if (psde->pipe_hw->ops.set_src_split_order)
  171. psde->pipe_hw->ops.set_src_split_order(psde->pipe_hw,
  172. rect_mode, enable);
  173. }
  174. void sde_plane_set_sid(struct drm_plane *plane, u32 vm)
  175. {
  176. struct sde_plane *psde;
  177. struct sde_kms *sde_kms;
  178. struct msm_drm_private *priv;
  179. if (!plane || !plane->dev) {
  180. SDE_ERROR("invalid plane\n");
  181. return;
  182. }
  183. priv = plane->dev->dev_private;
  184. if (!priv || !priv->kms) {
  185. SDE_ERROR("invalid KMS reference\n");
  186. return;
  187. }
  188. sde_kms = to_sde_kms(priv->kms);
  189. psde = to_sde_plane(plane);
  190. sde_hw_set_sspp_sid(sde_kms->hw_sid, psde->pipe, vm, sde_kms->catalog);
  191. }
  192. static void _sde_plane_set_qos_lut(struct drm_plane *plane,
  193. struct drm_crtc *crtc,
  194. struct drm_framebuffer *fb)
  195. {
  196. struct sde_plane *psde;
  197. const struct sde_format *fmt = NULL;
  198. u32 frame_rate, qos_count, fps_index = 0, lut_index, creq_lut_index, ds_lut_index;
  199. struct sde_perf_cfg *perf;
  200. struct sde_plane_state *pstate;
  201. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  202. bool inline_rot = false, landscape = false;
  203. struct drm_display_mode *mode;
  204. u32 fl_require0 = 0;
  205. if (!plane || !fb) {
  206. SDE_ERROR("invalid arguments\n");
  207. return;
  208. }
  209. psde = to_sde_plane(plane);
  210. pstate = to_sde_plane_state(plane->state);
  211. if (!psde->pipe_hw || !psde->pipe_sblk || !psde->catalog) {
  212. SDE_ERROR("invalid arguments\n");
  213. return;
  214. } else if (!psde->pipe_hw->ops.setup_qos_lut) {
  215. return;
  216. }
  217. mode = &crtc->state->adjusted_mode;
  218. landscape = mode->hdisplay > mode->vdisplay ? true : false;
  219. frame_rate = drm_mode_vrefresh(&crtc->mode);
  220. perf = &psde->catalog->perf;
  221. qos_count = perf->qos_refresh_count;
  222. while ((fps_index < qos_count) && perf->qos_refresh_rate) {
  223. if ((frame_rate <= perf->qos_refresh_rate[fps_index]) ||
  224. (fps_index == qos_count - 1))
  225. break;
  226. fps_index++;
  227. }
  228. if (psde->is_rt_pipe) {
  229. fmt = sde_get_sde_format_ext(fb->format->format, fb->modifier);
  230. inline_rot = (pstate->rotation & DRM_MODE_ROTATE_90);
  231. if (inline_rot && SDE_IS_IN_ROT_RESTRICTED_FMT(psde->catalog, fmt))
  232. lut_index = SDE_QOS_LUT_USAGE_INLINE_RESTRICTED_FMTS;
  233. else if (inline_rot)
  234. lut_index = SDE_QOS_LUT_USAGE_INLINE;
  235. else if (fmt && SDE_FORMAT_IS_LINEAR(fmt))
  236. lut_index = SDE_QOS_LUT_USAGE_LINEAR;
  237. else
  238. lut_index = SDE_QOS_LUT_USAGE_MACROTILE;
  239. } else {
  240. lut_index = (psde->wb_usage_type == WB_USAGE_OFFLINE_WB ||
  241. psde->wb_usage_type == WB_USAGE_ROT) ?
  242. SDE_QOS_LUT_USAGE_OFFLINE_WB : SDE_QOS_LUT_USAGE_NRT;
  243. }
  244. creq_lut_index = lut_index * SDE_CREQ_LUT_TYPE_MAX;
  245. if (psde->scaler3_cfg.enable)
  246. creq_lut_index += SDE_CREQ_LUT_TYPE_QSEED;
  247. creq_lut_index += (fps_index * SDE_QOS_LUT_USAGE_MAX * SDE_CREQ_LUT_TYPE_MAX);
  248. psde->pipe_qos_cfg.creq_lut = perf->creq_lut[creq_lut_index];
  249. ds_lut_index = lut_index * SDE_DANGER_SAFE_LUT_TYPE_MAX;
  250. if (landscape) {
  251. if (psde->catalog->qos_target_time_ns && sde_crtc->line_time_in_ns)
  252. fl_require0 = psde->catalog->qos_target_time_ns /
  253. (sde_crtc->line_time_in_ns * 2);
  254. if (!fl_require0 || fl_require0 < 4.5)
  255. ds_lut_index += SDE_DANGER_SAFE_LUT_TYPE_LANDSCAPE;
  256. }
  257. ds_lut_index += (fps_index * SDE_QOS_LUT_USAGE_MAX * SDE_DANGER_SAFE_LUT_TYPE_MAX);
  258. psde->pipe_qos_cfg.danger_lut = perf->danger_lut[ds_lut_index];
  259. psde->pipe_qos_cfg.safe_lut = perf->safe_lut[ds_lut_index];
  260. trace_sde_perf_set_qos_luts(psde->pipe - SSPP_VIG0, (fmt) ? fmt->base.pixel_format : 0,
  261. (fmt) ? fmt->fetch_mode : 0, psde->pipe_qos_cfg.danger_lut,
  262. psde->pipe_qos_cfg.safe_lut, psde->pipe_qos_cfg.creq_lut);
  263. SDE_DEBUG("plane%u: pnum:%d fmt:%4.4s fps:%d mode:%d lut[0x%x,0x%x 0x%llx] rt:%d type:%d\n",
  264. plane->base.id, psde->pipe - SSPP_VIG0,
  265. fmt ? (char *)&fmt->base.pixel_format : NULL, frame_rate,
  266. fmt ? fmt->fetch_mode : -1, psde->pipe_qos_cfg.danger_lut,
  267. psde->pipe_qos_cfg.safe_lut, psde->pipe_qos_cfg.creq_lut,
  268. psde->is_rt_pipe, psde->wb_usage_type);
  269. psde->pipe_hw->ops.setup_qos_lut(psde->pipe_hw, &psde->pipe_qos_cfg);
  270. }
  271. /**
  272. * _sde_plane_set_qos_ctrl - set QoS control of the given plane
  273. * @plane: Pointer to drm plane
  274. * @enable: true to enable QoS control
  275. * @flags: QoS control mode (enum sde_plane_qos)
  276. */
  277. static void _sde_plane_set_qos_ctrl(struct drm_plane *plane,
  278. bool enable, u32 flags)
  279. {
  280. struct sde_plane *psde;
  281. if (!plane) {
  282. SDE_ERROR("invalid arguments\n");
  283. return;
  284. }
  285. psde = to_sde_plane(plane);
  286. if (!psde->pipe_hw || !psde->pipe_sblk) {
  287. SDE_ERROR("invalid arguments\n");
  288. return;
  289. } else if (!psde->pipe_hw->ops.setup_qos_ctrl) {
  290. return;
  291. }
  292. if (flags & SDE_PLANE_QOS_VBLANK_CTRL) {
  293. psde->pipe_qos_cfg.creq_vblank = psde->pipe_sblk->creq_vblank;
  294. psde->pipe_qos_cfg.danger_vblank =
  295. psde->pipe_sblk->danger_vblank;
  296. psde->pipe_qos_cfg.vblank_en = enable;
  297. }
  298. if (flags & SDE_PLANE_QOS_VBLANK_AMORTIZE) {
  299. /* this feature overrules previous VBLANK_CTRL */
  300. psde->pipe_qos_cfg.vblank_en = false;
  301. psde->pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */
  302. psde->pipe_qos_cfg.danger_vblank = 0;
  303. }
  304. if (flags & SDE_PLANE_QOS_PANIC_CTRL)
  305. psde->pipe_qos_cfg.danger_safe_en = enable;
  306. if (!psde->is_rt_pipe) {
  307. psde->pipe_qos_cfg.vblank_en = false;
  308. psde->pipe_qos_cfg.danger_safe_en = false;
  309. }
  310. SDE_DEBUG("plane%u: pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n",
  311. plane->base.id,
  312. psde->pipe - SSPP_VIG0,
  313. psde->pipe_qos_cfg.danger_safe_en,
  314. psde->pipe_qos_cfg.vblank_en,
  315. psde->pipe_qos_cfg.creq_vblank,
  316. psde->pipe_qos_cfg.danger_vblank,
  317. psde->is_rt_pipe);
  318. psde->pipe_hw->ops.setup_qos_ctrl(psde->pipe_hw,
  319. &psde->pipe_qos_cfg);
  320. }
  321. void sde_plane_set_revalidate(struct drm_plane *plane, bool enable)
  322. {
  323. struct sde_plane *psde;
  324. if (!plane)
  325. return;
  326. psde = to_sde_plane(plane);
  327. psde->revalidate = enable;
  328. }
  329. int sde_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
  330. {
  331. struct sde_plane *psde;
  332. int rc;
  333. if (!plane) {
  334. SDE_ERROR("invalid arguments\n");
  335. return -EINVAL;
  336. }
  337. psde = to_sde_plane(plane);
  338. if (!psde->is_rt_pipe)
  339. goto end;
  340. rc = pm_runtime_resume_and_get(plane->dev->dev);
  341. if (rc < 0) {
  342. SDE_ERROR("failed to enable power resource %d\n", rc);
  343. SDE_EVT32(rc, SDE_EVTLOG_ERROR);
  344. return rc;
  345. }
  346. _sde_plane_set_qos_ctrl(plane, enable, SDE_PLANE_QOS_PANIC_CTRL);
  347. pm_runtime_put_sync(plane->dev->dev);
  348. end:
  349. return 0;
  350. }
  351. /**
  352. * _sde_plane_set_ot_limit - set OT limit for the given plane
  353. * @plane: Pointer to drm plane
  354. * @crtc: Pointer to drm crtc
  355. */
  356. static void _sde_plane_set_ot_limit(struct drm_plane *plane,
  357. struct drm_crtc *crtc)
  358. {
  359. struct sde_plane *psde;
  360. struct sde_vbif_set_ot_params ot_params;
  361. struct msm_drm_private *priv;
  362. struct sde_kms *sde_kms;
  363. if (!plane || !plane->dev || !crtc) {
  364. SDE_ERROR("invalid arguments plane %d crtc %d\n",
  365. !plane, !crtc);
  366. return;
  367. }
  368. priv = plane->dev->dev_private;
  369. if (!priv || !priv->kms) {
  370. SDE_ERROR("invalid KMS reference\n");
  371. return;
  372. }
  373. sde_kms = to_sde_kms(priv->kms);
  374. psde = to_sde_plane(plane);
  375. if (!psde->pipe_hw) {
  376. SDE_ERROR("invalid pipe reference\n");
  377. return;
  378. }
  379. memset(&ot_params, 0, sizeof(ot_params));
  380. ot_params.xin_id = psde->pipe_hw->cap->xin_id;
  381. ot_params.num = psde->pipe_hw->idx - SSPP_NONE;
  382. ot_params.width = psde->pipe_cfg.src_rect.w;
  383. ot_params.height = psde->pipe_cfg.src_rect.h;
  384. ot_params.is_wfd = ((psde->is_rt_pipe)
  385. || (psde->wb_usage_type == WB_USAGE_OFFLINE_WB)) ? false : true;
  386. ot_params.frame_rate = drm_mode_vrefresh(&crtc->mode);
  387. ot_params.vbif_idx = VBIF_RT;
  388. ot_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  389. ot_params.rd = true;
  390. sde_vbif_set_ot_limit(sde_kms, &ot_params);
  391. }
  392. /**
  393. * _sde_plane_set_vbif_qos - set vbif QoS for the given plane
  394. * @plane: Pointer to drm plane
  395. */
  396. static void _sde_plane_set_qos_remap(struct drm_plane *plane)
  397. {
  398. struct sde_plane *psde;
  399. struct sde_vbif_set_qos_params qos_params;
  400. struct msm_drm_private *priv;
  401. struct sde_kms *sde_kms;
  402. if (!plane || !plane->dev) {
  403. SDE_ERROR("invalid arguments\n");
  404. return;
  405. }
  406. priv = plane->dev->dev_private;
  407. if (!priv || !priv->kms) {
  408. SDE_ERROR("invalid KMS reference\n");
  409. return;
  410. }
  411. sde_kms = to_sde_kms(priv->kms);
  412. psde = to_sde_plane(plane);
  413. if (!psde->pipe_hw) {
  414. SDE_ERROR("invalid pipe reference\n");
  415. return;
  416. }
  417. memset(&qos_params, 0, sizeof(qos_params));
  418. qos_params.vbif_idx = VBIF_RT;
  419. qos_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  420. qos_params.xin_id = psde->pipe_hw->cap->xin_id;
  421. qos_params.num = psde->pipe_hw->idx - SSPP_VIG0;
  422. if (psde->is_rt_pipe)
  423. qos_params.client_type = VBIF_RT_CLIENT;
  424. else
  425. qos_params.client_type = (psde->wb_usage_type == WB_USAGE_OFFLINE_WB) ?
  426. VBIF_OFFLINE_WB_CLIENT : VBIF_NRT_CLIENT;
  427. SDE_DEBUG("plane%d pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n",
  428. plane->base.id, qos_params.num,
  429. qos_params.vbif_idx,
  430. qos_params.xin_id, qos_params.client_type,
  431. qos_params.clk_ctrl);
  432. sde_vbif_set_qos_remap(sde_kms, &qos_params);
  433. }
  434. /**
  435. * _sde_plane_set_ts_prefill - set prefill with traffic shaper
  436. * @plane: Pointer to drm plane
  437. * @pstate: Pointer to sde plane state
  438. */
  439. static void _sde_plane_set_ts_prefill(struct drm_plane *plane,
  440. struct sde_plane_state *pstate)
  441. {
  442. struct sde_plane *psde;
  443. struct sde_hw_pipe_ts_cfg cfg;
  444. struct msm_drm_private *priv;
  445. struct sde_kms *sde_kms;
  446. if (!plane || !plane->dev) {
  447. SDE_ERROR("invalid arguments");
  448. return;
  449. }
  450. priv = plane->dev->dev_private;
  451. if (!priv || !priv->kms) {
  452. SDE_ERROR("invalid KMS reference\n");
  453. return;
  454. }
  455. sde_kms = to_sde_kms(priv->kms);
  456. psde = to_sde_plane(plane);
  457. if (!psde->pipe_hw) {
  458. SDE_ERROR("invalid pipe reference\n");
  459. return;
  460. }
  461. if (!psde->pipe_hw || !psde->pipe_hw->ops.setup_ts_prefill)
  462. return;
  463. _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_VBLANK_AMORTIZE);
  464. memset(&cfg, 0, sizeof(cfg));
  465. cfg.size = sde_plane_get_property(pstate,
  466. PLANE_PROP_PREFILL_SIZE);
  467. cfg.time = sde_plane_get_property(pstate,
  468. PLANE_PROP_PREFILL_TIME);
  469. SDE_DEBUG("plane%d size:%llu time:%llu\n",
  470. plane->base.id, cfg.size, cfg.time);
  471. SDE_EVT32_VERBOSE(DRMID(plane), cfg.size, cfg.time);
  472. psde->pipe_hw->ops.setup_ts_prefill(psde->pipe_hw, &cfg,
  473. pstate->multirect_index);
  474. }
  475. /* helper to update a state's input fence pointer from the property */
  476. static void _sde_plane_set_input_fence(struct sde_plane *psde,
  477. struct sde_plane_state *pstate, uint64_t fd)
  478. {
  479. if (!psde || !pstate) {
  480. SDE_ERROR("invalid arg(s), plane %d state %d\n",
  481. !psde, !pstate);
  482. return;
  483. }
  484. /* clear previous reference */
  485. if (pstate->input_fence)
  486. sde_sync_put(pstate->input_fence);
  487. /* get fence pointer for later */
  488. if (fd == 0)
  489. pstate->input_fence = NULL;
  490. else
  491. pstate->input_fence = sde_sync_get(fd);
  492. SDE_DEBUG_PLANE(psde, "0x%llX\n", fd);
  493. }
  494. void sde_plane_dump_input_fence(struct drm_plane *plane)
  495. {
  496. struct sde_plane *psde;
  497. struct sde_plane_state *pstate;
  498. void *input_fence;
  499. if (!plane) {
  500. SDE_ERROR("invalid plane\n");
  501. } else if (!plane->state) {
  502. SDE_ERROR_PLANE(to_sde_plane(plane), "invalid state\n");
  503. } else {
  504. psde = to_sde_plane(plane);
  505. pstate = to_sde_plane_state(plane->state);
  506. input_fence = pstate->input_fence;
  507. if (input_fence)
  508. sde_fence_dump(input_fence);
  509. }
  510. }
  511. bool sde_plane_is_sw_fence_signaled(struct drm_plane *plane)
  512. {
  513. struct sde_plane *psde;
  514. struct sde_plane_state *pstate;
  515. struct dma_fence *fence;
  516. if (!plane) {
  517. SDE_ERROR("invalid plane\n");
  518. } else if (!plane->state) {
  519. SDE_ERROR_PLANE(to_sde_plane(plane), "invalid state\n");
  520. } else {
  521. psde = to_sde_plane(plane);
  522. pstate = to_sde_plane_state(plane->state);
  523. if (pstate->input_fence) {
  524. fence = (struct dma_fence *)pstate->input_fence;
  525. return dma_fence_is_signaled(fence);
  526. }
  527. }
  528. return false;
  529. }
  530. int sde_plane_wait_input_fence(struct drm_plane *plane, uint32_t wait_ms)
  531. {
  532. struct sde_plane *psde;
  533. struct sde_plane_state *pstate;
  534. uint32_t prefix;
  535. void *input_fence;
  536. int ret = -EINVAL;
  537. signed long rc;
  538. if (!plane) {
  539. SDE_ERROR("invalid plane\n");
  540. } else if (!plane->state) {
  541. SDE_ERROR_PLANE(to_sde_plane(plane), "invalid state\n");
  542. } else {
  543. psde = to_sde_plane(plane);
  544. pstate = to_sde_plane_state(plane->state);
  545. input_fence = pstate->input_fence;
  546. if (input_fence) {
  547. prefix = sde_sync_get_name_prefix(input_fence);
  548. rc = sde_sync_wait(input_fence, wait_ms);
  549. switch (rc) {
  550. case 0:
  551. SDE_ERROR_PLANE(psde, "%ums timeout on %08X fd %lld\n",
  552. wait_ms, prefix, sde_plane_get_property(pstate,
  553. PLANE_PROP_INPUT_FENCE));
  554. psde->is_error = true;
  555. sde_kms_timeline_status(plane->dev);
  556. ret = -ETIMEDOUT;
  557. break;
  558. case -ERESTARTSYS:
  559. SDE_ERROR_PLANE(psde,
  560. "%ums wait interrupted on %08X\n",
  561. wait_ms, prefix);
  562. psde->is_error = true;
  563. ret = -ERESTARTSYS;
  564. break;
  565. case -EINVAL:
  566. SDE_ERROR_PLANE(psde,
  567. "invalid fence param for %08X\n",
  568. prefix);
  569. psde->is_error = true;
  570. ret = -EINVAL;
  571. break;
  572. case -EBADF:
  573. SDE_INFO("plane%d spec fd signaled on bind failure fd %lld\n",
  574. plane->base.id,
  575. sde_plane_get_property(pstate, PLANE_PROP_INPUT_FENCE));
  576. psde->is_error = true;
  577. ret = 0;
  578. break;
  579. default:
  580. SDE_DEBUG_PLANE(psde, "signaled\n");
  581. ret = 0;
  582. break;
  583. }
  584. if (ret)
  585. SDE_EVT32(DRMID(plane), -ret, prefix, SDE_EVTLOG_ERROR);
  586. else
  587. SDE_EVT32_VERBOSE(DRMID(plane), -ret, prefix);
  588. } else {
  589. ret = 0;
  590. }
  591. }
  592. return ret;
  593. }
  594. /**
  595. * _sde_plane_get_aspace: gets the address space based on the
  596. * fb_translation mode property
  597. */
  598. static int _sde_plane_get_aspace(
  599. struct sde_plane *psde,
  600. struct sde_plane_state *pstate,
  601. struct msm_gem_address_space **aspace)
  602. {
  603. struct sde_kms *kms;
  604. int mode;
  605. if (!psde || !pstate || !aspace) {
  606. SDE_ERROR("invalid parameters\n");
  607. return -EINVAL;
  608. }
  609. kms = _sde_plane_get_kms(&psde->base);
  610. if (!kms) {
  611. SDE_ERROR("invalid kms\n");
  612. return -EINVAL;
  613. }
  614. mode = sde_plane_get_property(pstate,
  615. PLANE_PROP_FB_TRANSLATION_MODE);
  616. switch (mode) {
  617. case SDE_DRM_FB_NON_SEC:
  618. *aspace = kms->aspace[MSM_SMMU_DOMAIN_UNSECURE];
  619. if (!aspace)
  620. return -EINVAL;
  621. break;
  622. case SDE_DRM_FB_SEC:
  623. *aspace = kms->aspace[MSM_SMMU_DOMAIN_SECURE];
  624. if (!aspace)
  625. return -EINVAL;
  626. break;
  627. case SDE_DRM_FB_NON_SEC_DIR_TRANS:
  628. case SDE_DRM_FB_SEC_DIR_TRANS:
  629. *aspace = NULL;
  630. break;
  631. default:
  632. SDE_ERROR("invalid fb_translation mode:%d\n", mode);
  633. return -EFAULT;
  634. }
  635. return 0;
  636. }
  637. static inline void _sde_plane_set_scanout(struct drm_plane *plane,
  638. struct sde_plane_state *pstate,
  639. struct sde_hw_pipe_cfg *pipe_cfg,
  640. struct drm_framebuffer *fb)
  641. {
  642. struct sde_plane *psde;
  643. struct msm_gem_address_space *aspace = NULL;
  644. int ret, mode;
  645. bool secure = false;
  646. if (!plane || !pstate || !pipe_cfg || !fb) {
  647. SDE_ERROR(
  648. "invalid arg(s), plane %d state %d cfg %d fb %d\n",
  649. !plane, !pstate, !pipe_cfg, !fb);
  650. return;
  651. }
  652. psde = to_sde_plane(plane);
  653. if (!psde->pipe_hw) {
  654. SDE_ERROR_PLANE(psde, "invalid pipe_hw\n");
  655. return;
  656. }
  657. ret = _sde_plane_get_aspace(psde, pstate, &aspace);
  658. if (ret) {
  659. SDE_ERROR_PLANE(psde, "Failed to get aspace %d\n", ret);
  660. return;
  661. }
  662. /*
  663. * framebuffer prepare is deferred for prepare_fb calls that
  664. * happen during the transition from secure to non-secure.
  665. * Handle the prepare at this point for such cases. This can be
  666. * expected for one or two frames during the transition.
  667. */
  668. if (aspace && pstate->defer_prepare_fb) {
  669. SDE_EVT32(DRMID(plane), psde->pipe, aspace->domain_attached);
  670. ret = msm_framebuffer_prepare(fb, pstate->aspace);
  671. if (ret) {
  672. SDE_ERROR_PLANE(psde,
  673. "failed to prepare framebuffer %d\n", ret);
  674. return;
  675. }
  676. pstate->defer_prepare_fb = false;
  677. }
  678. mode = sde_plane_get_property(pstate, PLANE_PROP_FB_TRANSLATION_MODE);
  679. if ((mode == SDE_DRM_FB_SEC) || (mode == SDE_DRM_FB_SEC_DIR_TRANS))
  680. secure = true;
  681. ret = sde_format_populate_layout(aspace, fb, &pipe_cfg->layout);
  682. if (ret == -EAGAIN)
  683. SDE_DEBUG_PLANE(psde, "not updating same src addrs\n");
  684. else if (ret) {
  685. SDE_ERROR_PLANE(psde, "failed to get format layout, %d\n", ret);
  686. /*
  687. * Force solid fill color on error. This is to prevent
  688. * smmu faults during secure session transition.
  689. */
  690. psde->is_error = true;
  691. } else if (psde->pipe_hw->ops.setup_sourceaddress) {
  692. SDE_EVT32_VERBOSE(psde->pipe_hw->idx,
  693. pipe_cfg->layout.width,
  694. pipe_cfg->layout.height,
  695. pipe_cfg->layout.plane_addr[0],
  696. pipe_cfg->layout.plane_size[0],
  697. pipe_cfg->layout.plane_addr[1],
  698. pipe_cfg->layout.plane_size[1],
  699. pipe_cfg->layout.plane_addr[2],
  700. pipe_cfg->layout.plane_size[2],
  701. pipe_cfg->layout.plane_addr[3],
  702. pipe_cfg->layout.plane_size[3],
  703. pstate->multirect_index,
  704. secure);
  705. psde->pipe_hw->ops.setup_sourceaddress(psde->pipe_hw, pipe_cfg,
  706. pstate->multirect_index);
  707. }
  708. }
  709. static int _sde_plane_setup_scaler3_lut(struct sde_plane *psde,
  710. struct sde_plane_state *pstate)
  711. {
  712. struct sde_hw_scaler3_cfg *cfg;
  713. int ret = 0;
  714. if (!psde || !pstate) {
  715. SDE_ERROR("invalid args\n");
  716. return -EINVAL;
  717. }
  718. cfg = &psde->scaler3_cfg;
  719. cfg->dir_lut = msm_property_get_blob(
  720. &psde->property_info,
  721. &pstate->property_state, &cfg->dir_len,
  722. PLANE_PROP_SCALER_LUT_ED);
  723. cfg->cir_lut = msm_property_get_blob(
  724. &psde->property_info,
  725. &pstate->property_state, &cfg->cir_len,
  726. PLANE_PROP_SCALER_LUT_CIR);
  727. cfg->sep_lut = msm_property_get_blob(
  728. &psde->property_info,
  729. &pstate->property_state, &cfg->sep_len,
  730. PLANE_PROP_SCALER_LUT_SEP);
  731. if (!cfg->dir_lut || !cfg->cir_lut || !cfg->sep_lut)
  732. ret = -ENODATA;
  733. return ret;
  734. }
  735. static int _sde_plane_setup_scaler3lite_lut(struct sde_plane *psde,
  736. struct sde_plane_state *pstate)
  737. {
  738. struct sde_hw_scaler3_cfg *cfg;
  739. cfg = &psde->scaler3_cfg;
  740. cfg->sep_lut = msm_property_get_blob(
  741. &psde->property_info,
  742. &pstate->property_state, &cfg->sep_len,
  743. PLANE_PROP_SCALER_LUT_SEP);
  744. return cfg->sep_lut ? 0 : -ENODATA;
  745. }
  746. static void _sde_plane_setup_scaler3(struct sde_plane *psde,
  747. struct sde_plane_state *pstate, const struct sde_format *fmt,
  748. uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v)
  749. {
  750. uint32_t decimated, i, src_w, src_h, dst_w, dst_h, src_h_pre_down;
  751. struct sde_hw_scaler3_cfg *scale_cfg;
  752. bool pre_down_supported = (psde->features & BIT(SDE_SSPP_PREDOWNSCALE));
  753. bool inline_rotation = (pstate->rotation & DRM_MODE_ROTATE_90);
  754. if (!fmt || !chroma_subsmpl_h || !chroma_subsmpl_v) {
  755. SDE_ERROR("fmt %d smp_h %d smp_v %d\n", !fmt,
  756. chroma_subsmpl_h, chroma_subsmpl_v);
  757. return;
  758. }
  759. scale_cfg = &psde->scaler3_cfg;
  760. src_w = psde->pipe_cfg.src_rect.w;
  761. src_h = psde->pipe_cfg.src_rect.h;
  762. dst_w = psde->pipe_cfg.dst_rect.w;
  763. dst_h = psde->pipe_cfg.dst_rect.h;
  764. memset(scale_cfg, 0, sizeof(*scale_cfg));
  765. memset(&psde->pixel_ext, 0, sizeof(struct sde_hw_pixel_ext));
  766. /*
  767. * For inline rotation cases, scaler config is post-rotation,
  768. * so swap the dimensions here. However, pixel extension will
  769. * need pre-rotation settings, this will be corrected below
  770. * when calculating pixel extension settings.
  771. */
  772. if (inline_rotation)
  773. swap(src_w, src_h);
  774. decimated = DECIMATED_DIMENSION(src_w,
  775. psde->pipe_cfg.horz_decimation);
  776. scale_cfg->phase_step_x[SDE_SSPP_COMP_0] =
  777. mult_frac((1 << PHASE_STEP_SHIFT), decimated, dst_w);
  778. decimated = DECIMATED_DIMENSION(src_h,
  779. psde->pipe_cfg.vert_decimation);
  780. scale_cfg->phase_step_y[SDE_SSPP_COMP_0] =
  781. mult_frac((1 << PHASE_STEP_SHIFT), decimated, dst_h);
  782. scale_cfg->phase_step_y[SDE_SSPP_COMP_1_2] =
  783. scale_cfg->phase_step_y[SDE_SSPP_COMP_0] / chroma_subsmpl_v;
  784. scale_cfg->phase_step_x[SDE_SSPP_COMP_1_2] =
  785. scale_cfg->phase_step_x[SDE_SSPP_COMP_0] / chroma_subsmpl_h;
  786. scale_cfg->phase_step_x[SDE_SSPP_COMP_2] =
  787. scale_cfg->phase_step_x[SDE_SSPP_COMP_1_2];
  788. scale_cfg->phase_step_y[SDE_SSPP_COMP_2] =
  789. scale_cfg->phase_step_y[SDE_SSPP_COMP_1_2];
  790. scale_cfg->phase_step_x[SDE_SSPP_COMP_3] =
  791. scale_cfg->phase_step_x[SDE_SSPP_COMP_0];
  792. scale_cfg->phase_step_y[SDE_SSPP_COMP_3] =
  793. scale_cfg->phase_step_y[SDE_SSPP_COMP_0];
  794. for (i = 0; i < SDE_MAX_PLANES; i++) {
  795. /*
  796. * For inline rotation cases with pre-downscaling enabled
  797. * set x pre-downscale value if required. Only x direction
  798. * is currently supported. Use src_h as values have been swapped
  799. * and x direction corresponds to height value.
  800. */
  801. src_h_pre_down = src_h;
  802. if (pre_down_supported && inline_rotation) {
  803. if (i == 0 && (src_h > mult_frac(dst_h, 11, 5)))
  804. src_h_pre_down = src_h / 2;
  805. }
  806. scale_cfg->src_width[i] = DECIMATED_DIMENSION(src_w,
  807. psde->pipe_cfg.horz_decimation);
  808. scale_cfg->src_height[i] = DECIMATED_DIMENSION(src_h_pre_down,
  809. psde->pipe_cfg.vert_decimation);
  810. if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2) {
  811. scale_cfg->src_width[i] /= chroma_subsmpl_h;
  812. scale_cfg->src_height[i] /= chroma_subsmpl_v;
  813. }
  814. scale_cfg->preload_x[i] = psde->pipe_sblk->scaler_blk.h_preload;
  815. scale_cfg->preload_y[i] = psde->pipe_sblk->scaler_blk.v_preload;
  816. /* For pixel extension we need the pre-rotated orientation */
  817. if (inline_rotation) {
  818. psde->pixel_ext.num_ext_pxls_top[i] =
  819. scale_cfg->src_width[i];
  820. psde->pixel_ext.num_ext_pxls_left[i] =
  821. scale_cfg->src_height[i];
  822. } else {
  823. psde->pixel_ext.num_ext_pxls_top[i] =
  824. scale_cfg->src_height[i];
  825. psde->pixel_ext.num_ext_pxls_left[i] =
  826. scale_cfg->src_width[i];
  827. }
  828. }
  829. if ((!(SDE_FORMAT_IS_YUV(fmt)) && (src_h == dst_h)
  830. && (src_w == dst_w) && !inline_rotation) ||
  831. pstate->multirect_mode)
  832. return;
  833. SDE_DEBUG_PLANE(psde,
  834. "setting bilinear: src:%dx%d dst:%dx%d chroma:%dx%d fmt:%x\n",
  835. src_w, src_h, dst_w, dst_h,
  836. chroma_subsmpl_v, chroma_subsmpl_h,
  837. fmt->base.pixel_format);
  838. scale_cfg->dst_width = dst_w;
  839. scale_cfg->dst_height = dst_h;
  840. scale_cfg->y_rgb_filter_cfg = SDE_SCALE_BIL;
  841. scale_cfg->uv_filter_cfg = SDE_SCALE_BIL;
  842. scale_cfg->alpha_filter_cfg = SDE_SCALE_ALPHA_BIL;
  843. scale_cfg->lut_flag = 0;
  844. scale_cfg->blend_cfg = 1;
  845. scale_cfg->enable = 1;
  846. scale_cfg->dyn_exp_disabled = SDE_QSEED_DEFAULT_DYN_EXP;
  847. }
  848. /**
  849. * _sde_plane_setup_scaler2 - determine default scaler phase steps/filter type
  850. * @psde: Pointer to SDE plane object
  851. * @src: Source size
  852. * @dst: Destination size
  853. * @phase_steps: Pointer to output array for phase steps
  854. * @filter: Pointer to output array for filter type
  855. * @fmt: Pointer to format definition
  856. * @chroma_subsampling: Subsampling amount for chroma channel
  857. *
  858. * Returns: 0 on success
  859. */
  860. static int _sde_plane_setup_scaler2(struct sde_plane *psde,
  861. uint32_t src, uint32_t dst, uint32_t *phase_steps,
  862. enum sde_hw_filter *filter, const struct sde_format *fmt,
  863. uint32_t chroma_subsampling)
  864. {
  865. if (!psde || !phase_steps || !filter || !fmt) {
  866. SDE_ERROR(
  867. "invalid arg(s), plane %d phase %d filter %d fmt %d\n",
  868. !psde, !phase_steps, !filter, !fmt);
  869. return -EINVAL;
  870. }
  871. /* calculate phase steps, leave init phase as zero */
  872. phase_steps[SDE_SSPP_COMP_0] =
  873. mult_frac(1 << PHASE_STEP_SHIFT, src, dst);
  874. phase_steps[SDE_SSPP_COMP_1_2] =
  875. phase_steps[SDE_SSPP_COMP_0] / chroma_subsampling;
  876. phase_steps[SDE_SSPP_COMP_2] = phase_steps[SDE_SSPP_COMP_1_2];
  877. phase_steps[SDE_SSPP_COMP_3] = phase_steps[SDE_SSPP_COMP_0];
  878. /* calculate scaler config, if necessary */
  879. if (SDE_FORMAT_IS_YUV(fmt) || src != dst) {
  880. filter[SDE_SSPP_COMP_3] =
  881. (src <= dst) ? SDE_SCALE_FILTER_BIL :
  882. SDE_SCALE_FILTER_PCMN;
  883. if (SDE_FORMAT_IS_YUV(fmt)) {
  884. filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_CA;
  885. filter[SDE_SSPP_COMP_1_2] = filter[SDE_SSPP_COMP_3];
  886. } else {
  887. filter[SDE_SSPP_COMP_0] = filter[SDE_SSPP_COMP_3];
  888. filter[SDE_SSPP_COMP_1_2] =
  889. SDE_SCALE_FILTER_NEAREST;
  890. }
  891. } else {
  892. /* disable scaler */
  893. filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_MAX;
  894. filter[SDE_SSPP_COMP_1_2] = SDE_SCALE_FILTER_MAX;
  895. filter[SDE_SSPP_COMP_3] = SDE_SCALE_FILTER_MAX;
  896. }
  897. return 0;
  898. }
  899. /**
  900. * _sde_plane_setup_pixel_ext - determine default pixel extension values
  901. * @psde: Pointer to SDE plane object
  902. * @src: Source size
  903. * @dst: Destination size
  904. * @decimated_src: Source size after decimation, if any
  905. * @phase_steps: Pointer to output array for phase steps
  906. * @out_src: Output array for pixel extension values
  907. * @out_edge1: Output array for pixel extension first edge
  908. * @out_edge2: Output array for pixel extension second edge
  909. * @filter: Pointer to array for filter type
  910. * @fmt: Pointer to format definition
  911. * @chroma_subsampling: Subsampling amount for chroma channel
  912. * @post_compare: Whether to chroma subsampled source size for comparisions
  913. */
  914. static void _sde_plane_setup_pixel_ext(struct sde_plane *psde,
  915. uint32_t src, uint32_t dst, uint32_t decimated_src,
  916. uint32_t *phase_steps, uint32_t *out_src, int *out_edge1,
  917. int *out_edge2, enum sde_hw_filter *filter,
  918. const struct sde_format *fmt, uint32_t chroma_subsampling,
  919. bool post_compare)
  920. {
  921. int64_t edge1, edge2, caf;
  922. uint32_t src_work;
  923. int i, tmp;
  924. if (psde && phase_steps && out_src && out_edge1 &&
  925. out_edge2 && filter && fmt) {
  926. /* handle CAF for YUV formats */
  927. if (SDE_FORMAT_IS_YUV(fmt) && *filter == SDE_SCALE_FILTER_CA)
  928. caf = PHASE_STEP_UNIT_SCALE;
  929. else
  930. caf = 0;
  931. for (i = 0; i < SDE_MAX_PLANES; i++) {
  932. src_work = decimated_src;
  933. if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2)
  934. src_work /= chroma_subsampling;
  935. if (post_compare)
  936. src = src_work;
  937. if (!SDE_FORMAT_IS_YUV(fmt) && (src == dst)) {
  938. /* unity */
  939. edge1 = 0;
  940. edge2 = 0;
  941. } else if (dst >= src) {
  942. /* upscale */
  943. edge1 = (1 << PHASE_RESIDUAL);
  944. edge1 -= caf;
  945. edge2 = (1 << PHASE_RESIDUAL);
  946. edge2 += (dst - 1) * *(phase_steps + i);
  947. edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
  948. edge2 += caf;
  949. edge2 = -(edge2);
  950. } else {
  951. /* downscale */
  952. edge1 = 0;
  953. edge2 = (dst - 1) * *(phase_steps + i);
  954. edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
  955. edge2 += *(phase_steps + i);
  956. edge2 = -(edge2);
  957. }
  958. /* only enable CAF for luma plane */
  959. caf = 0;
  960. /* populate output arrays */
  961. *(out_src + i) = src_work;
  962. /* edge updates taken from __pxl_extn_helper */
  963. if (edge1 >= 0) {
  964. tmp = (uint32_t)edge1;
  965. tmp >>= PHASE_STEP_SHIFT;
  966. *(out_edge1 + i) = -tmp;
  967. } else {
  968. tmp = (uint32_t)(-edge1);
  969. *(out_edge1 + i) =
  970. (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
  971. PHASE_STEP_SHIFT;
  972. }
  973. if (edge2 >= 0) {
  974. tmp = (uint32_t)edge2;
  975. tmp >>= PHASE_STEP_SHIFT;
  976. *(out_edge2 + i) = -tmp;
  977. } else {
  978. tmp = (uint32_t)(-edge2);
  979. *(out_edge2 + i) =
  980. (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
  981. PHASE_STEP_SHIFT;
  982. }
  983. }
  984. }
  985. }
  986. static inline void _sde_plane_setup_csc(struct sde_plane *psde, struct sde_plane_state *pstate)
  987. {
  988. static const struct sde_csc_cfg sde_csc_YUV2RGB_601L = {
  989. {
  990. /* S15.16 format */
  991. 0x00012A00, 0x00000000, 0x00019880,
  992. 0x00012A00, 0xFFFF9B80, 0xFFFF3000,
  993. 0x00012A00, 0x00020480, 0x00000000,
  994. },
  995. /* signed bias */
  996. { 0xfff0, 0xff80, 0xff80,},
  997. { 0x0, 0x0, 0x0,},
  998. /* unsigned clamp */
  999. { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,},
  1000. { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,},
  1001. };
  1002. static const struct sde_csc_cfg sde_csc10_YUV2RGB_601L = {
  1003. {
  1004. /* S15.16 format */
  1005. 0x00012A00, 0x00000000, 0x00019880,
  1006. 0x00012A00, 0xFFFF9B80, 0xFFFF3000,
  1007. 0x00012A00, 0x00020480, 0x00000000,
  1008. },
  1009. /* signed bias */
  1010. { 0xffc0, 0xfe00, 0xfe00,},
  1011. { 0x0, 0x0, 0x0,},
  1012. /* unsigned clamp */
  1013. { 0x40, 0x3ac, 0x40, 0x3c0, 0x40, 0x3c0,},
  1014. { 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,},
  1015. };
  1016. if (!psde || !pstate) {
  1017. SDE_ERROR("invalid plane\n");
  1018. return;
  1019. }
  1020. /* revert to kernel default if override not available */
  1021. if (pstate->csc_usr_ptr)
  1022. pstate->csc_ptr = pstate->csc_usr_ptr;
  1023. else if (BIT(SDE_SSPP_CSC_10BIT) & psde->features)
  1024. pstate->csc_ptr = (struct sde_csc_cfg *)&sde_csc10_YUV2RGB_601L;
  1025. else
  1026. pstate->csc_ptr = (struct sde_csc_cfg *)&sde_csc_YUV2RGB_601L;
  1027. SDE_DEBUG_PLANE(psde, "using 0x%X 0x%X 0x%X...\n",
  1028. pstate->csc_ptr->csc_mv[0],
  1029. pstate->csc_ptr->csc_mv[1],
  1030. pstate->csc_ptr->csc_mv[2]);
  1031. }
  1032. static void sde_color_process_plane_setup(struct drm_plane *plane)
  1033. {
  1034. struct sde_plane *psde;
  1035. struct sde_plane_state *pstate;
  1036. uint32_t hue, saturation, value, contrast;
  1037. struct drm_msm_memcol *memcol = NULL;
  1038. struct drm_msm_3d_gamut *vig_gamut = NULL;
  1039. struct drm_msm_igc_lut *igc = NULL;
  1040. struct drm_msm_pgc_lut *gc = NULL;
  1041. size_t memcol_sz = 0, size = 0;
  1042. struct sde_hw_cp_cfg hw_cfg = {};
  1043. struct sde_hw_ctl *ctl = _sde_plane_get_hw_ctl(plane);
  1044. bool fp16_igc, fp16_unmult, ucsc_unmult, ucsc_alpha_dither;
  1045. int ucsc_gc, ucsc_igc;
  1046. struct drm_msm_fp16_gc *fp16_gc = NULL;
  1047. struct drm_msm_fp16_csc *fp16_csc = NULL;
  1048. struct drm_msm_ucsc_csc *ucsc_csc = NULL;
  1049. psde = to_sde_plane(plane);
  1050. pstate = to_sde_plane_state(plane->state);
  1051. hue = (uint32_t) sde_plane_get_property(pstate, PLANE_PROP_HUE_ADJUST);
  1052. if (psde->pipe_hw->ops.setup_pa_hue)
  1053. psde->pipe_hw->ops.setup_pa_hue(psde->pipe_hw, &hue);
  1054. saturation = (uint32_t) sde_plane_get_property(pstate,
  1055. PLANE_PROP_SATURATION_ADJUST);
  1056. if (psde->pipe_hw->ops.setup_pa_sat)
  1057. psde->pipe_hw->ops.setup_pa_sat(psde->pipe_hw, &saturation);
  1058. value = (uint32_t) sde_plane_get_property(pstate,
  1059. PLANE_PROP_VALUE_ADJUST);
  1060. if (psde->pipe_hw->ops.setup_pa_val)
  1061. psde->pipe_hw->ops.setup_pa_val(psde->pipe_hw, &value);
  1062. contrast = (uint32_t) sde_plane_get_property(pstate,
  1063. PLANE_PROP_CONTRAST_ADJUST);
  1064. if (psde->pipe_hw->ops.setup_pa_cont)
  1065. psde->pipe_hw->ops.setup_pa_cont(psde->pipe_hw, &contrast);
  1066. if (psde->pipe_hw->ops.setup_pa_memcolor) {
  1067. /* Skin memory color setup */
  1068. memcol = msm_property_get_blob(&psde->property_info,
  1069. &pstate->property_state,
  1070. &memcol_sz,
  1071. PLANE_PROP_SKIN_COLOR);
  1072. psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
  1073. MEMCOLOR_SKIN, memcol);
  1074. /* Sky memory color setup */
  1075. memcol = msm_property_get_blob(&psde->property_info,
  1076. &pstate->property_state,
  1077. &memcol_sz,
  1078. PLANE_PROP_SKY_COLOR);
  1079. psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
  1080. MEMCOLOR_SKY, memcol);
  1081. /* Foliage memory color setup */
  1082. memcol = msm_property_get_blob(&psde->property_info,
  1083. &pstate->property_state,
  1084. &memcol_sz,
  1085. PLANE_PROP_FOLIAGE_COLOR);
  1086. psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
  1087. MEMCOLOR_FOLIAGE, memcol);
  1088. }
  1089. if (pstate->dirty & SDE_PLANE_DIRTY_VIG_GAMUT &&
  1090. psde->pipe_hw->ops.setup_vig_gamut) {
  1091. vig_gamut = msm_property_get_blob(&psde->property_info,
  1092. &pstate->property_state,
  1093. &size,
  1094. PLANE_PROP_VIG_GAMUT);
  1095. hw_cfg.last_feature = 0;
  1096. hw_cfg.ctl = ctl;
  1097. hw_cfg.len = size;
  1098. hw_cfg.payload = vig_gamut;
  1099. psde->pipe_hw->ops.setup_vig_gamut(psde->pipe_hw, &hw_cfg);
  1100. }
  1101. if (pstate->dirty & SDE_PLANE_DIRTY_VIG_IGC &&
  1102. psde->pipe_hw->ops.setup_vig_igc) {
  1103. igc = msm_property_get_blob(&psde->property_info,
  1104. &pstate->property_state,
  1105. &size,
  1106. PLANE_PROP_VIG_IGC);
  1107. hw_cfg.last_feature = 0;
  1108. hw_cfg.ctl = ctl;
  1109. hw_cfg.len = size;
  1110. hw_cfg.payload = igc;
  1111. psde->pipe_hw->ops.setup_vig_igc(psde->pipe_hw, &hw_cfg);
  1112. }
  1113. if (pstate->dirty & SDE_PLANE_DIRTY_DMA_IGC &&
  1114. psde->pipe_hw->ops.setup_dma_igc) {
  1115. igc = msm_property_get_blob(&psde->property_info,
  1116. &pstate->property_state,
  1117. &size,
  1118. PLANE_PROP_DMA_IGC);
  1119. hw_cfg.last_feature = 0;
  1120. hw_cfg.ctl = ctl;
  1121. hw_cfg.len = size;
  1122. hw_cfg.payload = igc;
  1123. psde->pipe_hw->ops.setup_dma_igc(psde->pipe_hw, &hw_cfg,
  1124. pstate->multirect_index);
  1125. }
  1126. if (pstate->dirty & SDE_PLANE_DIRTY_DMA_GC &&
  1127. psde->pipe_hw->ops.setup_dma_gc) {
  1128. gc = msm_property_get_blob(&psde->property_info,
  1129. &pstate->property_state,
  1130. &size,
  1131. PLANE_PROP_DMA_GC);
  1132. hw_cfg.last_feature = 0;
  1133. hw_cfg.ctl = ctl;
  1134. hw_cfg.len = size;
  1135. hw_cfg.payload = gc;
  1136. psde->pipe_hw->ops.setup_dma_gc(psde->pipe_hw, &hw_cfg,
  1137. pstate->multirect_index);
  1138. }
  1139. if (pstate->dirty & SDE_PLANE_DIRTY_FP16_IGC &&
  1140. psde->pipe_hw->ops.setup_fp16_igc) {
  1141. fp16_igc = !!sde_plane_get_property(pstate,
  1142. PLANE_PROP_FP16_IGC);
  1143. hw_cfg.last_feature = 0;
  1144. hw_cfg.ctl = ctl;
  1145. hw_cfg.len = sizeof(bool);
  1146. hw_cfg.payload = &fp16_igc;
  1147. psde->pipe_hw->ops.setup_fp16_igc(psde->pipe_hw,
  1148. pstate->multirect_index, &hw_cfg);
  1149. }
  1150. if (pstate->dirty & SDE_PLANE_DIRTY_FP16_GC &&
  1151. psde->pipe_hw->ops.setup_fp16_gc) {
  1152. fp16_gc = msm_property_get_blob(&psde->property_info,
  1153. &pstate->property_state,
  1154. &size,
  1155. PLANE_PROP_FP16_GC);
  1156. hw_cfg.last_feature = 0;
  1157. hw_cfg.ctl = ctl;
  1158. hw_cfg.len = size;
  1159. hw_cfg.payload = fp16_gc;
  1160. psde->pipe_hw->ops.setup_fp16_gc(psde->pipe_hw,
  1161. pstate->multirect_index, &hw_cfg);
  1162. }
  1163. if (pstate->dirty & SDE_PLANE_DIRTY_FP16_CSC &&
  1164. psde->pipe_hw->ops.setup_fp16_csc) {
  1165. fp16_csc = msm_property_get_blob(&psde->property_info,
  1166. &pstate->property_state,
  1167. &size,
  1168. PLANE_PROP_FP16_CSC);
  1169. hw_cfg.last_feature = 0;
  1170. hw_cfg.ctl = ctl;
  1171. hw_cfg.len = size;
  1172. hw_cfg.payload = fp16_csc;
  1173. psde->pipe_hw->ops.setup_fp16_csc(psde->pipe_hw,
  1174. pstate->multirect_index, &hw_cfg);
  1175. }
  1176. if (pstate->dirty & SDE_PLANE_DIRTY_FP16_UNMULT &&
  1177. psde->pipe_hw->ops.setup_fp16_unmult) {
  1178. fp16_unmult = !!sde_plane_get_property(pstate,
  1179. PLANE_PROP_FP16_UNMULT);
  1180. hw_cfg.last_feature = 0;
  1181. hw_cfg.ctl = ctl;
  1182. hw_cfg.len = sizeof(bool);
  1183. hw_cfg.payload = &fp16_unmult;
  1184. psde->pipe_hw->ops.setup_fp16_unmult(psde->pipe_hw,
  1185. pstate->multirect_index, &hw_cfg);
  1186. }
  1187. if (pstate->dirty & SDE_PLANE_DIRTY_UCSC_IGC &&
  1188. psde->pipe_hw->ops.setup_ucsc_igc) {
  1189. ucsc_igc = sde_plane_get_property(pstate,
  1190. PLANE_PROP_UCSC_IGC);
  1191. hw_cfg.last_feature = 0;
  1192. hw_cfg.ctl = ctl;
  1193. hw_cfg.len = sizeof(int);
  1194. hw_cfg.payload = &ucsc_igc;
  1195. psde->pipe_hw->ops.setup_ucsc_igc(psde->pipe_hw,
  1196. pstate->multirect_index, &hw_cfg);
  1197. }
  1198. if (pstate->dirty & SDE_PLANE_DIRTY_UCSC_GC &&
  1199. psde->pipe_hw->ops.setup_ucsc_gc) {
  1200. ucsc_gc = sde_plane_get_property(pstate,
  1201. PLANE_PROP_UCSC_GC);
  1202. hw_cfg.last_feature = 0;
  1203. hw_cfg.ctl = ctl;
  1204. hw_cfg.len = sizeof(int);
  1205. hw_cfg.payload = &ucsc_gc;
  1206. psde->pipe_hw->ops.setup_ucsc_gc(psde->pipe_hw,
  1207. pstate->multirect_index, &hw_cfg);
  1208. }
  1209. if (pstate->dirty & SDE_PLANE_DIRTY_UCSC_CSC &&
  1210. psde->pipe_hw->ops.setup_ucsc_csc) {
  1211. ucsc_csc = msm_property_get_blob(&psde->property_info,
  1212. &pstate->property_state,
  1213. &size,
  1214. PLANE_PROP_UCSC_CSC);
  1215. hw_cfg.last_feature = 0;
  1216. hw_cfg.ctl = ctl;
  1217. hw_cfg.len = size;
  1218. hw_cfg.payload = ucsc_csc;
  1219. psde->pipe_hw->ops.setup_ucsc_csc(psde->pipe_hw,
  1220. pstate->multirect_index, &hw_cfg);
  1221. }
  1222. if (pstate->dirty & SDE_PLANE_DIRTY_UCSC_UNMULT &&
  1223. psde->pipe_hw->ops.setup_ucsc_unmult) {
  1224. ucsc_unmult = !!sde_plane_get_property(pstate,
  1225. PLANE_PROP_UCSC_UNMULT);
  1226. hw_cfg.last_feature = 0;
  1227. hw_cfg.ctl = ctl;
  1228. hw_cfg.len = sizeof(bool);
  1229. hw_cfg.payload = &ucsc_unmult;
  1230. psde->pipe_hw->ops.setup_ucsc_unmult(psde->pipe_hw,
  1231. pstate->multirect_index, &hw_cfg);
  1232. }
  1233. if (pstate->dirty & SDE_PLANE_DIRTY_UCSC_ALPHA_DITHER &&
  1234. psde->pipe_hw->ops.setup_ucsc_alpha_dither) {
  1235. ucsc_alpha_dither = !!sde_plane_get_property(pstate,
  1236. PLANE_PROP_UCSC_ALPHA_DITHER);
  1237. hw_cfg.last_feature = 0;
  1238. hw_cfg.ctl = ctl;
  1239. hw_cfg.len = sizeof(bool);
  1240. hw_cfg.payload = &ucsc_alpha_dither;
  1241. psde->pipe_hw->ops.setup_ucsc_alpha_dither(psde->pipe_hw,
  1242. pstate->multirect_index, &hw_cfg);
  1243. }
  1244. }
  1245. static void _sde_plane_setup_scaler(struct sde_plane *psde,
  1246. struct sde_plane_state *pstate,
  1247. const struct sde_format *fmt, bool color_fill)
  1248. {
  1249. struct sde_hw_pixel_ext *pe;
  1250. uint32_t chroma_subsmpl_h, chroma_subsmpl_v;
  1251. const struct drm_format_info *info = NULL;
  1252. if (!psde || !fmt || !pstate) {
  1253. SDE_ERROR("invalid arg(s), plane %d fmt %d state %d\n",
  1254. !psde, !fmt, !pstate);
  1255. return;
  1256. }
  1257. memcpy(&psde->scaler3_cfg, &pstate->scaler3_cfg,
  1258. sizeof(psde->scaler3_cfg));
  1259. memcpy(&psde->pixel_ext, &pstate->pixel_ext,
  1260. sizeof(psde->pixel_ext));
  1261. info = drm_format_info(fmt->base.pixel_format);
  1262. pe = &psde->pixel_ext;
  1263. psde->pipe_cfg.horz_decimation =
  1264. sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
  1265. psde->pipe_cfg.vert_decimation =
  1266. sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
  1267. /* don't chroma subsample if decimating */
  1268. chroma_subsmpl_h = psde->pipe_cfg.horz_decimation ? 1 : info->hsub;
  1269. chroma_subsmpl_v = psde->pipe_cfg.vert_decimation ? 1 : info->vsub;
  1270. /* update scaler */
  1271. if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3) ||
  1272. (psde->features & BIT(SDE_SSPP_SCALER_QSEED3LITE))) {
  1273. int rc = -EINVAL;
  1274. if (!color_fill && !psde->debugfs_default_scale)
  1275. rc = is_qseed3_rev_qseed3lite(psde->pipe_hw->catalog) ?
  1276. _sde_plane_setup_scaler3lite_lut(psde, pstate) :
  1277. _sde_plane_setup_scaler3_lut(psde, pstate);
  1278. if (rc || pstate->scaler_check_state !=
  1279. SDE_PLANE_SCLCHECK_SCALER_V2) {
  1280. SDE_EVT32_VERBOSE(DRMID(&psde->base), color_fill,
  1281. pstate->scaler_check_state,
  1282. psde->debugfs_default_scale, rc,
  1283. psde->pipe_cfg.src_rect.w,
  1284. psde->pipe_cfg.src_rect.h,
  1285. psde->pipe_cfg.dst_rect.w,
  1286. psde->pipe_cfg.dst_rect.h,
  1287. pstate->multirect_mode);
  1288. /* calculate default config for QSEED3 */
  1289. _sde_plane_setup_scaler3(psde, pstate, fmt,
  1290. chroma_subsmpl_h, chroma_subsmpl_v);
  1291. }
  1292. } else if (pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V1 ||
  1293. color_fill || psde->debugfs_default_scale) {
  1294. uint32_t deci_dim, i;
  1295. /* calculate default configuration for QSEED2 */
  1296. memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
  1297. SDE_DEBUG_PLANE(psde, "default config\n");
  1298. deci_dim = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.w,
  1299. psde->pipe_cfg.horz_decimation);
  1300. _sde_plane_setup_scaler2(psde,
  1301. deci_dim,
  1302. psde->pipe_cfg.dst_rect.w,
  1303. pe->phase_step_x,
  1304. pe->horz_filter, fmt, chroma_subsmpl_h);
  1305. if (SDE_FORMAT_IS_YUV(fmt))
  1306. deci_dim &= ~0x1;
  1307. _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.w,
  1308. psde->pipe_cfg.dst_rect.w, deci_dim,
  1309. pe->phase_step_x,
  1310. pe->roi_w,
  1311. pe->num_ext_pxls_left,
  1312. pe->num_ext_pxls_right, pe->horz_filter, fmt,
  1313. chroma_subsmpl_h, 0);
  1314. deci_dim = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.h,
  1315. psde->pipe_cfg.vert_decimation);
  1316. _sde_plane_setup_scaler2(psde,
  1317. deci_dim,
  1318. psde->pipe_cfg.dst_rect.h,
  1319. pe->phase_step_y,
  1320. pe->vert_filter, fmt, chroma_subsmpl_v);
  1321. _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.h,
  1322. psde->pipe_cfg.dst_rect.h, deci_dim,
  1323. pe->phase_step_y,
  1324. pe->roi_h,
  1325. pe->num_ext_pxls_top,
  1326. pe->num_ext_pxls_btm, pe->vert_filter, fmt,
  1327. chroma_subsmpl_v, 1);
  1328. for (i = 0; i < SDE_MAX_PLANES; i++) {
  1329. if (pe->num_ext_pxls_left[i] >= 0)
  1330. pe->left_rpt[i] = pe->num_ext_pxls_left[i];
  1331. else
  1332. pe->left_ftch[i] = pe->num_ext_pxls_left[i];
  1333. if (pe->num_ext_pxls_right[i] >= 0)
  1334. pe->right_rpt[i] = pe->num_ext_pxls_right[i];
  1335. else
  1336. pe->right_ftch[i] = pe->num_ext_pxls_right[i];
  1337. if (pe->num_ext_pxls_top[i] >= 0)
  1338. pe->top_rpt[i] = pe->num_ext_pxls_top[i];
  1339. else
  1340. pe->top_ftch[i] = pe->num_ext_pxls_top[i];
  1341. if (pe->num_ext_pxls_btm[i] >= 0)
  1342. pe->btm_rpt[i] = pe->num_ext_pxls_btm[i];
  1343. else
  1344. pe->btm_ftch[i] = pe->num_ext_pxls_btm[i];
  1345. }
  1346. }
  1347. if (psde->pipe_hw->ops.setup_pre_downscale)
  1348. psde->pipe_hw->ops.setup_pre_downscale(psde->pipe_hw,
  1349. &pstate->pre_down);
  1350. }
  1351. /**
  1352. * _sde_plane_color_fill - enables color fill on plane
  1353. * @psde: Pointer to SDE plane object
  1354. * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red
  1355. * @alpha: 8-bit fill alpha value, 255 selects 100% alpha
  1356. * Returns: 0 on success
  1357. */
  1358. static int _sde_plane_color_fill(struct sde_plane *psde,
  1359. uint32_t color, uint32_t alpha)
  1360. {
  1361. const struct sde_format *fmt;
  1362. const struct drm_plane *plane;
  1363. struct sde_plane_state *pstate;
  1364. bool blend_enable = true;
  1365. if (!psde || !psde->base.state) {
  1366. SDE_ERROR("invalid plane\n");
  1367. return -EINVAL;
  1368. }
  1369. if (!psde->pipe_hw) {
  1370. SDE_ERROR_PLANE(psde, "invalid plane h/w pointer\n");
  1371. return -EINVAL;
  1372. }
  1373. plane = &psde->base;
  1374. pstate = to_sde_plane_state(plane->state);
  1375. SDE_DEBUG_PLANE(psde, "\n");
  1376. /*
  1377. * select fill format to match user property expectation,
  1378. * h/w only supports RGB variants
  1379. */
  1380. fmt = sde_get_sde_format(DRM_FORMAT_ABGR8888);
  1381. blend_enable = (SDE_DRM_BLEND_OP_OPAQUE !=
  1382. sde_plane_get_property(pstate, PLANE_PROP_BLEND_OP));
  1383. /* update sspp */
  1384. if (fmt && psde->pipe_hw->ops.setup_solidfill) {
  1385. psde->pipe_hw->ops.setup_solidfill(psde->pipe_hw,
  1386. (color & 0xFFFFFF) | ((alpha & 0xFF) << 24),
  1387. pstate->multirect_index);
  1388. /* override scaler/decimation if solid fill */
  1389. psde->pipe_cfg.src_rect.x = 0;
  1390. psde->pipe_cfg.src_rect.y = 0;
  1391. psde->pipe_cfg.src_rect.w = psde->pipe_cfg.dst_rect.w;
  1392. psde->pipe_cfg.src_rect.h = psde->pipe_cfg.dst_rect.h;
  1393. _sde_plane_setup_scaler(psde, pstate, fmt, true);
  1394. if (psde->pipe_hw->ops.setup_format)
  1395. psde->pipe_hw->ops.setup_format(psde->pipe_hw,
  1396. fmt, blend_enable,
  1397. SDE_SSPP_SOLID_FILL,
  1398. pstate->multirect_index);
  1399. if (psde->pipe_hw->ops.setup_rects)
  1400. psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
  1401. &psde->pipe_cfg,
  1402. pstate->multirect_index);
  1403. if (psde->pipe_hw->ops.setup_pe)
  1404. psde->pipe_hw->ops.setup_pe(psde->pipe_hw,
  1405. &psde->pixel_ext);
  1406. if (psde->pipe_hw->ops.setup_scaler &&
  1407. pstate->multirect_index != SDE_SSPP_RECT_1) {
  1408. psde->pipe_hw->ctl = _sde_plane_get_hw_ctl(plane);
  1409. psde->pipe_hw->ops.setup_scaler(psde->pipe_hw,
  1410. &psde->pipe_cfg, &psde->pixel_ext,
  1411. &psde->scaler3_cfg);
  1412. }
  1413. }
  1414. return 0;
  1415. }
  1416. /**
  1417. * sde_plane_rot_atomic_check - verify rotator update of the given state
  1418. * @plane: Pointer to drm plane
  1419. * @state: Pointer to drm plane state to be validated
  1420. * return: 0 if success; error code otherwise
  1421. */
  1422. static int sde_plane_rot_atomic_check(struct drm_plane *plane,
  1423. struct drm_plane_state *state)
  1424. {
  1425. struct sde_plane *psde;
  1426. struct sde_plane_state *pstate, *old_pstate;
  1427. int ret = 0;
  1428. u32 rotation;
  1429. if (!plane || !state) {
  1430. SDE_ERROR("invalid plane/state\n");
  1431. return -EINVAL;
  1432. }
  1433. psde = to_sde_plane(plane);
  1434. pstate = to_sde_plane_state(state);
  1435. old_pstate = to_sde_plane_state(plane->state);
  1436. /* check inline rotation and simplify the transform */
  1437. rotation = drm_rotation_simplify(
  1438. state->rotation,
  1439. DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
  1440. DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y);
  1441. if ((rotation & DRM_MODE_ROTATE_180) ||
  1442. (rotation & DRM_MODE_ROTATE_270)) {
  1443. SDE_ERROR_PLANE(psde,
  1444. "invalid rotation transform must be simplified 0x%x\n",
  1445. rotation);
  1446. ret = -EINVAL;
  1447. goto exit;
  1448. }
  1449. if (rotation & DRM_MODE_ROTATE_90) {
  1450. struct msm_drm_private *priv = plane->dev->dev_private;
  1451. struct sde_kms *sde_kms;
  1452. const struct msm_format *msm_fmt;
  1453. const struct sde_format *fmt;
  1454. struct sde_rect src;
  1455. bool q16_data = true;
  1456. POPULATE_RECT(&src, state->src_x, state->src_y,
  1457. state->src_w, state->src_h, q16_data);
  1458. /*
  1459. * DRM framework expects rotation flag in counter-clockwise
  1460. * direction and the HW expects in clockwise direction.
  1461. * Flip the flags to match with HW.
  1462. */
  1463. rotation ^= (DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y);
  1464. if (!psde->pipe_sblk->in_rot_maxdwnscale_rt_num ||
  1465. !psde->pipe_sblk->in_rot_maxdwnscale_rt_denom ||
  1466. !psde->pipe_sblk->in_rot_maxdwnscale_nrt ||
  1467. !psde->pipe_sblk->in_rot_maxheight ||
  1468. !psde->pipe_sblk->in_rot_format_list ||
  1469. !(psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT))) {
  1470. SDE_ERROR_PLANE(psde,
  1471. "wrong config rt:%d/%d nrt:%d fmt:%d h:%d 0x%x\n",
  1472. !psde->pipe_sblk->in_rot_maxdwnscale_rt_num,
  1473. !psde->pipe_sblk->in_rot_maxdwnscale_rt_denom,
  1474. !psde->pipe_sblk->in_rot_maxdwnscale_nrt,
  1475. !psde->pipe_sblk->in_rot_format_list,
  1476. !psde->pipe_sblk->in_rot_maxheight,
  1477. psde->features);
  1478. ret = -EINVAL;
  1479. goto exit;
  1480. }
  1481. /* check for valid height */
  1482. if (src.h > psde->pipe_sblk->in_rot_maxheight) {
  1483. SDE_ERROR_PLANE(psde,
  1484. "invalid height for inline rot:%d max:%d\n",
  1485. src.h, psde->pipe_sblk->in_rot_maxheight);
  1486. ret = -EINVAL;
  1487. goto exit;
  1488. }
  1489. if (!sde_plane_enabled(state))
  1490. goto exit;
  1491. /* check for valid formats supported by inline rot */
  1492. sde_kms = to_sde_kms(priv->kms);
  1493. msm_fmt = msm_framebuffer_format(state->fb);
  1494. fmt = to_sde_format(msm_fmt);
  1495. ret = sde_format_validate_fmt(&sde_kms->base, fmt,
  1496. psde->pipe_sblk->in_rot_format_list);
  1497. }
  1498. exit:
  1499. pstate->rotation = rotation;
  1500. return ret;
  1501. }
  1502. static bool _sde_plane_halt_requests(struct drm_plane *plane,
  1503. uint32_t xin_id, bool halt_forced_clk, bool enable)
  1504. {
  1505. struct sde_plane *psde;
  1506. struct msm_drm_private *priv;
  1507. struct sde_vbif_set_xin_halt_params halt_params;
  1508. if (!plane || !plane->dev) {
  1509. SDE_ERROR("invalid arguments\n");
  1510. return false;
  1511. }
  1512. psde = to_sde_plane(plane);
  1513. if (!psde->pipe_hw || !psde->pipe_hw->cap) {
  1514. SDE_ERROR("invalid pipe reference\n");
  1515. return false;
  1516. }
  1517. priv = plane->dev->dev_private;
  1518. if (!priv || !priv->kms) {
  1519. SDE_ERROR("invalid KMS reference\n");
  1520. return false;
  1521. }
  1522. memset(&halt_params, 0, sizeof(halt_params));
  1523. halt_params.vbif_idx = VBIF_RT;
  1524. halt_params.xin_id = xin_id;
  1525. halt_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  1526. halt_params.forced_on = halt_forced_clk;
  1527. halt_params.enable = enable;
  1528. return sde_vbif_set_xin_halt(to_sde_kms(priv->kms), &halt_params);
  1529. }
  1530. void sde_plane_halt_requests(struct drm_plane *plane, bool enable)
  1531. {
  1532. struct sde_plane *psde;
  1533. if (!plane) {
  1534. SDE_ERROR("invalid plane\n");
  1535. return;
  1536. }
  1537. psde = to_sde_plane(plane);
  1538. if (!psde->pipe_hw || !psde->pipe_hw->cap) {
  1539. SDE_ERROR("invalid pipe reference\n");
  1540. return;
  1541. }
  1542. SDE_EVT32(DRMID(plane), psde->xin_halt_forced_clk, enable);
  1543. psde->xin_halt_forced_clk =
  1544. _sde_plane_halt_requests(plane, psde->pipe_hw->cap->xin_id,
  1545. psde->xin_halt_forced_clk, enable);
  1546. }
  1547. void sde_plane_secure_ctrl_xin_client(struct drm_plane *plane,
  1548. struct drm_crtc *crtc)
  1549. {
  1550. struct sde_plane *psde;
  1551. if (!plane || !crtc) {
  1552. SDE_ERROR("invalid plane/crtc\n");
  1553. return;
  1554. }
  1555. psde = to_sde_plane(plane);
  1556. if (psde->features & BIT(SDE_SSPP_BLOCK_SEC_UI))
  1557. return;
  1558. /* do all VBIF programming for the sec-ui allowed SSPP */
  1559. _sde_plane_set_qos_remap(plane);
  1560. _sde_plane_set_ot_limit(plane, crtc);
  1561. }
  1562. /**
  1563. * sde_plane_rot_install_properties - install plane rotator properties
  1564. * @plane: Pointer to drm plane
  1565. * @catalog: Pointer to mdss configuration
  1566. * return: none
  1567. */
  1568. static void sde_plane_rot_install_properties(struct drm_plane *plane,
  1569. struct sde_mdss_cfg *catalog)
  1570. {
  1571. struct sde_plane *psde = to_sde_plane(plane);
  1572. unsigned int supported_rotations = DRM_MODE_ROTATE_0 |
  1573. DRM_MODE_ROTATE_180 | DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y;
  1574. int ret = 0;
  1575. if (!plane || !psde) {
  1576. SDE_ERROR("invalid plane\n");
  1577. return;
  1578. } else if (!catalog) {
  1579. SDE_ERROR("invalid catalog\n");
  1580. return;
  1581. }
  1582. if (!psde->is_virtual && psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT))
  1583. supported_rotations |= DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270;
  1584. ret = drm_plane_create_rotation_property(plane,
  1585. DRM_MODE_ROTATE_0, supported_rotations);
  1586. if (ret) {
  1587. DRM_ERROR("create rotation property failed: %d\n", ret);
  1588. return;
  1589. }
  1590. }
  1591. void sde_plane_clear_multirect(const struct drm_plane_state *drm_state)
  1592. {
  1593. struct sde_plane_state *pstate;
  1594. if (!drm_state)
  1595. return;
  1596. pstate = to_sde_plane_state(drm_state);
  1597. pstate->multirect_index = SDE_SSPP_RECT_SOLO;
  1598. pstate->multirect_mode = SDE_SSPP_MULTIRECT_NONE;
  1599. }
  1600. /**
  1601. * multi_rect validate API allows to validate only R0 and R1 RECT
  1602. * passing for each plane. Client of this API must not pass multiple
  1603. * plane which are not sharing same XIN client. Such calls will fail
  1604. * even though kernel client is passing valid multirect configuration.
  1605. */
  1606. int sde_plane_validate_multirect_v2(struct sde_multirect_plane_states *plane)
  1607. {
  1608. struct sde_plane_state *pstate[R_MAX];
  1609. const struct drm_plane_state *drm_state[R_MAX];
  1610. struct sde_rect src[R_MAX], dst[R_MAX];
  1611. struct sde_plane *sde_plane[R_MAX];
  1612. const struct sde_format *fmt[R_MAX];
  1613. int xin_id[R_MAX];
  1614. bool q16_data = true;
  1615. int i, j, buffer_lines, width_threshold[R_MAX];
  1616. unsigned int max_tile_height = 1;
  1617. bool parallel_fetch_qualified = true;
  1618. enum sde_sspp_multirect_mode mode = SDE_SSPP_MULTIRECT_NONE;
  1619. const struct msm_format *msm_fmt;
  1620. bool const_alpha_enable = true;
  1621. for (i = 0; i < R_MAX; i++) {
  1622. drm_state[i] = i ? plane->r1 : plane->r0;
  1623. if (!drm_state[i]) {
  1624. SDE_ERROR("drm plane state is NULL\n");
  1625. return -EINVAL;
  1626. }
  1627. pstate[i] = to_sde_plane_state(drm_state[i]);
  1628. sde_plane[i] = to_sde_plane(drm_state[i]->plane);
  1629. xin_id[i] = sde_plane[i]->pipe_hw->cap->xin_id;
  1630. for (j = 0; j < i; j++) {
  1631. if (xin_id[i] != xin_id[j]) {
  1632. SDE_ERROR_PLANE(sde_plane[i],
  1633. "invalid multirect validate call base:%d xin_id:%d curr:%d xin:%d\n",
  1634. j, xin_id[j], i, xin_id[i]);
  1635. return -EINVAL;
  1636. }
  1637. }
  1638. msm_fmt = msm_framebuffer_format(drm_state[i]->fb);
  1639. if (!msm_fmt) {
  1640. SDE_ERROR_PLANE(sde_plane[i], "null fb\n");
  1641. return -EINVAL;
  1642. }
  1643. fmt[i] = to_sde_format(msm_fmt);
  1644. if (SDE_FORMAT_IS_UBWC(fmt[i]) &&
  1645. (fmt[i]->tile_height > max_tile_height))
  1646. max_tile_height = fmt[i]->tile_height;
  1647. POPULATE_RECT(&src[i], drm_state[i]->src_x, drm_state[i]->src_y,
  1648. drm_state[i]->src_w, drm_state[i]->src_h, q16_data);
  1649. POPULATE_RECT(&dst[i], drm_state[i]->crtc_x,
  1650. drm_state[i]->crtc_y, drm_state[i]->crtc_w,
  1651. drm_state[i]->crtc_h, !q16_data);
  1652. if (src[i].w != dst[i].w || src[i].h != dst[i].h) {
  1653. SDE_ERROR_PLANE(sde_plane[i],
  1654. "scaling is not supported in multirect mode\n");
  1655. return -EINVAL;
  1656. }
  1657. if (pstate[i]->rotation & DRM_MODE_ROTATE_90) {
  1658. SDE_ERROR_PLANE(sde_plane[i],
  1659. "inline rotation is not supported in mulirect mode\n");
  1660. return -EINVAL;
  1661. }
  1662. if (SDE_FORMAT_IS_YUV(fmt[i])) {
  1663. SDE_ERROR_PLANE(sde_plane[i],
  1664. "Unsupported format for multirect mode\n");
  1665. return -EINVAL;
  1666. }
  1667. /**
  1668. * SSPP PD_MEM is split half - one for each RECT.
  1669. * Tiled formats need 5 lines of buffering while fetching
  1670. * whereas linear formats need only 2 lines.
  1671. * So we cannot support more than half of the supported SSPP
  1672. * width for tiled formats.
  1673. */
  1674. width_threshold[i] = sde_plane[i]->pipe_sblk->maxlinewidth;
  1675. if (SDE_FORMAT_IS_UBWC(fmt[i]))
  1676. width_threshold[i] /= 2;
  1677. if (parallel_fetch_qualified && src[i].w > width_threshold[i])
  1678. parallel_fetch_qualified = false;
  1679. if (sde_plane[i]->is_virtual)
  1680. mode = sde_plane_get_property(pstate[i],
  1681. PLANE_PROP_MULTIRECT_MODE);
  1682. if (pstate[i]->const_alpha_en != const_alpha_enable)
  1683. const_alpha_enable = false;
  1684. }
  1685. buffer_lines = 2 * max_tile_height;
  1686. /**
  1687. * fallback to driver mode selection logic if client is using
  1688. * multirect plane without setting property.
  1689. *
  1690. * validate multirect mode configuration based on rectangle
  1691. */
  1692. switch (mode) {
  1693. case SDE_SSPP_MULTIRECT_NONE:
  1694. if (parallel_fetch_qualified)
  1695. mode = SDE_SSPP_MULTIRECT_PARALLEL;
  1696. else if (TIME_MULTIPLEX_RECT(dst[R1], dst[R0], buffer_lines) ||
  1697. TIME_MULTIPLEX_RECT(dst[R0], dst[R1], buffer_lines))
  1698. mode = SDE_SSPP_MULTIRECT_TIME_MX;
  1699. else
  1700. SDE_ERROR(
  1701. "planes(%d - %d) multirect mode selection fail\n",
  1702. drm_state[R0]->plane->base.id,
  1703. drm_state[R1]->plane->base.id);
  1704. break;
  1705. case SDE_SSPP_MULTIRECT_PARALLEL:
  1706. if (!parallel_fetch_qualified) {
  1707. SDE_ERROR("R0 plane:%d width_threshold:%d src_w:%d\n",
  1708. drm_state[R0]->plane->base.id,
  1709. width_threshold[R0], src[R0].w);
  1710. SDE_ERROR("R1 plane:%d width_threshold:%d src_w:%d\n",
  1711. drm_state[R1]->plane->base.id,
  1712. width_threshold[R1], src[R1].w);
  1713. SDE_ERROR("parallel fetch not qualified\n");
  1714. mode = SDE_SSPP_MULTIRECT_NONE;
  1715. }
  1716. break;
  1717. case SDE_SSPP_MULTIRECT_TIME_MX:
  1718. if (!TIME_MULTIPLEX_RECT(dst[R1], dst[R0], buffer_lines) &&
  1719. !TIME_MULTIPLEX_RECT(dst[R0], dst[R1], buffer_lines)) {
  1720. SDE_ERROR(
  1721. "buffer_lines:%d R0 plane:%d dst_y:%d dst_h:%d\n",
  1722. buffer_lines, drm_state[R0]->plane->base.id,
  1723. dst[R0].y, dst[R0].h);
  1724. SDE_ERROR(
  1725. "buffer_lines:%d R1 plane:%d dst_y:%d dst_h:%d\n",
  1726. buffer_lines, drm_state[R1]->plane->base.id,
  1727. dst[R1].y, dst[R1].h);
  1728. SDE_ERROR("time multiplexed fetch not qualified\n");
  1729. mode = SDE_SSPP_MULTIRECT_NONE;
  1730. }
  1731. break;
  1732. default:
  1733. SDE_ERROR("bad mode:%d selection\n", mode);
  1734. mode = SDE_SSPP_MULTIRECT_NONE;
  1735. break;
  1736. }
  1737. for (i = 0; i < R_MAX; i++) {
  1738. pstate[i]->multirect_mode = mode;
  1739. pstate[i]->const_alpha_en = const_alpha_enable;
  1740. }
  1741. if (mode == SDE_SSPP_MULTIRECT_NONE)
  1742. return -EINVAL;
  1743. if (sde_plane[R0]->is_virtual) {
  1744. pstate[R0]->multirect_index = SDE_SSPP_RECT_1;
  1745. pstate[R1]->multirect_index = SDE_SSPP_RECT_0;
  1746. } else {
  1747. pstate[R0]->multirect_index = SDE_SSPP_RECT_0;
  1748. pstate[R1]->multirect_index = SDE_SSPP_RECT_1;
  1749. }
  1750. SDE_DEBUG_PLANE(sde_plane[R0], "R0: %d - %d\n",
  1751. pstate[R0]->multirect_mode, pstate[R0]->multirect_index);
  1752. SDE_DEBUG_PLANE(sde_plane[R1], "R1: %d - %d\n",
  1753. pstate[R1]->multirect_mode, pstate[R1]->multirect_index);
  1754. return 0;
  1755. }
  1756. /**
  1757. * sde_plane_ctl_flush - set/clear control flush bitmask for the given plane
  1758. * @plane: Pointer to drm plane structure
  1759. * @ctl: Pointer to hardware control driver
  1760. * @set: set if true else clear
  1761. */
  1762. void sde_plane_ctl_flush(struct drm_plane *plane, struct sde_hw_ctl *ctl,
  1763. bool set)
  1764. {
  1765. if (!plane || !ctl) {
  1766. SDE_ERROR("invalid parameters\n");
  1767. return;
  1768. }
  1769. if (!ctl->ops.update_bitmask_sspp) {
  1770. SDE_ERROR("invalid ops\n");
  1771. return;
  1772. }
  1773. ctl->ops.update_bitmask_sspp(ctl, sde_plane_pipe(plane), set);
  1774. }
  1775. static int sde_plane_prepare_fb(struct drm_plane *plane,
  1776. struct drm_plane_state *new_state)
  1777. {
  1778. struct drm_framebuffer *fb = new_state->fb;
  1779. struct sde_plane *psde = to_sde_plane(plane);
  1780. struct sde_plane_state *pstate = to_sde_plane_state(new_state);
  1781. struct sde_hw_fmt_layout layout;
  1782. struct msm_gem_address_space *aspace;
  1783. int ret, mode;
  1784. if (!fb)
  1785. return 0;
  1786. SDE_DEBUG_PLANE(psde, "FB[%u]\n", fb->base.id);
  1787. ret = _sde_plane_get_aspace(psde, pstate, &aspace);
  1788. if (ret) {
  1789. SDE_ERROR_PLANE(psde, "Failed to get aspace\n");
  1790. return ret;
  1791. }
  1792. /* cache aspace */
  1793. pstate->aspace = aspace;
  1794. /*
  1795. * when transitioning from secure to non-secure,
  1796. * plane->prepare_fb happens before the commit. In such case,
  1797. * defer the prepare_fb and handled it late, during the commit
  1798. * after attaching the domains as part of the transition
  1799. */
  1800. pstate->defer_prepare_fb = (aspace && !aspace->domain_attached) ?
  1801. true : false;
  1802. if (pstate->defer_prepare_fb) {
  1803. SDE_EVT32(DRMID(plane), psde->pipe);
  1804. SDE_DEBUG_PLANE(psde,
  1805. "domain not attached, prepare_fb handled later\n");
  1806. return 0;
  1807. }
  1808. if (pstate->aspace && fb) {
  1809. ret = msm_framebuffer_prepare(fb,
  1810. pstate->aspace);
  1811. if (ret) {
  1812. SDE_ERROR("failed to prepare framebuffer fb:%d plane:%d pipe:%d ret:%d\n",
  1813. fb->base.id, plane->base.id, psde->pipe, ret);
  1814. SDE_EVT32(fb->base.id, plane->base.id, psde->pipe, ret, SDE_EVTLOG_ERROR);
  1815. return ret;
  1816. }
  1817. }
  1818. /*
  1819. * Avoid mapping during the validate phase for S2-only buffer & CSF-2.5.
  1820. * _sde_plane_set_scanout can handle the mapping after the scm_call during commit.
  1821. */
  1822. mode = sde_plane_get_property(pstate, PLANE_PROP_FB_TRANSLATION_MODE);
  1823. if (mode != SDE_DRM_FB_SEC_DIR_TRANS) {
  1824. /* validate framebuffer layout before commit */
  1825. ret = sde_format_populate_layout(pstate->aspace, fb, &layout);
  1826. if (ret) {
  1827. SDE_ERROR_PLANE(psde, "failed to get format layout, %d\n", ret);
  1828. return ret;
  1829. }
  1830. } else {
  1831. SDE_DEBUG("deferring dma-buf mapping to commit phase\n");
  1832. SDE_EVT32(DRMID(plane), fb->base.id, mode);
  1833. }
  1834. return 0;
  1835. }
  1836. static void sde_plane_cleanup_fb(struct drm_plane *plane,
  1837. struct drm_plane_state *old_state)
  1838. {
  1839. struct sde_plane *psde = to_sde_plane(plane);
  1840. struct sde_plane_state *old_pstate;
  1841. if (!old_state || !old_state->fb || !plane)
  1842. return;
  1843. old_pstate = to_sde_plane_state(old_state);
  1844. SDE_DEBUG_PLANE(psde, "FB[%u]\n", old_state->fb->base.id);
  1845. msm_framebuffer_cleanup(old_state->fb, old_pstate->aspace);
  1846. }
  1847. static void _sde_plane_sspp_atomic_check_mode_changed(struct sde_plane *psde,
  1848. struct drm_plane_state *state,
  1849. struct drm_plane_state *old_state)
  1850. {
  1851. struct sde_plane_state *pstate = to_sde_plane_state(state);
  1852. struct sde_plane_state *old_pstate = to_sde_plane_state(old_state);
  1853. struct drm_framebuffer *fb, *old_fb;
  1854. /* no need to check it again */
  1855. if (pstate->dirty == SDE_PLANE_DIRTY_ALL)
  1856. return;
  1857. if (!sde_plane_enabled(state) || !sde_plane_enabled(old_state)
  1858. || psde->is_error) {
  1859. SDE_DEBUG_PLANE(psde,
  1860. "enabling/disabling full modeset required\n");
  1861. pstate->dirty |= SDE_PLANE_DIRTY_ALL;
  1862. } else if (to_sde_plane_state(old_state)->pending) {
  1863. SDE_DEBUG_PLANE(psde, "still pending\n");
  1864. pstate->dirty |= SDE_PLANE_DIRTY_ALL;
  1865. } else if (pstate->multirect_index != old_pstate->multirect_index ||
  1866. pstate->multirect_mode != old_pstate->multirect_mode) {
  1867. SDE_DEBUG_PLANE(psde, "multirect config updated\n");
  1868. pstate->dirty |= SDE_PLANE_DIRTY_ALL;
  1869. } else if (state->src_w != old_state->src_w ||
  1870. state->src_h != old_state->src_h ||
  1871. state->src_x != old_state->src_x ||
  1872. state->src_y != old_state->src_y) {
  1873. SDE_DEBUG_PLANE(psde, "src rect updated\n");
  1874. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1875. } else if (state->crtc_w != old_state->crtc_w ||
  1876. state->crtc_h != old_state->crtc_h ||
  1877. state->crtc_x != old_state->crtc_x ||
  1878. state->crtc_y != old_state->crtc_y) {
  1879. SDE_DEBUG_PLANE(psde, "crtc rect updated\n");
  1880. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1881. } else if (pstate->excl_rect.w != old_pstate->excl_rect.w ||
  1882. pstate->excl_rect.h != old_pstate->excl_rect.h ||
  1883. pstate->excl_rect.x != old_pstate->excl_rect.x ||
  1884. pstate->excl_rect.y != old_pstate->excl_rect.y) {
  1885. SDE_DEBUG_PLANE(psde, "excl_rect updated\n");
  1886. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1887. } else if (pstate->rotation != old_pstate->rotation) {
  1888. SDE_DEBUG_PLANE(psde, "rotation updated 0x%x->0x%x\n",
  1889. pstate->rotation, old_pstate->rotation);
  1890. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT;
  1891. }
  1892. fb = state->fb;
  1893. old_fb = old_state->fb;
  1894. if (!fb || !old_fb) {
  1895. SDE_DEBUG_PLANE(psde, "can't compare fb handles\n");
  1896. } else if ((fb->format->format != old_fb->format->format) ||
  1897. pstate->const_alpha_en != old_pstate->const_alpha_en) {
  1898. SDE_DEBUG_PLANE(psde, "format change\n");
  1899. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT | SDE_PLANE_DIRTY_RECTS;
  1900. } else {
  1901. uint64_t new_mod = fb->modifier;
  1902. uint64_t old_mod = old_fb->modifier;
  1903. uint32_t *new_pitches = fb->pitches;
  1904. uint32_t *old_pitches = old_fb->pitches;
  1905. uint32_t *new_offset = fb->offsets;
  1906. uint32_t *old_offset = old_fb->offsets;
  1907. int i;
  1908. if (new_mod != old_mod) {
  1909. SDE_DEBUG_PLANE(psde,
  1910. "format modifiers change new_mode:%llu old_mode:%llu\n",
  1911. new_mod, old_mod);
  1912. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT |
  1913. SDE_PLANE_DIRTY_RECTS;
  1914. }
  1915. for (i = 0; i < ARRAY_SIZE(fb->pitches); i++) {
  1916. if (new_pitches[i] != old_pitches[i]) {
  1917. SDE_DEBUG_PLANE(psde,
  1918. "pitches change plane:%d old_pitches:%u new_pitches:%u\n",
  1919. i, old_pitches[i], new_pitches[i]);
  1920. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1921. break;
  1922. }
  1923. }
  1924. for (i = 0; i < ARRAY_SIZE(fb->offsets); i++) {
  1925. if (new_offset[i] != old_offset[i]) {
  1926. SDE_DEBUG_PLANE(psde,
  1927. "offset change plane:%d old_offset:%u new_offset:%u\n",
  1928. i, old_offset[i], new_offset[i]);
  1929. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT |
  1930. SDE_PLANE_DIRTY_RECTS;
  1931. break;
  1932. }
  1933. }
  1934. }
  1935. }
  1936. int sde_plane_validate_src_addr(struct drm_plane *plane,
  1937. unsigned long base_addr, u32 size)
  1938. {
  1939. int ret = -EINVAL;
  1940. u32 addr;
  1941. struct sde_plane *psde = to_sde_plane(plane);
  1942. if (!psde || !base_addr || !size) {
  1943. SDE_ERROR_PLANE(psde, "invalid arguments\n");
  1944. return ret;
  1945. }
  1946. if (psde->pipe_hw && psde->pipe_hw->ops.get_sourceaddress) {
  1947. addr = psde->pipe_hw->ops.get_sourceaddress(psde->pipe_hw,
  1948. is_sde_plane_virtual(plane));
  1949. if ((addr >= base_addr) && (addr < (base_addr + size)))
  1950. ret = 0;
  1951. }
  1952. return ret;
  1953. }
  1954. static inline bool _sde_plane_is_pre_downscale_enabled(
  1955. struct sde_hw_inline_pre_downscale_cfg *pre_down)
  1956. {
  1957. return pre_down->pre_downscale_x_0 || pre_down->pre_downscale_y_0;
  1958. }
  1959. static int _sde_plane_validate_scaler_v2(struct sde_plane *psde,
  1960. struct sde_plane_state *pstate,
  1961. const struct sde_format *fmt,
  1962. uint32_t img_w, uint32_t img_h,
  1963. uint32_t src_w, uint32_t src_h,
  1964. uint32_t deci_w, uint32_t deci_h)
  1965. {
  1966. struct sde_hw_inline_pre_downscale_cfg *pd_cfg;
  1967. bool pre_down_en;
  1968. int i;
  1969. if (!psde || !pstate || !fmt) {
  1970. SDE_ERROR_PLANE(psde, "invalid arguments\n");
  1971. return -EINVAL;
  1972. }
  1973. if (psde->debugfs_default_scale ||
  1974. (pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2 &&
  1975. pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2_CHECK))
  1976. return 0;
  1977. pd_cfg = &pstate->pre_down;
  1978. pre_down_en = _sde_plane_is_pre_downscale_enabled(pd_cfg);
  1979. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_INVALID;
  1980. for (i = 0; i < SDE_MAX_PLANES; i++) {
  1981. uint32_t hor_req_pixels, hor_fetch_pixels;
  1982. uint32_t vert_req_pixels, vert_fetch_pixels;
  1983. uint32_t src_w_tmp, src_h_tmp;
  1984. uint32_t scaler_w, scaler_h;
  1985. uint32_t pre_down_ratio_x = 1, pre_down_ratio_y = 1;
  1986. bool rot;
  1987. /* re-use color plane 1's config for plane 2 */
  1988. if (i == 2)
  1989. continue;
  1990. if (pre_down_en) {
  1991. if (i == 0 && pd_cfg->pre_downscale_x_0)
  1992. pre_down_ratio_x = pd_cfg->pre_downscale_x_0;
  1993. if (i == 0 && pd_cfg->pre_downscale_y_0)
  1994. pre_down_ratio_y = pd_cfg->pre_downscale_y_0;
  1995. if ((i == 1 || i == 2) && pd_cfg->pre_downscale_x_1)
  1996. pre_down_ratio_x = pd_cfg->pre_downscale_x_1;
  1997. if ((i == 1 || i == 2) && pd_cfg->pre_downscale_y_1)
  1998. pre_down_ratio_y = pd_cfg->pre_downscale_y_1;
  1999. SDE_DEBUG_PLANE(psde, "pre_down[%d]: x:%d, y:%d\n",
  2000. i, pre_down_ratio_x, pre_down_ratio_y);
  2001. }
  2002. src_w_tmp = src_w;
  2003. src_h_tmp = src_h;
  2004. /*
  2005. * For chroma plane, width is half for the following sub sampled
  2006. * formats. Except in case of decimation, where hardware avoids
  2007. * 1 line of decimation instead of downsampling.
  2008. */
  2009. if (i == 1) {
  2010. if (!deci_w &&
  2011. (fmt->chroma_sample == SDE_CHROMA_420 ||
  2012. fmt->chroma_sample == SDE_CHROMA_H2V1))
  2013. src_w_tmp >>= 1;
  2014. if (!deci_h &&
  2015. (fmt->chroma_sample == SDE_CHROMA_420 ||
  2016. fmt->chroma_sample == SDE_CHROMA_H1V2))
  2017. src_h_tmp >>= 1;
  2018. }
  2019. hor_req_pixels = pstate->pixel_ext.roi_w[i];
  2020. vert_req_pixels = pstate->pixel_ext.roi_h[i];
  2021. hor_fetch_pixels = DECIMATED_DIMENSION(src_w_tmp +
  2022. (int8_t)(pstate->pixel_ext.left_ftch[i] & 0xFF) +
  2023. (int8_t)(pstate->pixel_ext.right_ftch[i] & 0xFF),
  2024. deci_w);
  2025. vert_fetch_pixels = DECIMATED_DIMENSION(src_h_tmp +
  2026. (int8_t)(pstate->pixel_ext.top_ftch[i] & 0xFF) +
  2027. (int8_t)(pstate->pixel_ext.btm_ftch[i] & 0xFF),
  2028. deci_h);
  2029. if ((hor_req_pixels != hor_fetch_pixels) ||
  2030. (hor_fetch_pixels > img_w) ||
  2031. (vert_req_pixels != vert_fetch_pixels) ||
  2032. (vert_fetch_pixels > img_h)) {
  2033. SDE_ERROR_PLANE(psde,
  2034. "req %d/%d, fetch %d/%d, src %dx%d\n",
  2035. hor_req_pixels, vert_req_pixels,
  2036. hor_fetch_pixels, vert_fetch_pixels,
  2037. img_w, img_h);
  2038. return -EINVAL;
  2039. }
  2040. /*
  2041. * swap the scaler src width & height for inline-rotation 90
  2042. * comparison with Pixel-Extension, as PE is based on
  2043. * pre-rotation and QSEED is based on post-rotation
  2044. */
  2045. rot = pstate->rotation & DRM_MODE_ROTATE_90;
  2046. scaler_w = rot ? pstate->scaler3_cfg.src_height[i]
  2047. : pstate->scaler3_cfg.src_width[i];
  2048. scaler_h = rot ? pstate->scaler3_cfg.src_width[i]
  2049. : pstate->scaler3_cfg.src_height[i];
  2050. /*
  2051. * Alpha plane can only be scaled using bilinear or pixel
  2052. * repeat/drop, src_width and src_height are only specified
  2053. * for Y and UV plane
  2054. */
  2055. if (i != 3 && (hor_req_pixels / pre_down_ratio_x != scaler_w ||
  2056. vert_req_pixels / pre_down_ratio_y !=
  2057. scaler_h)) {
  2058. SDE_ERROR_PLANE(psde,
  2059. "roi[%d] roi:%dx%d scaler:%dx%d src:%dx%d rot:%d pd:%d/%d\n",
  2060. i, pstate->pixel_ext.roi_w[i],
  2061. pstate->pixel_ext.roi_h[i], scaler_w, scaler_h,
  2062. src_w, src_h, rot, pre_down_ratio_x, pre_down_ratio_y);
  2063. return -EINVAL;
  2064. }
  2065. /*
  2066. * SSPP fetch , unpack output and QSEED3 input lines need
  2067. * to match for Y plane
  2068. */
  2069. if (i == 0 &&
  2070. (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) &
  2071. BIT(SDE_DRM_DEINTERLACE)) &&
  2072. ((pstate->scaler3_cfg.src_height[i] != (src_h/2)) ||
  2073. (pstate->pixel_ext.roi_h[i] != (src_h/2)))) {
  2074. SDE_ERROR_PLANE(psde,
  2075. "de-interlace fail roi[%d] %d/%d, src %dx%d, src %dx%d\n",
  2076. i, pstate->pixel_ext.roi_w[i],
  2077. pstate->pixel_ext.roi_h[i],
  2078. pstate->scaler3_cfg.src_width[i],
  2079. pstate->scaler3_cfg.src_height[i],
  2080. src_w, src_h);
  2081. return -EINVAL;
  2082. }
  2083. }
  2084. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_SCALER_V2;
  2085. return 0;
  2086. }
  2087. static inline bool _sde_plane_has_pre_downscale(struct sde_plane *psde)
  2088. {
  2089. return (psde->features & BIT(SDE_SSPP_PREDOWNSCALE));
  2090. }
  2091. static int _sde_atomic_check_pre_downscale(struct sde_plane *psde,
  2092. struct sde_plane_state *pstate, struct sde_rect *dst,
  2093. u32 src_w, u32 src_h)
  2094. {
  2095. int ret = 0;
  2096. u32 min_ratio_numer, min_ratio_denom;
  2097. struct sde_hw_inline_pre_downscale_cfg *pd_cfg = &pstate->pre_down;
  2098. bool pd_x;
  2099. bool pd_y;
  2100. if (!_sde_plane_is_pre_downscale_enabled(pd_cfg))
  2101. return ret;
  2102. pd_x = pd_cfg->pre_downscale_x_0 > 1;
  2103. pd_y = pd_cfg->pre_downscale_y_0 > 1;
  2104. min_ratio_numer = psde->pipe_sblk->in_rot_maxdwnscale_rt_nopd_num;
  2105. min_ratio_denom = psde->pipe_sblk->in_rot_maxdwnscale_rt_nopd_denom;
  2106. if (pd_x && !_sde_plane_has_pre_downscale(psde)) {
  2107. SDE_ERROR_PLANE(psde,
  2108. "hw does not support pre-downscale X: 0x%x\n",
  2109. psde->features);
  2110. ret = -EINVAL;
  2111. } else if (pd_y && !(psde->features & BIT(SDE_SSPP_PREDOWNSCALE_Y))) {
  2112. SDE_ERROR_PLANE(psde,
  2113. "hw does not support pre-downscale Y: 0x%x\n",
  2114. psde->features);
  2115. ret = -EINVAL;
  2116. } else if (!min_ratio_numer || !min_ratio_denom) {
  2117. SDE_ERROR_PLANE(psde,
  2118. "min downscale ratio not set! %u / %u\n",
  2119. min_ratio_numer, min_ratio_denom);
  2120. ret = -EINVAL;
  2121. /* compare pre-rotated src w/h with post-rotated dst h/w resp. */
  2122. } else if (pd_x && (src_w < mult_frac(dst->h, min_ratio_numer,
  2123. min_ratio_denom))) {
  2124. SDE_ERROR_PLANE(psde,
  2125. "failed min downscale-x check %u->%u, %u/%u\n",
  2126. src_w, dst->h, min_ratio_numer, min_ratio_denom);
  2127. ret = -EINVAL;
  2128. } else if (pd_y && (src_h < mult_frac(dst->w, min_ratio_numer,
  2129. min_ratio_denom))) {
  2130. SDE_ERROR_PLANE(psde,
  2131. "failed min downscale-y check %u->%u, %u/%u\n",
  2132. src_h, dst->w, min_ratio_numer, min_ratio_denom);
  2133. ret = -EINVAL;
  2134. }
  2135. return ret;
  2136. }
  2137. static void _sde_plane_get_max_downscale_limits(struct sde_plane *psde,
  2138. struct sde_plane_state *pstate, bool rt_client, u32 dst_h,
  2139. u32 src_h, u32 *max_numer_w, u32 *max_denom_w,
  2140. u32 *max_numer_h, u32 *max_denom_h)
  2141. {
  2142. bool rotated, has_predown, default_scale;
  2143. const struct sde_sspp_sub_blks *sblk;
  2144. struct sde_hw_inline_pre_downscale_cfg *pd = NULL;
  2145. rotated = pstate->rotation & DRM_MODE_ROTATE_90;
  2146. sblk = psde->pipe_sblk;
  2147. *max_numer_w = sblk->maxdwnscale;
  2148. *max_denom_w = 1;
  2149. *max_numer_h = sblk->maxdwnscale;
  2150. *max_denom_h = 1;
  2151. has_predown = _sde_plane_has_pre_downscale(psde);
  2152. if (has_predown)
  2153. pd = &pstate->pre_down;
  2154. default_scale = psde->debugfs_default_scale ||
  2155. (pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2 &&
  2156. pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2_CHECK);
  2157. /**
  2158. * Inline rotation has different max vertical downscaling limits since
  2159. * the source-width becomes the scaler's pre-downscaled source-height.
  2160. **/
  2161. if (rotated) {
  2162. if (pd != NULL && rt_client && has_predown) {
  2163. if (default_scale)
  2164. pd->pre_downscale_x_0 = (src_h >
  2165. mult_frac(dst_h, 11, 5)) ? 2 : 0;
  2166. *max_numer_h = pd->pre_downscale_x_0 ?
  2167. sblk->in_rot_maxdwnscale_rt_num :
  2168. sblk->in_rot_maxdwnscale_rt_nopd_num;
  2169. *max_denom_h = pd->pre_downscale_x_0 ?
  2170. sblk->in_rot_maxdwnscale_rt_denom :
  2171. sblk->in_rot_maxdwnscale_rt_nopd_denom;
  2172. } else if (rt_client) {
  2173. *max_numer_h = sblk->in_rot_maxdwnscale_rt_num;
  2174. *max_denom_h = sblk->in_rot_maxdwnscale_rt_denom;
  2175. } else {
  2176. *max_numer_h = sblk->in_rot_maxdwnscale_nrt;
  2177. }
  2178. }
  2179. }
  2180. static int _sde_atomic_check_decimation_scaler(struct drm_plane_state *state,
  2181. struct sde_plane *psde, const struct sde_format *fmt,
  2182. struct sde_plane_state *pstate, struct sde_rect *src,
  2183. struct sde_rect *dst, u32 width, u32 height)
  2184. {
  2185. int ret = 0;
  2186. uint32_t deci_w, deci_h, src_deci_w, src_deci_h;
  2187. uint32_t scaler_src_w, scaler_src_h;
  2188. uint32_t max_downscale_num_w, max_downscale_denom_w;
  2189. uint32_t max_downscale_num_h, max_downscale_denom_h;
  2190. uint32_t max_upscale, max_linewidth;
  2191. bool inline_rotation, rt_client;
  2192. struct drm_crtc *crtc;
  2193. struct drm_crtc_state *new_cstate;
  2194. const struct sde_sspp_sub_blks *sblk;
  2195. if (!state || !state->state || !state->crtc) {
  2196. SDE_ERROR_PLANE(psde, "invalid arguments\n");
  2197. return -EINVAL;
  2198. }
  2199. deci_w = sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
  2200. deci_h = sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
  2201. src_deci_w = DECIMATED_DIMENSION(src->w, deci_w);
  2202. src_deci_h = DECIMATED_DIMENSION(src->h, deci_h);
  2203. /* with inline rotator, the source of the scaler is post-rotated */
  2204. inline_rotation = pstate->rotation & DRM_MODE_ROTATE_90 ? true : false;
  2205. if (inline_rotation) {
  2206. scaler_src_w = src_deci_h;
  2207. scaler_src_h = src_deci_w;
  2208. } else {
  2209. scaler_src_w = src_deci_w;
  2210. scaler_src_h = src_deci_h;
  2211. }
  2212. sblk = psde->pipe_sblk;
  2213. max_upscale = sblk->maxupscale;
  2214. if (inline_rotation)
  2215. max_linewidth = sblk->in_rot_maxheight;
  2216. else if (scaler_src_w != state->crtc_w || scaler_src_h != state->crtc_h)
  2217. max_linewidth = sblk->scaling_linewidth;
  2218. else
  2219. max_linewidth = sblk->maxlinewidth;
  2220. crtc = state->crtc;
  2221. new_cstate = drm_atomic_get_new_crtc_state(state->state, crtc);
  2222. rt_client = sde_crtc_is_rt_client(crtc, new_cstate);
  2223. _sde_plane_get_max_downscale_limits(psde, pstate, rt_client, dst->h,
  2224. scaler_src_h, &max_downscale_num_w, &max_downscale_denom_w,
  2225. &max_downscale_num_h, &max_downscale_denom_h);
  2226. /* decimation validation */
  2227. if ((deci_w || deci_h)
  2228. && ((deci_w > sblk->maxhdeciexp)
  2229. || (deci_h > sblk->maxvdeciexp))) {
  2230. SDE_ERROR_PLANE(psde, "too much decimation requested\n");
  2231. ret = -EINVAL;
  2232. } else if ((deci_w || deci_h)
  2233. && (fmt->fetch_mode != SDE_FETCH_LINEAR)) {
  2234. SDE_ERROR_PLANE(psde, "decimation requires linear fetch\n");
  2235. ret = -EINVAL;
  2236. } else if (!(psde->features & SDE_SSPP_SCALER) &&
  2237. ((src->w != dst->w) || (src->h != dst->h))) {
  2238. SDE_ERROR_PLANE(psde,
  2239. "pipe doesn't support scaling %ux%u->%ux%u\n",
  2240. src->w, src->h, dst->w, dst->h);
  2241. ret = -EINVAL;
  2242. /* check scaler source width */
  2243. } else if (scaler_src_w > max_linewidth) {
  2244. SDE_ERROR_PLANE(psde,
  2245. "invalid src w:%u, scaler w:%u, line w:%u, rot: %d\n",
  2246. src->w, scaler_src_w, max_linewidth, inline_rotation);
  2247. ret = -E2BIG;
  2248. /* check max scaler capability */
  2249. } else if (((scaler_src_w * max_upscale) < dst->w) ||
  2250. ((scaler_src_h * max_upscale) < dst->h) ||
  2251. (mult_frac(dst->w, max_downscale_num_w, max_downscale_denom_w)
  2252. < scaler_src_w) ||
  2253. (mult_frac(dst->h, max_downscale_num_h, max_downscale_denom_h)
  2254. < scaler_src_h)) {
  2255. SDE_ERROR_PLANE(psde,
  2256. "too much scaling %ux%u->%ux%u rot:%d dwn:%d/%d %d/%d\n",
  2257. scaler_src_w, scaler_src_h, dst->w, dst->h,
  2258. inline_rotation, max_downscale_num_w,
  2259. max_downscale_denom_w, max_downscale_num_h,
  2260. max_downscale_denom_h);
  2261. ret = -E2BIG;
  2262. /* check inline pre-downscale support */
  2263. } else if (inline_rotation && _sde_atomic_check_pre_downscale(psde,
  2264. pstate, dst, src_deci_w, src_deci_h)) {
  2265. ret = -EINVAL;
  2266. /* QSEED validation */
  2267. } else if (_sde_plane_validate_scaler_v2(psde, pstate, fmt,
  2268. width, height, src->w, src->h,
  2269. deci_w, deci_h)) {
  2270. ret = -EINVAL;
  2271. }
  2272. return ret;
  2273. }
  2274. static int _sde_atomic_check_excl_rect(struct sde_plane *psde,
  2275. struct sde_plane_state *pstate, struct sde_rect *src,
  2276. const struct sde_format *fmt, int ret)
  2277. {
  2278. /* check excl rect configs */
  2279. if (!ret && pstate->excl_rect.w && pstate->excl_rect.h) {
  2280. struct sde_rect intersect;
  2281. /*
  2282. * Check exclusion rect against src rect.
  2283. * it must intersect with source rect.
  2284. */
  2285. sde_kms_rect_intersect(src, &pstate->excl_rect, &intersect);
  2286. if (intersect.w != pstate->excl_rect.w ||
  2287. intersect.h != pstate->excl_rect.h ||
  2288. SDE_FORMAT_IS_YUV(fmt)) {
  2289. SDE_ERROR_PLANE(psde,
  2290. "invalid excl_rect:{%d,%d,%d,%d} src:{%d,%d,%d,%d}, fmt: %4.4s\n",
  2291. pstate->excl_rect.x, pstate->excl_rect.y,
  2292. pstate->excl_rect.w, pstate->excl_rect.h,
  2293. src->x, src->y, src->w, src->h,
  2294. (char *)&fmt->base.pixel_format);
  2295. ret = -EINVAL;
  2296. }
  2297. SDE_DEBUG_PLANE(psde, "excl_rect: {%d,%d,%d,%d}\n",
  2298. pstate->excl_rect.x, pstate->excl_rect.y,
  2299. pstate->excl_rect.w, pstate->excl_rect.h);
  2300. }
  2301. return ret;
  2302. }
  2303. static int _sde_plane_validate_shared_crtc(struct sde_plane *psde,
  2304. struct drm_plane_state *state)
  2305. {
  2306. struct sde_kms *sde_kms;
  2307. struct sde_splash_display *splash_display;
  2308. int i;
  2309. sde_kms = _sde_plane_get_kms(&psde->base);
  2310. if (!sde_kms || !state->crtc)
  2311. return 0;
  2312. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  2313. splash_display = &sde_kms->splash_data.splash_display[i];
  2314. if (splash_display && splash_display->cont_splash_enabled &&
  2315. splash_display->encoder &&
  2316. state->crtc != splash_display->encoder->crtc) {
  2317. struct sde_sspp_index_info *pipe_info = &splash_display->pipe_info;
  2318. if (test_bit(psde->pipe, pipe_info->pipes) ||
  2319. test_bit(psde->pipe, pipe_info->virt_pipes)) {
  2320. SDE_ERROR_PLANE(psde, "pipe:%d used in cont-splash on crtc:%d\n",
  2321. psde->pipe,
  2322. splash_display->encoder->crtc->base.id);
  2323. return -EINVAL;
  2324. }
  2325. }
  2326. }
  2327. return 0;
  2328. }
  2329. static int _sde_plane_sspp_atomic_check_helper(struct sde_plane *psde,
  2330. const struct sde_format *fmt,
  2331. struct sde_rect src, struct sde_rect dst,
  2332. u32 width, u32 height)
  2333. {
  2334. int ret = 0;
  2335. u32 min_src_size = SDE_FORMAT_IS_YUV(fmt) ? 2 : 1;
  2336. if (SDE_FORMAT_IS_YUV(fmt) &&
  2337. (!(psde->features & SDE_SSPP_SCALER) ||
  2338. !(psde->features & (BIT(SDE_SSPP_CSC)
  2339. | BIT(SDE_SSPP_CSC_10BIT))))) {
  2340. SDE_ERROR_PLANE(psde,
  2341. "plane doesn't have scaler/csc for yuv\n");
  2342. ret = -EINVAL;
  2343. /* check src bounds */
  2344. } else if (width > MAX_IMG_WIDTH || height > MAX_IMG_HEIGHT ||
  2345. src.w < min_src_size || src.h < min_src_size ||
  2346. CHECK_LAYER_BOUNDS(src.x, src.w, width) ||
  2347. CHECK_LAYER_BOUNDS(src.y, src.h, height)) {
  2348. SDE_ERROR_PLANE(psde, "invalid source %u, %u, %ux%u\n",
  2349. src.x, src.y, src.w, src.h);
  2350. ret = -E2BIG;
  2351. /* valid yuv image */
  2352. } else if (SDE_FORMAT_IS_YUV(fmt) && ((src.x & 0x1) || (src.y & 0x1) ||
  2353. (src.w & 0x1) || (src.h & 0x1))) {
  2354. SDE_ERROR_PLANE(psde, "invalid yuv source %u, %u, %ux%u\n",
  2355. src.x, src.y, src.w, src.h);
  2356. ret = -EINVAL;
  2357. /* min dst support */
  2358. } else if (dst.w < 0x1 || dst.h < 0x1) {
  2359. SDE_ERROR_PLANE(psde, "invalid dest rect %u, %u, %ux%u\n",
  2360. dst.x, dst.y, dst.w, dst.h);
  2361. ret = -EINVAL;
  2362. } else if (SDE_FORMAT_IS_UBWC(fmt) &&
  2363. !psde->catalog->ubwc_rev) {
  2364. SDE_ERROR_PLANE(psde, "ubwc not supported\n");
  2365. ret = -EINVAL;
  2366. }
  2367. return ret;
  2368. }
  2369. static int sde_plane_sspp_atomic_check(struct drm_plane *plane,
  2370. struct drm_plane_state *state)
  2371. {
  2372. int ret = 0;
  2373. struct sde_plane *psde;
  2374. struct sde_plane_state *pstate;
  2375. const struct msm_format *msm_fmt;
  2376. const struct sde_format *fmt;
  2377. struct sde_rect src, dst;
  2378. bool q16_data = true;
  2379. struct drm_framebuffer *fb;
  2380. u32 width;
  2381. u32 height;
  2382. psde = to_sde_plane(plane);
  2383. pstate = to_sde_plane_state(state);
  2384. if (!psde->pipe_sblk) {
  2385. SDE_ERROR_PLANE(psde, "invalid catalog\n");
  2386. return -EINVAL;
  2387. }
  2388. /* src values are in Q16 fixed point, convert to integer */
  2389. POPULATE_RECT(&src, state->src_x, state->src_y,
  2390. state->src_w, state->src_h, q16_data);
  2391. POPULATE_RECT(&dst, state->crtc_x, state->crtc_y, state->crtc_w,
  2392. state->crtc_h, !q16_data);
  2393. SDE_DEBUG_PLANE(psde, "check %d -> %d\n",
  2394. sde_plane_enabled(plane->state), sde_plane_enabled(state));
  2395. if (!sde_plane_enabled(state))
  2396. goto modeset_update;
  2397. fb = state->fb;
  2398. width = fb ? state->fb->width : 0x0;
  2399. height = fb ? state->fb->height : 0x0;
  2400. SDE_DEBUG("plane%d sspp:%x/%dx%d/%4.4s/%llx\n",
  2401. plane->base.id,
  2402. pstate->rotation,
  2403. width, height,
  2404. fb ? (char *) &state->fb->format->format : 0x0,
  2405. fb ? state->fb->modifier : 0x0);
  2406. SDE_DEBUG("src:%dx%d %d,%d crtc:%dx%d+%d+%d\n",
  2407. state->src_w >> 16, state->src_h >> 16,
  2408. state->src_x >> 16, state->src_y >> 16,
  2409. state->crtc_w, state->crtc_h,
  2410. state->crtc_x, state->crtc_y);
  2411. msm_fmt = msm_framebuffer_format(fb);
  2412. fmt = to_sde_format(msm_fmt);
  2413. ret = _sde_plane_sspp_atomic_check_helper(psde, fmt, src, dst, width,
  2414. height);
  2415. if (ret)
  2416. return ret;
  2417. ret = _sde_atomic_check_decimation_scaler(state, psde, fmt, pstate,
  2418. &src, &dst, width, height);
  2419. if (ret)
  2420. return ret;
  2421. ret = _sde_atomic_check_excl_rect(psde, pstate,
  2422. &src, fmt, ret);
  2423. if (ret)
  2424. return ret;
  2425. ret = _sde_plane_validate_shared_crtc(psde, state);
  2426. if (ret)
  2427. return ret;
  2428. pstate->const_alpha_en = fmt->alpha_enable &&
  2429. (SDE_DRM_BLEND_OP_OPAQUE !=
  2430. sde_plane_get_property(pstate, PLANE_PROP_BLEND_OP)) &&
  2431. (pstate->stage != SDE_STAGE_0);
  2432. modeset_update:
  2433. if (!ret)
  2434. _sde_plane_sspp_atomic_check_mode_changed(psde,
  2435. state, plane->state);
  2436. return ret;
  2437. }
  2438. static int _sde_plane_atomic_check(struct drm_plane *plane,
  2439. struct drm_plane_state *state)
  2440. {
  2441. int ret = 0;
  2442. struct sde_plane *psde;
  2443. struct sde_plane_state *pstate;
  2444. psde = to_sde_plane(plane);
  2445. pstate = to_sde_plane_state(state);
  2446. SDE_DEBUG_PLANE(psde, "\n");
  2447. ret = sde_plane_rot_atomic_check(plane, state);
  2448. if (ret)
  2449. goto exit;
  2450. ret = sde_plane_sspp_atomic_check(plane, state);
  2451. exit:
  2452. return ret;
  2453. }
  2454. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
  2455. static int sde_plane_atomic_check(struct drm_plane *plane,
  2456. struct drm_atomic_state *atomic_state)
  2457. {
  2458. struct drm_plane_state *state = NULL;
  2459. if (!plane || !atomic_state) {
  2460. SDE_ERROR("invalid arg(s), plane %d atomic_state %d\n",
  2461. !plane, !atomic_state);
  2462. return -EINVAL;
  2463. }
  2464. state = drm_atomic_get_new_plane_state(atomic_state, plane);
  2465. return _sde_plane_atomic_check(plane, state);
  2466. }
  2467. #else
  2468. static int sde_plane_atomic_check(struct drm_plane *plane,
  2469. struct drm_plane_state *state)
  2470. {
  2471. if (!plane || !state) {
  2472. SDE_ERROR("invalid arg(s), plane %d state %d\n",
  2473. !plane, !state);
  2474. return -EINVAL;
  2475. }
  2476. return _sde_plane_atomic_check(plane, state);
  2477. }
  2478. #endif
  2479. void sde_plane_flush(struct drm_plane *plane)
  2480. {
  2481. struct sde_plane *psde;
  2482. struct sde_plane_state *pstate;
  2483. if (!plane || !plane->state) {
  2484. SDE_ERROR("invalid plane\n");
  2485. return;
  2486. }
  2487. psde = to_sde_plane(plane);
  2488. pstate = to_sde_plane_state(plane->state);
  2489. /*
  2490. * These updates have to be done immediately before the plane flush
  2491. * timing, and may not be moved to the atomic_update/mode_set functions.
  2492. */
  2493. if (psde->is_error)
  2494. /* force white frame with 100% alpha pipe output on error */
  2495. _sde_plane_color_fill(psde, 0xFFFFFF, 0xFF);
  2496. else if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG)
  2497. /* force 100% alpha */
  2498. _sde_plane_color_fill(psde, psde->color_fill, 0xFF);
  2499. else if (psde->pipe_hw && pstate->csc_ptr && psde->pipe_hw->ops.setup_csc)
  2500. psde->pipe_hw->ops.setup_csc(psde->pipe_hw, pstate->csc_ptr);
  2501. /* flag h/w flush complete */
  2502. if (plane->state)
  2503. pstate->pending = false;
  2504. }
  2505. /**
  2506. * sde_plane_set_error: enable/disable error condition
  2507. * @plane: pointer to drm_plane structure
  2508. */
  2509. void sde_plane_set_error(struct drm_plane *plane, bool error)
  2510. {
  2511. struct sde_plane *psde;
  2512. if (!plane)
  2513. return;
  2514. psde = to_sde_plane(plane);
  2515. psde->is_error = error;
  2516. }
  2517. static void _sde_plane_sspp_setup_sys_cache(struct sde_plane *psde,
  2518. struct sde_plane_state *pstate)
  2519. {
  2520. struct drm_plane_state *state = psde->base.state;
  2521. struct sde_sc_cfg *sc_cfg = psde->catalog->sc_cfg;
  2522. struct sde_hw_pipe_sc_cfg *cfg = &pstate->sc_cfg;
  2523. bool prev_rd_en = cfg->rd_en;
  2524. u32 cache_flag, cache_rd_type, cache_wr_type;
  2525. enum sde_sys_cache_state cache_state;
  2526. if (!state->fb) {
  2527. SDE_ERROR("invalid fb on plane %d\n", DRMID(&psde->base));
  2528. return;
  2529. }
  2530. cache_state = pstate->static_cache_state;
  2531. msm_framebuffer_get_cache_hint(state->fb, &cache_flag, &cache_rd_type, &cache_wr_type);
  2532. cfg->rd_en = false;
  2533. cfg->rd_scid = 0x0;
  2534. cfg->flags = SYS_CACHE_EN_FLAG | SYS_CACHE_SCID;
  2535. /*
  2536. * if condition handles static display legacy path, where internal state machine is
  2537. * transitioning the "cache_state" variable to program the LLCC cache through
  2538. * SSPP hardware using SDE_SYS_CACHE_DISP SCID.
  2539. * else condition handles static display and IWE path, were the frame is programmed to
  2540. * LLCC cache through WB/CWB path and read back by SSPP hardware. The FB cache hints are
  2541. * used to pass information on which SCID to use during read path and LLCC cache to
  2542. * keep active.
  2543. */
  2544. if (test_bit(SDE_SYS_CACHE_DISP, psde->catalog->sde_sys_cache_type_map)
  2545. && ((cache_state == CACHE_STATE_FRAME_WRITE)
  2546. || (cache_state == CACHE_STATE_FRAME_READ))) {
  2547. cfg->type = pstate->static_cache_type;
  2548. cfg->rd_en = true;
  2549. cfg->rd_scid = sc_cfg[cfg->type].llcc_scid;
  2550. if (test_bit(SDE_FEATURE_SYS_CACHE_NSE, psde->catalog->features)) {
  2551. cfg->rd_noallocate = false;
  2552. pstate->static_cache_state = CACHE_STATE_NORMAL;
  2553. } else {
  2554. cfg->rd_noallocate = (cache_state == CACHE_STATE_FRAME_READ);
  2555. }
  2556. cfg->flags |= SYS_CACHE_NO_ALLOC;
  2557. } else if (test_bit(cache_rd_type, psde->catalog->sde_sys_cache_type_map) && cache_flag) {
  2558. cfg->rd_en = true;
  2559. cfg->type = cache_rd_type;
  2560. cfg->rd_scid = sc_cfg[cache_rd_type].llcc_scid;
  2561. cfg->rd_noallocate = false;
  2562. cfg->flags |= SYS_CACHE_NO_ALLOC;
  2563. cache_flag = MSM_FB_CACHE_READ_EN;
  2564. msm_framebuffer_set_cache_hint(state->fb, cache_flag, cache_rd_type, cache_wr_type);
  2565. }
  2566. if (!cfg->rd_en && !prev_rd_en)
  2567. return;
  2568. SDE_EVT32(DRMID(&psde->base), cfg->type, cfg->rd_scid, cfg->rd_en, cfg->rd_noallocate,
  2569. cfg->flags, cache_state, cache_flag, cache_rd_type, cache_wr_type,
  2570. state->fb->base.id);
  2571. psde->pipe_hw->ops.setup_sys_cache(psde->pipe_hw, cfg);
  2572. }
  2573. void sde_plane_static_img_control(struct drm_plane *plane,
  2574. enum sde_sys_cache_state state, enum sde_sys_cache_type type)
  2575. {
  2576. struct sde_plane *psde;
  2577. struct sde_plane_state *pstate;
  2578. if (!plane || !plane->state) {
  2579. SDE_ERROR("invalid plane\n");
  2580. return;
  2581. }
  2582. psde = to_sde_plane(plane);
  2583. pstate = to_sde_plane_state(plane->state);
  2584. pstate->static_cache_state = state;
  2585. pstate->static_cache_type = type;
  2586. if (state == CACHE_STATE_FRAME_WRITE || state == CACHE_STATE_FRAME_READ)
  2587. _sde_plane_sspp_setup_sys_cache(psde, pstate);
  2588. }
  2589. static void _sde_plane_map_prop_to_dirty_bits(void)
  2590. {
  2591. plane_prop_array[PLANE_PROP_SCALER_V1] =
  2592. plane_prop_array[PLANE_PROP_SCALER_V2] =
  2593. plane_prop_array[PLANE_PROP_SCALER_LUT_ED] =
  2594. plane_prop_array[PLANE_PROP_SCALER_LUT_CIR] =
  2595. plane_prop_array[PLANE_PROP_SCALER_LUT_SEP] =
  2596. plane_prop_array[PLANE_PROP_H_DECIMATE] =
  2597. plane_prop_array[PLANE_PROP_V_DECIMATE] =
  2598. plane_prop_array[PLANE_PROP_SRC_CONFIG] =
  2599. plane_prop_array[PLANE_PROP_ZPOS] =
  2600. plane_prop_array[PLANE_PROP_EXCL_RECT_V1] =
  2601. plane_prop_array[PLANE_PROP_UBWC_STATS_ROI] =
  2602. SDE_PLANE_DIRTY_RECTS;
  2603. plane_prop_array[PLANE_PROP_CSC_V1] =
  2604. plane_prop_array[PLANE_PROP_CSC_DMA_V1] =
  2605. plane_prop_array[PLANE_PROP_INVERSE_PMA] =
  2606. SDE_PLANE_DIRTY_FORMAT;
  2607. plane_prop_array[PLANE_PROP_MULTIRECT_MODE] =
  2608. plane_prop_array[PLANE_PROP_COLOR_FILL] =
  2609. SDE_PLANE_DIRTY_ALL;
  2610. /* no special action required */
  2611. plane_prop_array[PLANE_PROP_INFO] =
  2612. plane_prop_array[PLANE_PROP_ALPHA] =
  2613. plane_prop_array[PLANE_PROP_INPUT_FENCE] =
  2614. plane_prop_array[PLANE_PROP_BLEND_OP] = 0;
  2615. plane_prop_array[PLANE_PROP_FB_TRANSLATION_MODE] =
  2616. SDE_PLANE_DIRTY_FB_TRANSLATION_MODE;
  2617. plane_prop_array[PLANE_PROP_PREFILL_SIZE] =
  2618. plane_prop_array[PLANE_PROP_PREFILL_TIME] =
  2619. SDE_PLANE_DIRTY_PERF;
  2620. plane_prop_array[PLANE_PROP_VIG_GAMUT] = SDE_PLANE_DIRTY_VIG_GAMUT;
  2621. plane_prop_array[PLANE_PROP_VIG_IGC] = SDE_PLANE_DIRTY_VIG_IGC;
  2622. plane_prop_array[PLANE_PROP_DMA_IGC] = SDE_PLANE_DIRTY_DMA_IGC;
  2623. plane_prop_array[PLANE_PROP_DMA_GC] = SDE_PLANE_DIRTY_DMA_GC;
  2624. plane_prop_array[PLANE_PROP_SKIN_COLOR] =
  2625. plane_prop_array[PLANE_PROP_SKY_COLOR] =
  2626. plane_prop_array[PLANE_PROP_FOLIAGE_COLOR] =
  2627. plane_prop_array[PLANE_PROP_HUE_ADJUST] =
  2628. plane_prop_array[PLANE_PROP_SATURATION_ADJUST] =
  2629. plane_prop_array[PLANE_PROP_VALUE_ADJUST] =
  2630. plane_prop_array[PLANE_PROP_CONTRAST_ADJUST] =
  2631. SDE_PLANE_DIRTY_ALL;
  2632. plane_prop_array[PLANE_PROP_FP16_IGC] = SDE_PLANE_DIRTY_FP16_IGC;
  2633. plane_prop_array[PLANE_PROP_FP16_GC] = SDE_PLANE_DIRTY_FP16_GC;
  2634. plane_prop_array[PLANE_PROP_FP16_CSC] = SDE_PLANE_DIRTY_FP16_CSC;
  2635. plane_prop_array[PLANE_PROP_FP16_UNMULT] = SDE_PLANE_DIRTY_FP16_UNMULT;
  2636. plane_prop_array[PLANE_PROP_UCSC_UNMULT] = SDE_PLANE_DIRTY_UCSC_UNMULT;
  2637. plane_prop_array[PLANE_PROP_UCSC_IGC] = SDE_PLANE_DIRTY_UCSC_IGC;
  2638. plane_prop_array[PLANE_PROP_UCSC_CSC] = SDE_PLANE_DIRTY_UCSC_CSC;
  2639. plane_prop_array[PLANE_PROP_UCSC_GC] = SDE_PLANE_DIRTY_UCSC_GC;
  2640. plane_prop_array[PLANE_PROP_UCSC_ALPHA_DITHER] = SDE_PLANE_DIRTY_UCSC_ALPHA_DITHER;
  2641. }
  2642. static inline bool _sde_plane_allow_uidle(struct sde_plane *psde,
  2643. struct sde_rect *src, struct sde_rect *dst)
  2644. {
  2645. u32 max_downscale = psde->catalog->uidle_cfg.max_dwnscale;
  2646. u32 downscale = (src->h * 1000)/dst->h;
  2647. return (downscale > max_downscale) ? false : true;
  2648. }
  2649. static void _sde_plane_setup_uidle(struct drm_crtc *crtc,
  2650. struct sde_plane *psde, struct sde_plane_state *pstate,
  2651. struct sde_rect *src, struct sde_rect *dst)
  2652. {
  2653. struct sde_hw_pipe_uidle_cfg cfg;
  2654. u32 line_time = sde_crtc_get_line_time(crtc);
  2655. u32 fal1_target_idle_time_ns =
  2656. psde->catalog->uidle_cfg.fal1_target_idle_time * 1000; /* nS */
  2657. u32 fal10_target_idle_time_ns =
  2658. psde->catalog->uidle_cfg.fal10_target_idle_time * 1000; /* nS */
  2659. u32 fal10_threshold =
  2660. psde->catalog->uidle_cfg.fal10_threshold; /* uS */
  2661. if (line_time && fal10_threshold && fal10_target_idle_time_ns &&
  2662. fal1_target_idle_time_ns) {
  2663. cfg.enable = _sde_plane_allow_uidle(psde, src, dst);
  2664. cfg.fal10_threshold = fal10_threshold;
  2665. cfg.fal10_exit_threshold = fal10_threshold + 2;
  2666. cfg.fal1_threshold = min(1 +
  2667. (fal1_target_idle_time_ns*1000/line_time*2)/1000,
  2668. psde->catalog->uidle_cfg.fal1_max_threshold);
  2669. cfg.fal_allowed_threshold = fal10_threshold +
  2670. (fal10_target_idle_time_ns*1000/line_time*2)/1000;
  2671. cfg.fill_level_scale = 0;
  2672. /*
  2673. * if uidle fill scale is supported, determing the scale value
  2674. * and adjust fal10 thresholds to their scaled values.
  2675. * fal1 thresholds and fal_allowed are not scaled.
  2676. */
  2677. if (psde->pipe_hw->ops.setup_uidle_fill_scale) {
  2678. u32 fl_require0 = psde->catalog->qos_target_time_ns / line_time * 2;
  2679. u32 fl_require = max(fal10_threshold * 1000, fl_require0);
  2680. u32 fl_scale = fl_require / fal10_threshold;
  2681. u32 fal10_threshold_noscale;
  2682. cfg.fill_level_scale = (fl_scale <= 1) ? 0 : (32 / fl_scale);
  2683. if (cfg.fill_level_scale) {
  2684. fal10_threshold_noscale = fal10_threshold *
  2685. 32/cfg.fill_level_scale;
  2686. cfg.fal_allowed_threshold = fal10_threshold_noscale +
  2687. (fal10_target_idle_time_ns * 1000 / line_time * 2) / 1000;
  2688. }
  2689. }
  2690. } else {
  2691. SDE_ERROR("invalid settings, will disable UIDLE %d %d %d %d\n",
  2692. line_time, fal10_threshold, fal10_target_idle_time_ns,
  2693. fal1_target_idle_time_ns);
  2694. memset(&cfg, 0, sizeof(struct sde_hw_pipe_uidle_cfg));
  2695. }
  2696. SDE_DEBUG_PLANE(psde,
  2697. "tholds: fal10=%d fal10_exit=%d fal1=%d fal_allowed=%d fill_scale=%d\n",
  2698. cfg.fal10_threshold, cfg.fal10_exit_threshold,
  2699. cfg.fal1_threshold, cfg.fal_allowed_threshold,
  2700. cfg.fill_level_scale);
  2701. SDE_DEBUG_PLANE(psde,
  2702. "times: line:%d fal1_idle:%d fal10_idle:%d dwnscale:%d\n",
  2703. line_time, fal1_target_idle_time_ns,
  2704. fal10_target_idle_time_ns,
  2705. psde->catalog->uidle_cfg.max_dwnscale);
  2706. SDE_EVT32_VERBOSE(cfg.enable,
  2707. cfg.fal10_threshold, cfg.fal10_exit_threshold,
  2708. cfg.fal1_threshold, cfg.fal_allowed_threshold,
  2709. cfg.fill_level_scale, psde->catalog->uidle_cfg.max_dwnscale);
  2710. if (psde->pipe_hw->ops.setup_uidle_fill_scale)
  2711. psde->pipe_hw->ops.setup_uidle_fill_scale(psde->pipe_hw, &cfg);
  2712. psde->pipe_hw->ops.setup_uidle(
  2713. psde->pipe_hw, &cfg,
  2714. pstate->multirect_index);
  2715. }
  2716. static void _sde_plane_update_secure_session(struct sde_plane *psde,
  2717. struct sde_plane_state *pstate)
  2718. {
  2719. bool enable = false;
  2720. int mode = sde_plane_get_property(pstate,
  2721. PLANE_PROP_FB_TRANSLATION_MODE);
  2722. if ((mode == SDE_DRM_FB_SEC) ||
  2723. (mode == SDE_DRM_FB_SEC_DIR_TRANS))
  2724. enable = true;
  2725. /* update secure session flag */
  2726. psde->pipe_hw->ops.setup_secure_address(psde->pipe_hw,
  2727. pstate->multirect_index,
  2728. enable);
  2729. }
  2730. static void _sde_plane_update_roi_config(struct drm_plane *plane,
  2731. struct drm_crtc *crtc, struct drm_framebuffer *fb)
  2732. {
  2733. const struct sde_format *fmt;
  2734. const struct msm_format *msm_fmt;
  2735. struct sde_plane *psde;
  2736. struct drm_plane_state *state;
  2737. struct sde_plane_state *pstate;
  2738. struct sde_rect src, dst;
  2739. const struct sde_rect *crtc_roi;
  2740. bool q16_data = true;
  2741. int idx;
  2742. psde = to_sde_plane(plane);
  2743. state = plane->state;
  2744. pstate = to_sde_plane_state(state);
  2745. msm_fmt = msm_framebuffer_format(fb);
  2746. if (!msm_fmt) {
  2747. SDE_ERROR("crtc%d plane%d: null format\n",
  2748. DRMID(crtc), DRMID(plane));
  2749. return;
  2750. }
  2751. fmt = to_sde_format(msm_fmt);
  2752. POPULATE_RECT(&src, state->src_x, state->src_y,
  2753. state->src_w, state->src_h, q16_data);
  2754. POPULATE_RECT(&dst, state->crtc_x, state->crtc_y,
  2755. state->crtc_w, state->crtc_h, !q16_data);
  2756. SDE_DEBUG_PLANE(psde,
  2757. "FB[%u] %u,%u,%ux%u->crtc%u %d,%d,%ux%u, %4.4s ubwc %d\n",
  2758. fb->base.id, src.x, src.y, src.w, src.h,
  2759. crtc->base.id, dst.x, dst.y, dst.w, dst.h,
  2760. (char *)&fmt->base.pixel_format,
  2761. SDE_FORMAT_IS_UBWC(fmt));
  2762. if (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) &
  2763. BIT(SDE_DRM_DEINTERLACE)) {
  2764. SDE_DEBUG_PLANE(psde, "deinterlace\n");
  2765. for (idx = 0; idx < SDE_MAX_PLANES; ++idx)
  2766. psde->pipe_cfg.layout.plane_pitch[idx] <<= 1;
  2767. src.h /= 2;
  2768. src.y = DIV_ROUND_UP(src.y, 2);
  2769. src.y &= ~0x1;
  2770. }
  2771. /*
  2772. * adjust layer mixer position of the sspp in the presence
  2773. * of a partial update to the active lm origin
  2774. */
  2775. sde_crtc_get_crtc_roi(crtc->state, &crtc_roi);
  2776. dst.x -= crtc_roi->x;
  2777. dst.y -= crtc_roi->y;
  2778. /* check for UIDLE */
  2779. if (psde->pipe_hw->ops.setup_uidle)
  2780. _sde_plane_setup_uidle(crtc, psde, pstate, &src, &dst);
  2781. psde->pipe_cfg.src_rect = src;
  2782. psde->pipe_cfg.dst_rect = dst;
  2783. _sde_plane_setup_scaler(psde, pstate, fmt, false);
  2784. _sde_plane_setup_panel_stacking(psde, pstate);
  2785. /* check for color fill */
  2786. psde->color_fill = (uint32_t)sde_plane_get_property(pstate,
  2787. PLANE_PROP_COLOR_FILL);
  2788. if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG) {
  2789. /* skip remaining processing on color fill */
  2790. pstate->dirty = 0x0;
  2791. } else if (psde->pipe_hw->ops.setup_rects) {
  2792. psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
  2793. &psde->pipe_cfg,
  2794. pstate->multirect_index);
  2795. }
  2796. if (psde->pipe_hw->ops.setup_pe &&
  2797. (pstate->multirect_index != SDE_SSPP_RECT_1))
  2798. psde->pipe_hw->ops.setup_pe(psde->pipe_hw,
  2799. &psde->pixel_ext);
  2800. /**
  2801. * when programmed in multirect mode, scalar block will be
  2802. * bypassed. Still we need to update alpha and bitwidth
  2803. * ONLY for RECT0
  2804. */
  2805. if (psde->pipe_hw->ops.setup_scaler &&
  2806. pstate->multirect_index != SDE_SSPP_RECT_1) {
  2807. psde->pipe_hw->ctl = _sde_plane_get_hw_ctl(plane);
  2808. psde->pipe_hw->ops.setup_scaler(psde->pipe_hw,
  2809. &psde->pipe_cfg, &psde->pixel_ext,
  2810. &psde->scaler3_cfg);
  2811. }
  2812. /* update excl rect */
  2813. if (psde->pipe_hw->ops.setup_excl_rect)
  2814. psde->pipe_hw->ops.setup_excl_rect(psde->pipe_hw,
  2815. &pstate->excl_rect,
  2816. pstate->multirect_index);
  2817. /* enable multirect config of corresponding rect */
  2818. if (psde->pipe_hw->ops.update_multirect)
  2819. psde->pipe_hw->ops.update_multirect(
  2820. psde->pipe_hw,
  2821. true,
  2822. pstate->multirect_index,
  2823. pstate->multirect_mode);
  2824. /* update line insertion */
  2825. if (pstate->lineinsertion_feature && psde->pipe_hw->ops.setup_line_insertion)
  2826. psde->pipe_hw->ops.setup_line_insertion(psde->pipe_hw,
  2827. pstate->multirect_index,
  2828. &pstate->line_insertion_cfg);
  2829. }
  2830. static void _sde_plane_update_format_and_rects(struct sde_plane *psde,
  2831. struct sde_plane_state *pstate, const struct sde_format *fmt)
  2832. {
  2833. uint32_t src_flags = 0;
  2834. SDE_DEBUG_PLANE(psde, "rotation 0x%X\n", pstate->rotation);
  2835. if (pstate->rotation & DRM_MODE_REFLECT_X)
  2836. src_flags |= SDE_SSPP_FLIP_LR;
  2837. if (pstate->rotation & DRM_MODE_REFLECT_Y)
  2838. src_flags |= SDE_SSPP_FLIP_UD;
  2839. if (pstate->rotation & DRM_MODE_ROTATE_90)
  2840. src_flags |= SDE_SSPP_ROT_90;
  2841. /* update format */
  2842. psde->pipe_hw->ops.setup_format(psde->pipe_hw, fmt,
  2843. pstate->const_alpha_en, src_flags,
  2844. pstate->multirect_index);
  2845. if (psde->pipe_hw->ops.setup_cdp) {
  2846. struct sde_hw_pipe_cdp_cfg *cdp_cfg = &pstate->cdp_cfg;
  2847. memset(cdp_cfg, 0, sizeof(struct sde_hw_pipe_cdp_cfg));
  2848. cdp_cfg->enable = psde->catalog->perf.cdp_cfg
  2849. [SDE_PERF_CDP_USAGE_RT].rd_enable;
  2850. cdp_cfg->ubwc_meta_enable =
  2851. SDE_FORMAT_IS_UBWC(fmt);
  2852. cdp_cfg->tile_amortize_enable =
  2853. SDE_FORMAT_IS_UBWC(fmt) ||
  2854. SDE_FORMAT_IS_TILE(fmt);
  2855. cdp_cfg->preload_ahead = SDE_WB_CDP_PRELOAD_AHEAD_64;
  2856. psde->pipe_hw->ops.setup_cdp(psde->pipe_hw, cdp_cfg,
  2857. pstate->multirect_index);
  2858. }
  2859. _sde_plane_sspp_setup_sys_cache(psde, pstate);
  2860. /* update csc */
  2861. if (SDE_FORMAT_IS_YUV(fmt))
  2862. _sde_plane_setup_csc(psde, pstate);
  2863. else
  2864. pstate->csc_ptr = 0;
  2865. if (psde->pipe_hw->ops.setup_inverse_pma) {
  2866. uint32_t pma_mode = 0;
  2867. if (fmt->alpha_enable)
  2868. pma_mode = (uint32_t) sde_plane_get_property(
  2869. pstate, PLANE_PROP_INVERSE_PMA);
  2870. psde->pipe_hw->ops.setup_inverse_pma(psde->pipe_hw,
  2871. pstate->multirect_index, pma_mode);
  2872. }
  2873. if (psde->pipe_hw->ops.setup_dgm_csc)
  2874. psde->pipe_hw->ops.setup_dgm_csc(psde->pipe_hw,
  2875. pstate->multirect_index, pstate->csc_usr_ptr);
  2876. if (psde->pipe_hw->ops.set_ubwc_stats_roi) {
  2877. if (SDE_FORMAT_IS_UBWC(fmt) && !SDE_FORMAT_IS_YUV(fmt))
  2878. psde->pipe_hw->ops.set_ubwc_stats_roi(psde->pipe_hw,
  2879. pstate->multirect_index, &pstate->ubwc_stats_roi);
  2880. else
  2881. psde->pipe_hw->ops.set_ubwc_stats_roi(psde->pipe_hw,
  2882. pstate->multirect_index, NULL);
  2883. }
  2884. }
  2885. static void _sde_plane_update_sharpening(struct sde_plane *psde)
  2886. {
  2887. psde->sharp_cfg.strength = SHARP_STRENGTH_DEFAULT;
  2888. psde->sharp_cfg.edge_thr = SHARP_EDGE_THR_DEFAULT;
  2889. psde->sharp_cfg.smooth_thr = SHARP_SMOOTH_THR_DEFAULT;
  2890. psde->sharp_cfg.noise_thr = SHARP_NOISE_THR_DEFAULT;
  2891. psde->pipe_hw->ops.setup_sharpening(psde->pipe_hw,
  2892. &psde->sharp_cfg);
  2893. }
  2894. static void _sde_plane_update_properties(struct drm_plane *plane,
  2895. struct drm_crtc *crtc, struct drm_framebuffer *fb)
  2896. {
  2897. uint32_t nplanes;
  2898. const struct msm_format *msm_fmt;
  2899. const struct sde_format *fmt;
  2900. struct sde_plane *psde;
  2901. struct drm_plane_state *state;
  2902. struct sde_plane_state *pstate;
  2903. psde = to_sde_plane(plane);
  2904. state = plane->state;
  2905. pstate = to_sde_plane_state(state);
  2906. if (!pstate) {
  2907. SDE_ERROR("invalid plane state for plane%d\n", DRMID(plane));
  2908. return;
  2909. }
  2910. msm_fmt = msm_framebuffer_format(fb);
  2911. if (!msm_fmt) {
  2912. SDE_ERROR("crtc%d plane%d: null format\n",
  2913. DRMID(crtc), DRMID(plane));
  2914. return;
  2915. }
  2916. fmt = to_sde_format(msm_fmt);
  2917. nplanes = fmt->num_planes;
  2918. /* update secure session flag */
  2919. if (pstate->dirty & SDE_PLANE_DIRTY_FB_TRANSLATION_MODE)
  2920. _sde_plane_update_secure_session(psde, pstate);
  2921. /* update roi config */
  2922. if (pstate->dirty & SDE_PLANE_DIRTY_RECTS)
  2923. _sde_plane_update_roi_config(plane, crtc, fb);
  2924. if ((pstate->dirty & SDE_PLANE_DIRTY_FORMAT ||
  2925. pstate->dirty & SDE_PLANE_DIRTY_RECTS) &&
  2926. psde->pipe_hw->ops.setup_format)
  2927. _sde_plane_update_format_and_rects(psde, pstate, fmt);
  2928. sde_color_process_plane_setup(plane);
  2929. /* update sharpening */
  2930. if ((pstate->dirty & SDE_PLANE_DIRTY_SHARPEN) &&
  2931. psde->pipe_hw->ops.setup_sharpening)
  2932. _sde_plane_update_sharpening(psde);
  2933. if (pstate->dirty & (SDE_PLANE_DIRTY_QOS | SDE_PLANE_DIRTY_RECTS |
  2934. SDE_PLANE_DIRTY_FORMAT))
  2935. _sde_plane_set_qos_lut(plane, crtc, fb);
  2936. _sde_plane_set_qos_ctrl(plane, true, SDE_PLANE_QOS_PANIC_CTRL);
  2937. _sde_plane_set_ot_limit(plane, crtc);
  2938. if (pstate->dirty & SDE_PLANE_DIRTY_PERF)
  2939. _sde_plane_set_ts_prefill(plane, pstate);
  2940. if (pstate->dirty & SDE_PLANE_DIRTY_QOS)
  2941. _sde_plane_set_qos_remap(plane);
  2942. /* clear dirty */
  2943. pstate->dirty = 0x0;
  2944. }
  2945. static void _sde_plane_check_lut_dirty(struct sde_plane *psde,
  2946. struct sde_plane_state *pstate)
  2947. {
  2948. /**
  2949. * Valid configuration if scaler is not enabled or
  2950. * lut flag is set
  2951. */
  2952. if (pstate->scaler3_cfg.lut_flag || !pstate->scaler3_cfg.enable)
  2953. return;
  2954. pstate->scaler3_cfg.lut_flag = psde->cached_lut_flag;
  2955. SDE_EVT32(DRMID(&psde->base), pstate->scaler3_cfg.lut_flag, SDE_EVTLOG_ERROR);
  2956. }
  2957. static int sde_plane_sspp_atomic_update(struct drm_plane *plane,
  2958. struct drm_plane_state *old_state)
  2959. {
  2960. struct sde_plane *psde;
  2961. struct drm_plane_state *state;
  2962. struct sde_plane_state *pstate;
  2963. struct sde_plane_state *old_pstate;
  2964. struct drm_crtc *crtc;
  2965. struct drm_framebuffer *fb;
  2966. int idx;
  2967. int dirty_prop_flag;
  2968. bool is_rt;
  2969. if (!plane) {
  2970. SDE_ERROR("invalid plane\n");
  2971. return -EINVAL;
  2972. } else if (!plane->state) {
  2973. SDE_ERROR("invalid plane state\n");
  2974. return -EINVAL;
  2975. } else if (!old_state) {
  2976. SDE_ERROR("invalid old state\n");
  2977. return -EINVAL;
  2978. }
  2979. psde = to_sde_plane(plane);
  2980. state = plane->state;
  2981. pstate = to_sde_plane_state(state);
  2982. old_pstate = to_sde_plane_state(old_state);
  2983. crtc = state->crtc;
  2984. fb = state->fb;
  2985. if (!crtc || !fb) {
  2986. SDE_ERROR_PLANE(psde, "invalid crtc %d or fb %d\n",
  2987. !crtc, !fb);
  2988. return -EINVAL;
  2989. }
  2990. SDE_DEBUG(
  2991. "plane%d sspp:%dx%d/%4.4s/%llx/%dx%d+%d+%d/%x crtc:%dx%d+%d+%d\n",
  2992. plane->base.id,
  2993. state->fb->width, state->fb->height,
  2994. (char *) &state->fb->format->format,
  2995. state->fb->modifier,
  2996. state->src_w >> 16, state->src_h >> 16,
  2997. state->src_x >> 16, state->src_y >> 16,
  2998. pstate->rotation,
  2999. state->crtc_w, state->crtc_h,
  3000. state->crtc_x, state->crtc_y);
  3001. /* Caching the valid lut flag in sde plane */
  3002. if (pstate->scaler3_cfg.enable && pstate->scaler3_cfg.lut_flag)
  3003. psde->cached_lut_flag = pstate->scaler3_cfg.lut_flag;
  3004. /* force reprogramming of all the parameters, if the flag is set */
  3005. if (psde->revalidate) {
  3006. SDE_DEBUG("plane:%d - reconfigure all the parameters\n",
  3007. plane->base.id);
  3008. _sde_plane_check_lut_dirty(psde, pstate);
  3009. pstate->dirty = SDE_PLANE_DIRTY_ALL | SDE_PLANE_DIRTY_CP;
  3010. psde->revalidate = false;
  3011. }
  3012. /* determine what needs to be refreshed */
  3013. mutex_lock(&psde->property_info.property_lock);
  3014. while ((idx = msm_property_pop_dirty(&psde->property_info,
  3015. &pstate->property_state)) >= 0) {
  3016. dirty_prop_flag = plane_prop_array[idx];
  3017. pstate->dirty |= dirty_prop_flag;
  3018. }
  3019. mutex_unlock(&psde->property_info.property_lock);
  3020. /**
  3021. * since plane_atomic_check is invoked before crtc_atomic_check
  3022. * in the commit sequence, all the parameters for updating the
  3023. * plane dirty flag will not be available during
  3024. * plane_atomic_check as some features params are updated
  3025. * in crtc_atomic_check (eg.:sDMA). So check for mode_change
  3026. * before sspp update.
  3027. */
  3028. _sde_plane_sspp_atomic_check_mode_changed(psde, state,
  3029. old_state);
  3030. /* re-program the output rects always if partial update roi changed */
  3031. if (sde_crtc_is_crtc_roi_dirty(crtc->state))
  3032. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  3033. if (pstate->dirty & SDE_PLANE_DIRTY_RECTS)
  3034. memset(&(psde->pipe_cfg), 0, sizeof(struct sde_hw_pipe_cfg));
  3035. _sde_plane_set_scanout(plane, pstate, &psde->pipe_cfg, fb);
  3036. is_rt = sde_crtc_is_rt_client(crtc, crtc->state);
  3037. if (is_rt != psde->is_rt_pipe || crtc->state->mode_changed) {
  3038. psde->is_rt_pipe = is_rt;
  3039. psde->wb_usage_type = psde->is_rt_pipe ? 0 : sde_crtc_get_wb_usage_type(crtc);
  3040. pstate->dirty |= SDE_PLANE_DIRTY_QOS;
  3041. }
  3042. /* early out if nothing dirty */
  3043. if (!pstate->dirty)
  3044. return 0;
  3045. pstate->pending = true;
  3046. _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);
  3047. _sde_plane_update_properties(plane, crtc, fb);
  3048. return 0;
  3049. }
  3050. static void _sde_plane_atomic_disable(struct drm_plane *plane,
  3051. struct drm_plane_state *old_state)
  3052. {
  3053. struct sde_plane *psde;
  3054. struct drm_plane_state *state;
  3055. struct sde_plane_state *pstate;
  3056. u32 multirect_index = SDE_SSPP_RECT_0;
  3057. struct sde_cp_crtc_skip_blend_plane skip_blend_plane;
  3058. u32 blend_type;
  3059. if (!plane) {
  3060. SDE_ERROR("invalid plane\n");
  3061. return;
  3062. } else if (!plane->state) {
  3063. SDE_ERROR("invalid plane state\n");
  3064. return;
  3065. } else if (!old_state) {
  3066. SDE_ERROR("invalid old state\n");
  3067. return;
  3068. }
  3069. psde = to_sde_plane(plane);
  3070. state = plane->state;
  3071. pstate = to_sde_plane_state(state);
  3072. blend_type = sde_plane_get_property(pstate,
  3073. PLANE_PROP_BLEND_OP);
  3074. /* some of the color features are dependent on plane with skip blend.
  3075. * if skip blend plane is being disabled, we need to disable color properties.
  3076. */
  3077. if (blend_type == SDE_DRM_BLEND_OP_SKIP && old_state->crtc) {
  3078. skip_blend_plane.valid_plane = false;
  3079. skip_blend_plane.plane = SSPP_NONE;
  3080. sde_cp_set_skip_blend_plane_info(old_state->crtc, &skip_blend_plane);
  3081. sde_crtc_disable_cp_features(old_state->crtc);
  3082. }
  3083. SDE_EVT32(DRMID(plane), is_sde_plane_virtual(plane),
  3084. pstate->multirect_mode);
  3085. pstate->pending = true;
  3086. pstate->static_cache_state = CACHE_STATE_DISABLED;
  3087. if (is_sde_plane_virtual(plane))
  3088. multirect_index = SDE_SSPP_RECT_1;
  3089. /* disable multirect config of corresponding rect */
  3090. if (psde->pipe_hw && psde->pipe_hw->ops.update_multirect)
  3091. psde->pipe_hw->ops.update_multirect(psde->pipe_hw, false,
  3092. multirect_index, SDE_SSPP_MULTIRECT_TIME_MX);
  3093. }
  3094. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
  3095. static void _sde_plane_atomic_update(struct drm_plane *plane,
  3096. struct drm_plane_state *old_state)
  3097. #else
  3098. static void sde_plane_atomic_update(struct drm_plane *plane,
  3099. struct drm_plane_state *old_state)
  3100. #endif
  3101. {
  3102. struct sde_plane *psde;
  3103. struct drm_plane_state *state;
  3104. if (!plane) {
  3105. SDE_ERROR("invalid plane\n");
  3106. return;
  3107. } else if (!plane->state) {
  3108. SDE_ERROR("invalid plane state\n");
  3109. return;
  3110. }
  3111. psde = to_sde_plane(plane);
  3112. psde->is_error = false;
  3113. state = plane->state;
  3114. SDE_DEBUG_PLANE(psde, "\n");
  3115. if (!sde_plane_enabled(state)) {
  3116. _sde_plane_atomic_disable(plane, old_state);
  3117. } else {
  3118. int ret;
  3119. ret = sde_plane_sspp_atomic_update(plane, old_state);
  3120. /* atomic_check should have ensured that this doesn't fail */
  3121. WARN_ON(ret < 0);
  3122. }
  3123. }
  3124. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
  3125. static void sde_plane_atomic_update(struct drm_plane *plane,
  3126. struct drm_atomic_state *atomic_state)
  3127. {
  3128. struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(atomic_state, plane);
  3129. _sde_plane_atomic_update(plane, old_state);
  3130. }
  3131. #endif
  3132. void sde_plane_restore(struct drm_plane *plane)
  3133. {
  3134. struct sde_plane *psde;
  3135. if (!plane || !plane->state) {
  3136. SDE_ERROR("invalid plane\n");
  3137. return;
  3138. }
  3139. psde = to_sde_plane(plane);
  3140. /*
  3141. * Revalidate is only true here if idle PC occurred and
  3142. * there is no plane state update in current commit cycle.
  3143. */
  3144. if (!psde->revalidate)
  3145. return;
  3146. SDE_DEBUG_PLANE(psde, "\n");
  3147. /* last plane state is same as current state */
  3148. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0))
  3149. _sde_plane_atomic_update(plane, plane->state);
  3150. #else
  3151. sde_plane_atomic_update(plane, plane->state);
  3152. #endif
  3153. }
  3154. bool sde_plane_is_cache_required(struct drm_plane *plane,
  3155. enum sde_sys_cache_type type)
  3156. {
  3157. struct sde_plane_state *pstate;
  3158. u32 cache_flag, cache_rd_type, cache_wr_type;
  3159. if (!plane || !plane->state) {
  3160. SDE_ERROR("invalid plane\n");
  3161. return false;
  3162. }
  3163. pstate = to_sde_plane_state(plane->state);
  3164. msm_framebuffer_get_cache_hint(plane->state->fb, &cache_flag, &cache_rd_type,
  3165. &cache_wr_type);
  3166. /* check if llcc is required for the plane */
  3167. if (pstate->sc_cfg.rd_en && ((pstate->sc_cfg.type == type)
  3168. || (cache_flag && (cache_rd_type == type))
  3169. || (cache_flag && (cache_wr_type == type)))) {
  3170. SDE_EVT32_VERBOSE(DRMID(plane), type, pstate->sc_cfg.rd_en, pstate->sc_cfg.type,
  3171. cache_flag, cache_rd_type, cache_wr_type,
  3172. plane->state->fb->base.id);
  3173. return true;
  3174. }
  3175. return false;
  3176. }
  3177. static void _sde_plane_install_master_only_properties(struct sde_plane *psde)
  3178. {
  3179. char feature_name[256];
  3180. if (psde->pipe_sblk->maxhdeciexp) {
  3181. msm_property_install_range(&psde->property_info,
  3182. "h_decimate", 0x0, 0,
  3183. psde->pipe_sblk->maxhdeciexp, 0,
  3184. PLANE_PROP_H_DECIMATE);
  3185. }
  3186. if (psde->pipe_sblk->maxvdeciexp) {
  3187. msm_property_install_range(&psde->property_info,
  3188. "v_decimate", 0x0, 0,
  3189. psde->pipe_sblk->maxvdeciexp, 0,
  3190. PLANE_PROP_V_DECIMATE);
  3191. }
  3192. if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) {
  3193. msm_property_install_range(
  3194. &psde->property_info, "scaler_v2",
  3195. 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V2);
  3196. msm_property_install_blob(&psde->property_info,
  3197. "lut_ed", 0, PLANE_PROP_SCALER_LUT_ED);
  3198. msm_property_install_blob(&psde->property_info,
  3199. "lut_cir", 0,
  3200. PLANE_PROP_SCALER_LUT_CIR);
  3201. msm_property_install_blob(&psde->property_info,
  3202. "lut_sep", 0,
  3203. PLANE_PROP_SCALER_LUT_SEP);
  3204. } else if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3LITE)) {
  3205. msm_property_install_range(
  3206. &psde->property_info, "scaler_v2",
  3207. 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V2);
  3208. msm_property_install_blob(&psde->property_info,
  3209. "lut_sep", 0,
  3210. PLANE_PROP_SCALER_LUT_SEP);
  3211. } else if (psde->features & SDE_SSPP_SCALER) {
  3212. msm_property_install_range(
  3213. &psde->property_info, "scaler_v1", 0x0,
  3214. 0, ~0, 0, PLANE_PROP_SCALER_V1);
  3215. }
  3216. if (psde->features & BIT(SDE_SSPP_CSC) ||
  3217. psde->features & BIT(SDE_SSPP_CSC_10BIT))
  3218. msm_property_install_volatile_range(
  3219. &psde->property_info, "csc_v1", 0x0,
  3220. 0, ~0, 0, PLANE_PROP_CSC_V1);
  3221. if (psde->features & BIT(SDE_SSPP_HSIC)) {
  3222. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3223. "SDE_SSPP_HUE_V",
  3224. psde->pipe_sblk->hsic_blk.version >> 16);
  3225. msm_property_install_range(&psde->property_info,
  3226. feature_name, 0, 0, 0xFFFFFFFF, 0,
  3227. PLANE_PROP_HUE_ADJUST);
  3228. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3229. "SDE_SSPP_SATURATION_V",
  3230. psde->pipe_sblk->hsic_blk.version >> 16);
  3231. msm_property_install_range(&psde->property_info,
  3232. feature_name, 0, 0, 0xFFFFFFFF, 0,
  3233. PLANE_PROP_SATURATION_ADJUST);
  3234. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3235. "SDE_SSPP_VALUE_V",
  3236. psde->pipe_sblk->hsic_blk.version >> 16);
  3237. msm_property_install_range(&psde->property_info,
  3238. feature_name, 0, 0, 0xFFFFFFFF, 0,
  3239. PLANE_PROP_VALUE_ADJUST);
  3240. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3241. "SDE_SSPP_CONTRAST_V",
  3242. psde->pipe_sblk->hsic_blk.version >> 16);
  3243. msm_property_install_range(&psde->property_info,
  3244. feature_name, 0, 0, 0xFFFFFFFF, 0,
  3245. PLANE_PROP_CONTRAST_ADJUST);
  3246. }
  3247. }
  3248. static void _sde_plane_install_colorproc_properties(struct sde_plane *psde,
  3249. struct sde_kms_info *info)
  3250. {
  3251. char feature_name[256];
  3252. bool is_master = !psde->is_virtual;
  3253. static const struct drm_prop_enum_list ucsc_gc[] = {
  3254. {UCSC_GC_MODE_DISABLE, "disable"},
  3255. {UCSC_GC_MODE_SRGB, "srgb"},
  3256. {UCSC_GC_MODE_PQ, "pq"},
  3257. {UCSC_GC_MODE_GAMMA2_2, "gamma2_2"},
  3258. {UCSC_GC_MODE_HLG, "hlg"},
  3259. };
  3260. static const struct drm_prop_enum_list ucsc_igc[] = {
  3261. {UCSC_IGC_MODE_DISABLE, "disable"},
  3262. {UCSC_IGC_MODE_SRGB, "srgb"},
  3263. {UCSC_IGC_MODE_REC709, "rec709"},
  3264. {UCSC_IGC_MODE_GAMMA2_2, "gamma2_2"},
  3265. {UCSC_IGC_MODE_HLG, "hlg"},
  3266. {UCSC_IGC_MODE_PQ, "pq"},
  3267. };
  3268. if ((is_master &&
  3269. (psde->features & BIT(SDE_SSPP_INVERSE_PMA))) ||
  3270. (psde->features & BIT(SDE_SSPP_DGM_INVERSE_PMA))) {
  3271. msm_property_install_range(&psde->property_info,
  3272. "inverse_pma", 0x0, 0, 1, 0, PLANE_PROP_INVERSE_PMA);
  3273. sde_kms_info_add_keyint(info, "inverse_pma", 1);
  3274. }
  3275. if (psde->features & BIT(SDE_SSPP_DGM_CSC)) {
  3276. msm_property_install_volatile_range(
  3277. &psde->property_info, "csc_dma_v1", 0x0,
  3278. 0, ~0, 0, PLANE_PROP_CSC_DMA_V1);
  3279. sde_kms_info_add_keyint(info, "csc_dma_v1", 1);
  3280. }
  3281. if (psde->features & BIT(SDE_SSPP_MEMCOLOR)) {
  3282. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3283. "SDE_SSPP_SKIN_COLOR_V",
  3284. psde->pipe_sblk->memcolor_blk.version >> 16);
  3285. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3286. PLANE_PROP_SKIN_COLOR);
  3287. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3288. "SDE_SSPP_SKY_COLOR_V",
  3289. psde->pipe_sblk->memcolor_blk.version >> 16);
  3290. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3291. PLANE_PROP_SKY_COLOR);
  3292. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3293. "SDE_SSPP_FOLIAGE_COLOR_V",
  3294. psde->pipe_sblk->memcolor_blk.version >> 16);
  3295. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3296. PLANE_PROP_FOLIAGE_COLOR);
  3297. }
  3298. if (psde->features & BIT(SDE_SSPP_VIG_GAMUT)) {
  3299. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3300. "SDE_VIG_3D_LUT_GAMUT_V",
  3301. psde->pipe_sblk->gamut_blk.version >> 16);
  3302. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3303. PLANE_PROP_VIG_GAMUT);
  3304. }
  3305. if (psde->features & BIT(SDE_SSPP_VIG_IGC)) {
  3306. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3307. "SDE_VIG_1D_LUT_IGC_V",
  3308. psde->pipe_sblk->igc_blk[0].version >> 16);
  3309. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3310. PLANE_PROP_VIG_IGC);
  3311. }
  3312. if (psde->features & BIT(SDE_SSPP_DMA_IGC)) {
  3313. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3314. "SDE_DGM_1D_LUT_IGC_V",
  3315. psde->pipe_sblk->igc_blk[0].version >> 16);
  3316. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3317. PLANE_PROP_DMA_IGC);
  3318. }
  3319. if (psde->features & BIT(SDE_SSPP_DMA_GC)) {
  3320. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3321. "SDE_DGM_1D_LUT_GC_V",
  3322. psde->pipe_sblk->gc_blk[0].version >> 16);
  3323. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3324. PLANE_PROP_DMA_GC);
  3325. }
  3326. if (psde->features & BIT(SDE_SSPP_FP16_IGC)) {
  3327. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3328. "SDE_SSPP_FP16_IGC_V",
  3329. psde->pipe_sblk->fp16_igc_blk[0].version >> 16);
  3330. msm_property_install_range(&psde->property_info, feature_name,
  3331. 0x0, 0, 1, 0, PLANE_PROP_FP16_IGC);
  3332. }
  3333. if (psde->features & BIT(SDE_SSPP_FP16_GC)) {
  3334. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3335. "SDE_SSPP_FP16_GC_V",
  3336. psde->pipe_sblk->fp16_gc_blk[0].version >> 16);
  3337. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3338. PLANE_PROP_FP16_GC);
  3339. }
  3340. if (psde->features & BIT(SDE_SSPP_FP16_CSC)) {
  3341. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3342. "SDE_SSPP_FP16_CSC_V",
  3343. psde->pipe_sblk->fp16_csc_blk[0].version >> 16);
  3344. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3345. PLANE_PROP_FP16_CSC);
  3346. }
  3347. if (psde->features & BIT(SDE_SSPP_FP16_UNMULT)) {
  3348. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3349. "SDE_SSPP_FP16_UNMULT_V",
  3350. psde->pipe_sblk->fp16_unmult_blk[0].version >> 16);
  3351. msm_property_install_range(&psde->property_info, feature_name,
  3352. 0x0, 0, 1, 0, PLANE_PROP_FP16_UNMULT);
  3353. }
  3354. if (psde->features & BIT(SDE_SSPP_UCSC_IGC)) {
  3355. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3356. "SDE_SSPP_UCSC_IGC_V",
  3357. psde->pipe_sblk->ucsc_igc_blk[0].version >> 16);
  3358. msm_property_install_volatile_enum(&psde->property_info, feature_name,
  3359. 0x0, 0, ucsc_igc, ARRAY_SIZE(ucsc_igc), 0, PLANE_PROP_UCSC_IGC);
  3360. }
  3361. if (psde->features & BIT(SDE_SSPP_UCSC_GC)) {
  3362. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3363. "SDE_SSPP_UCSC_GC_V",
  3364. psde->pipe_sblk->ucsc_gc_blk[0].version >> 16);
  3365. msm_property_install_volatile_enum(&psde->property_info, feature_name,
  3366. 0x0, 0, ucsc_gc, ARRAY_SIZE(ucsc_gc), 0, PLANE_PROP_UCSC_GC);
  3367. }
  3368. if (psde->features & BIT(SDE_SSPP_UCSC_CSC)) {
  3369. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3370. "SDE_SSPP_UCSC_CSC_V",
  3371. psde->pipe_sblk->ucsc_csc_blk[0].version >> 16);
  3372. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3373. PLANE_PROP_UCSC_CSC);
  3374. }
  3375. if (psde->features & BIT(SDE_SSPP_UCSC_UNMULT)) {
  3376. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3377. "SDE_SSPP_UCSC_UNMULT_V",
  3378. psde->pipe_sblk->ucsc_unmult_blk[0].version >> 16);
  3379. msm_property_install_volatile_range(&psde->property_info, feature_name,
  3380. 0x0, 0, 1, 0, PLANE_PROP_UCSC_UNMULT);
  3381. }
  3382. if (psde->features & BIT(SDE_SSPP_UCSC_ALPHA_DITHER)) {
  3383. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3384. "SDE_SSPP_UCSC_ALPHA_DITHER_V",
  3385. psde->pipe_sblk->ucsc_alpha_dither_blk[0].version >> 16);
  3386. msm_property_install_volatile_range(&psde->property_info, feature_name,
  3387. 0x0, 0, 1, 0, PLANE_PROP_UCSC_ALPHA_DITHER);
  3388. }
  3389. }
  3390. static void _sde_plane_setup_capabilities_blob(struct sde_plane *psde,
  3391. u32 master_plane_id, struct sde_kms_info *info,
  3392. struct sde_mdss_cfg *catalog)
  3393. {
  3394. bool is_master = !psde->is_virtual;
  3395. const struct sde_format_extended *format_list;
  3396. u32 index;
  3397. int pipe_id;
  3398. if (is_master) {
  3399. format_list = psde->pipe_sblk->format_list;
  3400. } else {
  3401. format_list = psde->pipe_sblk->virt_format_list;
  3402. sde_kms_info_add_keyint(info, "primary_smart_plane_id",
  3403. master_plane_id);
  3404. }
  3405. if (format_list) {
  3406. sde_kms_info_start(info, "pixel_formats");
  3407. while (format_list->fourcc_format) {
  3408. sde_kms_info_append_format(info,
  3409. format_list->fourcc_format,
  3410. format_list->modifier);
  3411. ++format_list;
  3412. }
  3413. sde_kms_info_stop(info);
  3414. }
  3415. if (psde->pipe_hw && catalog->qseed_hw_rev)
  3416. sde_kms_info_add_keyint(info, "scaler_step_ver", catalog->qseed_hw_rev);
  3417. sde_kms_info_add_keyint(info, "max_linewidth",
  3418. psde->pipe_sblk->maxlinewidth);
  3419. sde_kms_info_add_keyint(info, "max_upscale",
  3420. psde->pipe_sblk->maxupscale);
  3421. sde_kms_info_add_keyint(info, "max_downscale",
  3422. psde->pipe_sblk->maxdwnscale);
  3423. sde_kms_info_add_keyint(info, "max_horizontal_deci",
  3424. psde->pipe_sblk->maxhdeciexp);
  3425. sde_kms_info_add_keyint(info, "max_vertical_deci",
  3426. psde->pipe_sblk->maxvdeciexp);
  3427. sde_kms_info_add_keyint(info, "max_per_pipe_bw",
  3428. psde->pipe_sblk->max_per_pipe_bw * 1000LL);
  3429. sde_kms_info_add_keyint(info, "max_per_pipe_bw_high",
  3430. psde->pipe_sblk->max_per_pipe_bw_high * 1000LL);
  3431. if (SDE_SSPP_VALID_VIG(psde->pipe))
  3432. pipe_id = psde->pipe - SSPP_VIG0;
  3433. else if (SDE_SSPP_VALID_DMA(psde->pipe))
  3434. pipe_id = psde->pipe - SSPP_DMA0;
  3435. else
  3436. pipe_id = -1;
  3437. sde_kms_info_add_keyint(info, "pipe_idx", pipe_id);
  3438. index = (master_plane_id == 0) ? 0 : 1;
  3439. if (test_bit(SDE_FEATURE_DEMURA, catalog->features) &&
  3440. catalog->demura_supported[psde->pipe][index] != ~0x0)
  3441. sde_kms_info_add_keyint(info, "demura_block",
  3442. catalog->demura_supported[psde->pipe][index]);
  3443. if (psde->features & BIT(SDE_SSPP_SEC_UI_ALLOWED))
  3444. sde_kms_info_add_keyint(info, "sec_ui_allowed", 1);
  3445. if (psde->features & BIT(SDE_SSPP_BLOCK_SEC_UI))
  3446. sde_kms_info_add_keyint(info, "block_sec_ui", 1);
  3447. if (psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT)) {
  3448. const struct sde_format_extended *inline_rot_fmt_list;
  3449. sde_kms_info_add_keyint(info, "true_inline_rot_rev",
  3450. catalog->true_inline_rot_rev);
  3451. sde_kms_info_add_keyint(info,
  3452. "true_inline_dwnscale_rt",
  3453. (int) (psde->pipe_sblk->in_rot_maxdwnscale_rt_num /
  3454. psde->pipe_sblk->in_rot_maxdwnscale_rt_denom));
  3455. sde_kms_info_add_keyint(info,
  3456. "true_inline_dwnscale_rt_numerator",
  3457. psde->pipe_sblk->in_rot_maxdwnscale_rt_num);
  3458. sde_kms_info_add_keyint(info,
  3459. "true_inline_dwnscale_rt_denominator",
  3460. psde->pipe_sblk->in_rot_maxdwnscale_rt_denom);
  3461. sde_kms_info_add_keyint(info, "true_inline_dwnscale_nrt",
  3462. psde->pipe_sblk->in_rot_maxdwnscale_nrt);
  3463. sde_kms_info_add_keyint(info, "true_inline_max_height",
  3464. psde->pipe_sblk->in_rot_maxheight);
  3465. inline_rot_fmt_list = psde->pipe_sblk->in_rot_format_list;
  3466. if (inline_rot_fmt_list) {
  3467. sde_kms_info_start(info, "inline_rot_pixel_formats");
  3468. while (inline_rot_fmt_list->fourcc_format) {
  3469. sde_kms_info_append_format(info,
  3470. inline_rot_fmt_list->fourcc_format,
  3471. inline_rot_fmt_list->modifier);
  3472. ++inline_rot_fmt_list;
  3473. }
  3474. sde_kms_info_stop(info);
  3475. }
  3476. }
  3477. }
  3478. /* helper to install properties which are common to planes and crtcs */
  3479. static void _sde_plane_install_properties(struct drm_plane *plane,
  3480. struct sde_mdss_cfg *catalog, u32 master_plane_id)
  3481. {
  3482. static const struct drm_prop_enum_list e_blend_op[] = {
  3483. {SDE_DRM_BLEND_OP_NOT_DEFINED, "not_defined"},
  3484. {SDE_DRM_BLEND_OP_OPAQUE, "opaque"},
  3485. {SDE_DRM_BLEND_OP_PREMULTIPLIED, "premultiplied"},
  3486. {SDE_DRM_BLEND_OP_COVERAGE, "coverage"},
  3487. {SDE_DRM_BLEND_OP_SKIP, "skip_blending"},
  3488. };
  3489. static const struct drm_prop_enum_list e_src_config[] = {
  3490. {SDE_DRM_DEINTERLACE, "deinterlace"}
  3491. };
  3492. static const struct drm_prop_enum_list e_fb_translation_mode[] = {
  3493. {SDE_DRM_FB_NON_SEC, "non_sec"},
  3494. {SDE_DRM_FB_SEC, "sec"},
  3495. {SDE_DRM_FB_NON_SEC_DIR_TRANS, "non_sec_direct_translation"},
  3496. {SDE_DRM_FB_SEC_DIR_TRANS, "sec_direct_translation"},
  3497. };
  3498. static const struct drm_prop_enum_list e_multirect_mode[] = {
  3499. {SDE_SSPP_MULTIRECT_NONE, "none"},
  3500. {SDE_SSPP_MULTIRECT_PARALLEL, "parallel"},
  3501. {SDE_SSPP_MULTIRECT_TIME_MX, "serial"},
  3502. };
  3503. struct sde_kms_info *info;
  3504. struct sde_plane *psde = to_sde_plane(plane);
  3505. bool is_master;
  3506. int zpos_max = 255;
  3507. int zpos_def = 0;
  3508. if (!plane || !psde) {
  3509. SDE_ERROR("invalid plane\n");
  3510. return;
  3511. } else if (!psde->pipe_hw || !psde->pipe_sblk) {
  3512. SDE_ERROR("invalid plane, pipe_hw %d pipe_sblk %d\n",
  3513. !psde->pipe_hw, !psde->pipe_sblk);
  3514. return;
  3515. } else if (!catalog) {
  3516. SDE_ERROR("invalid catalog\n");
  3517. return;
  3518. }
  3519. psde->catalog = catalog;
  3520. is_master = !psde->is_virtual;
  3521. info = vzalloc(sizeof(struct sde_kms_info));
  3522. if (!info) {
  3523. SDE_ERROR("failed to allocate info memory\n");
  3524. return;
  3525. }
  3526. if (sde_is_custom_client()) {
  3527. if (catalog->mixer_count &&
  3528. catalog->mixer[0].sblk->maxblendstages) {
  3529. zpos_max = catalog->mixer[0].sblk->maxblendstages - 1;
  3530. if (test_bit(SDE_FEATURE_BASE_LAYER, catalog->features) &&
  3531. (zpos_max > SDE_STAGE_MAX - 1))
  3532. zpos_max = SDE_STAGE_MAX - 1;
  3533. else if (zpos_max > SDE_STAGE_MAX - SDE_STAGE_0 - 1)
  3534. zpos_max = SDE_STAGE_MAX - SDE_STAGE_0 - 1;
  3535. }
  3536. } else if (plane->type != DRM_PLANE_TYPE_PRIMARY) {
  3537. /* reserve zpos == 0 for primary planes */
  3538. zpos_def = drm_plane_index(plane) + 1;
  3539. }
  3540. msm_property_install_range(&psde->property_info, "zpos",
  3541. 0x0, 0, zpos_max, zpos_def, PLANE_PROP_ZPOS);
  3542. msm_property_install_range(&psde->property_info, "alpha",
  3543. 0x0, 0, 255, 255, PLANE_PROP_ALPHA);
  3544. /* linux default file descriptor range on each process */
  3545. msm_property_install_range(&psde->property_info, "input_fence",
  3546. 0x0, 0, INR_OPEN_MAX, 0, PLANE_PROP_INPUT_FENCE);
  3547. if (is_master)
  3548. _sde_plane_install_master_only_properties(psde);
  3549. else
  3550. msm_property_install_enum(&psde->property_info,
  3551. "multirect_mode", 0x0, 0, e_multirect_mode,
  3552. ARRAY_SIZE(e_multirect_mode), 0,
  3553. PLANE_PROP_MULTIRECT_MODE);
  3554. if (psde->features & BIT(SDE_SSPP_EXCL_RECT))
  3555. msm_property_install_volatile_range(&psde->property_info,
  3556. "excl_rect_v1", 0x0, 0, ~0, 0, PLANE_PROP_EXCL_RECT_V1);
  3557. sde_plane_rot_install_properties(plane, catalog);
  3558. msm_property_install_enum(&psde->property_info, "blend_op", 0x0, 0,
  3559. e_blend_op, ARRAY_SIZE(e_blend_op), 0, PLANE_PROP_BLEND_OP);
  3560. msm_property_install_enum(&psde->property_info, "src_config", 0x0, 1,
  3561. e_src_config, ARRAY_SIZE(e_src_config), 0,
  3562. PLANE_PROP_SRC_CONFIG);
  3563. if (psde->pipe_hw->ops.setup_solidfill)
  3564. msm_property_install_range(&psde->property_info, "color_fill",
  3565. 0, 0, 0xFFFFFFFF, 0, PLANE_PROP_COLOR_FILL);
  3566. msm_property_install_range(&psde->property_info, "prefill_size", 0x0,
  3567. 0, ~0, 0, PLANE_PROP_PREFILL_SIZE);
  3568. msm_property_install_range(&psde->property_info, "prefill_time", 0x0,
  3569. 0, ~0, 0, PLANE_PROP_PREFILL_TIME);
  3570. msm_property_install_blob(&psde->property_info, "capabilities",
  3571. DRM_MODE_PROP_IMMUTABLE, PLANE_PROP_INFO);
  3572. sde_kms_info_reset(info);
  3573. _sde_plane_setup_capabilities_blob(psde, master_plane_id, info,
  3574. catalog);
  3575. _sde_plane_install_colorproc_properties(psde, info);
  3576. msm_property_set_blob(&psde->property_info, &psde->blob_info,
  3577. info->data, SDE_KMS_INFO_DATALEN(info),
  3578. PLANE_PROP_INFO);
  3579. msm_property_install_enum(&psde->property_info, "fb_translation_mode",
  3580. 0x0, 0, e_fb_translation_mode,
  3581. ARRAY_SIZE(e_fb_translation_mode), 0,
  3582. PLANE_PROP_FB_TRANSLATION_MODE);
  3583. if (psde->pipe_hw->ops.set_ubwc_stats_roi)
  3584. msm_property_install_volatile_range(&psde->property_info, "ubwc_stats_roi",
  3585. 0, 0, ~0, 0, PLANE_PROP_UBWC_STATS_ROI);
  3586. vfree(info);
  3587. }
  3588. static inline void _sde_plane_set_csc_v1(struct sde_plane *psde,
  3589. void __user *usr_ptr, struct sde_plane_state *pstate)
  3590. {
  3591. struct sde_drm_csc_v1 csc_v1;
  3592. int i;
  3593. if (!psde || !pstate) {
  3594. SDE_ERROR("invalid plane\n");
  3595. return;
  3596. }
  3597. pstate->csc_usr_ptr = NULL;
  3598. if (!usr_ptr) {
  3599. SDE_DEBUG_PLANE(psde, "csc data removed\n");
  3600. return;
  3601. }
  3602. if (copy_from_user(&csc_v1, usr_ptr, sizeof(csc_v1))) {
  3603. SDE_ERROR_PLANE(psde, "failed to copy csc data\n");
  3604. return;
  3605. }
  3606. /* populate from user space */
  3607. for (i = 0; i < SDE_CSC_MATRIX_COEFF_SIZE; ++i)
  3608. pstate->csc_cfg.csc_mv[i] = csc_v1.ctm_coeff[i] >> 16;
  3609. for (i = 0; i < SDE_CSC_BIAS_SIZE; ++i) {
  3610. pstate->csc_cfg.csc_pre_bv[i] = csc_v1.pre_bias[i];
  3611. pstate->csc_cfg.csc_post_bv[i] = csc_v1.post_bias[i];
  3612. }
  3613. for (i = 0; i < SDE_CSC_CLAMP_SIZE; ++i) {
  3614. pstate->csc_cfg.csc_pre_lv[i] = csc_v1.pre_clamp[i];
  3615. pstate->csc_cfg.csc_post_lv[i] = csc_v1.post_clamp[i];
  3616. }
  3617. pstate->csc_usr_ptr = &pstate->csc_cfg;
  3618. }
  3619. static inline void _sde_plane_set_scaler_v1(struct sde_plane *psde,
  3620. struct sde_plane_state *pstate, void __user *usr)
  3621. {
  3622. struct sde_drm_scaler_v1 scale_v1;
  3623. struct sde_hw_pixel_ext *pe;
  3624. int i;
  3625. if (!psde || !pstate) {
  3626. SDE_ERROR("invalid argument(s)\n");
  3627. return;
  3628. }
  3629. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_NONE;
  3630. if (!usr) {
  3631. SDE_DEBUG_PLANE(psde, "scale data removed\n");
  3632. return;
  3633. }
  3634. if (copy_from_user(&scale_v1, usr, sizeof(scale_v1))) {
  3635. SDE_ERROR_PLANE(psde, "failed to copy scale data\n");
  3636. return;
  3637. }
  3638. /* force property to be dirty, even if the pointer didn't change */
  3639. msm_property_set_dirty(&psde->property_info,
  3640. &pstate->property_state, PLANE_PROP_SCALER_V1);
  3641. /* populate from user space */
  3642. pe = &pstate->pixel_ext;
  3643. memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
  3644. for (i = 0; i < SDE_MAX_PLANES; i++) {
  3645. pe->init_phase_x[i] = scale_v1.init_phase_x[i];
  3646. pe->phase_step_x[i] = scale_v1.phase_step_x[i];
  3647. pe->init_phase_y[i] = scale_v1.init_phase_y[i];
  3648. pe->phase_step_y[i] = scale_v1.phase_step_y[i];
  3649. pe->horz_filter[i] = scale_v1.horz_filter[i];
  3650. pe->vert_filter[i] = scale_v1.vert_filter[i];
  3651. }
  3652. for (i = 0; i < SDE_MAX_PLANES; i++) {
  3653. pe->left_ftch[i] = scale_v1.pe.left_ftch[i];
  3654. pe->right_ftch[i] = scale_v1.pe.right_ftch[i];
  3655. pe->left_rpt[i] = scale_v1.pe.left_rpt[i];
  3656. pe->right_rpt[i] = scale_v1.pe.right_rpt[i];
  3657. pe->roi_w[i] = scale_v1.pe.num_ext_pxls_lr[i];
  3658. pe->top_ftch[i] = scale_v1.pe.top_ftch[i];
  3659. pe->btm_ftch[i] = scale_v1.pe.btm_ftch[i];
  3660. pe->top_rpt[i] = scale_v1.pe.top_rpt[i];
  3661. pe->btm_rpt[i] = scale_v1.pe.btm_rpt[i];
  3662. pe->roi_h[i] = scale_v1.pe.num_ext_pxls_tb[i];
  3663. }
  3664. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_SCALER_V1;
  3665. SDE_EVT32_VERBOSE(DRMID(&psde->base));
  3666. SDE_DEBUG_PLANE(psde, "user property data copied\n");
  3667. }
  3668. static void _sde_plane_clear_predownscale_settings(
  3669. struct sde_plane_state *pstate)
  3670. {
  3671. pstate->pre_down.pre_downscale_x_0 = 0;
  3672. pstate->pre_down.pre_downscale_x_1 = 0;
  3673. pstate->pre_down.pre_downscale_y_0 = 0;
  3674. pstate->pre_down.pre_downscale_y_1 = 0;
  3675. }
  3676. static inline void _sde_plane_set_scaler_v2(struct sde_plane *psde,
  3677. struct sde_plane_state *pstate, void __user *usr)
  3678. {
  3679. struct sde_drm_scaler_v2 scale_v2;
  3680. struct sde_hw_pixel_ext *pe;
  3681. int i;
  3682. struct sde_hw_scaler3_cfg *cfg;
  3683. struct sde_hw_inline_pre_downscale_cfg *pd_cfg;
  3684. if (!psde || !pstate) {
  3685. SDE_ERROR("invalid argument(s)\n");
  3686. return;
  3687. }
  3688. cfg = &pstate->scaler3_cfg;
  3689. pd_cfg = &pstate->pre_down;
  3690. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_NONE;
  3691. if (!usr) {
  3692. SDE_DEBUG_PLANE(psde, "scale data removed\n");
  3693. cfg->enable = 0;
  3694. _sde_plane_clear_predownscale_settings(pstate);
  3695. goto end;
  3696. }
  3697. if (copy_from_user(&scale_v2, usr, sizeof(scale_v2))) {
  3698. SDE_ERROR_PLANE(psde, "failed to copy scale data\n");
  3699. return;
  3700. }
  3701. /* detach/ignore user data if 'disabled' */
  3702. if (!scale_v2.enable) {
  3703. SDE_DEBUG_PLANE(psde, "scale data removed\n");
  3704. cfg->enable = 0;
  3705. _sde_plane_clear_predownscale_settings(pstate);
  3706. goto end;
  3707. }
  3708. /* populate from user space */
  3709. sde_set_scaler_v2(cfg, &scale_v2);
  3710. if (_sde_plane_has_pre_downscale(psde)) {
  3711. pd_cfg->pre_downscale_x_0 = scale_v2.pre_downscale_x_0;
  3712. pd_cfg->pre_downscale_x_1 = scale_v2.pre_downscale_x_1;
  3713. pd_cfg->pre_downscale_y_0 = scale_v2.pre_downscale_y_0;
  3714. pd_cfg->pre_downscale_y_1 = scale_v2.pre_downscale_y_1;
  3715. }
  3716. pe = &pstate->pixel_ext;
  3717. memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
  3718. for (i = 0; i < SDE_MAX_PLANES; i++) {
  3719. pe->left_ftch[i] = scale_v2.pe.left_ftch[i];
  3720. pe->right_ftch[i] = scale_v2.pe.right_ftch[i];
  3721. pe->left_rpt[i] = scale_v2.pe.left_rpt[i];
  3722. pe->right_rpt[i] = scale_v2.pe.right_rpt[i];
  3723. pe->roi_w[i] = scale_v2.pe.num_ext_pxls_lr[i];
  3724. pe->top_ftch[i] = scale_v2.pe.top_ftch[i];
  3725. pe->btm_ftch[i] = scale_v2.pe.btm_ftch[i];
  3726. pe->top_rpt[i] = scale_v2.pe.top_rpt[i];
  3727. pe->btm_rpt[i] = scale_v2.pe.btm_rpt[i];
  3728. pe->roi_h[i] = scale_v2.pe.num_ext_pxls_tb[i];
  3729. }
  3730. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_SCALER_V2_CHECK;
  3731. end:
  3732. /* force property to be dirty, even if the pointer didn't change */
  3733. msm_property_set_dirty(&psde->property_info,
  3734. &pstate->property_state, PLANE_PROP_SCALER_V2);
  3735. SDE_EVT32_VERBOSE(DRMID(&psde->base), cfg->enable, cfg->de.enable,
  3736. cfg->src_width[0], cfg->src_height[0],
  3737. cfg->dst_width, cfg->dst_height);
  3738. SDE_DEBUG_PLANE(psde, "user property data copied\n");
  3739. }
  3740. static void _sde_plane_set_excl_rect_v1(struct sde_plane *psde,
  3741. struct sde_plane_state *pstate, void __user *usr_ptr)
  3742. {
  3743. struct drm_clip_rect excl_rect_v1;
  3744. if (!psde || !pstate) {
  3745. SDE_ERROR("invalid argument(s)\n");
  3746. return;
  3747. }
  3748. if (!usr_ptr) {
  3749. memset(&pstate->excl_rect, 0, sizeof(pstate->excl_rect));
  3750. SDE_DEBUG_PLANE(psde, "excl_rect data cleared\n");
  3751. return;
  3752. }
  3753. if (copy_from_user(&excl_rect_v1, usr_ptr, sizeof(excl_rect_v1))) {
  3754. SDE_ERROR_PLANE(psde, "failed to copy excl_rect data\n");
  3755. return;
  3756. }
  3757. /* populate from user space */
  3758. pstate->excl_rect.x = excl_rect_v1.x1;
  3759. pstate->excl_rect.y = excl_rect_v1.y1;
  3760. pstate->excl_rect.w = excl_rect_v1.x2 - excl_rect_v1.x1;
  3761. pstate->excl_rect.h = excl_rect_v1.y2 - excl_rect_v1.y1;
  3762. SDE_DEBUG_PLANE(psde, "excl_rect: {%d,%d,%d,%d}\n",
  3763. pstate->excl_rect.x, pstate->excl_rect.y,
  3764. pstate->excl_rect.w, pstate->excl_rect.h);
  3765. }
  3766. static void _sde_plane_set_ubwc_stats_roi(struct sde_plane *psde,
  3767. struct sde_plane_state *pstate, void __user *usr_ptr)
  3768. {
  3769. struct sde_drm_ubwc_stats_roi roi = {0};
  3770. if (!psde || !pstate) {
  3771. SDE_ERROR("invalid argument(s)\n");
  3772. return;
  3773. }
  3774. if (!usr_ptr) {
  3775. SDE_DEBUG_PLANE(psde, "ubwc roi disabled");
  3776. goto end;
  3777. }
  3778. if (copy_from_user(&roi, usr_ptr, sizeof(roi))) {
  3779. SDE_ERROR_PLANE(psde, "failed to copy ubwc stats roi");
  3780. return;
  3781. }
  3782. if (roi.y_coord0 > psde->pipe_cfg.src_rect.h || roi.y_coord1 > psde->pipe_cfg.src_rect.h) {
  3783. SDE_ERROR_PLANE(psde, "invalid ubwc roi y0 0x%x, y1 0x%x, src height 0x%x",
  3784. roi.y_coord0, roi.y_coord1, psde->pipe_cfg.src_rect.h);
  3785. memset(&roi, 0, sizeof(roi));
  3786. }
  3787. end:
  3788. SDE_EVT32(psde, roi.y_coord0, roi.y_coord1);
  3789. memcpy(&pstate->ubwc_stats_roi, &roi, sizeof(struct sde_drm_ubwc_stats_roi));
  3790. }
  3791. static int sde_plane_atomic_set_property(struct drm_plane *plane,
  3792. struct drm_plane_state *state, struct drm_property *property,
  3793. uint64_t val)
  3794. {
  3795. struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
  3796. struct sde_plane_state *pstate;
  3797. int idx, ret = -EINVAL;
  3798. SDE_DEBUG_PLANE(psde, "\n");
  3799. if (!plane) {
  3800. SDE_ERROR("invalid plane\n");
  3801. } else if (!state) {
  3802. SDE_ERROR_PLANE(psde, "invalid state\n");
  3803. } else {
  3804. pstate = to_sde_plane_state(state);
  3805. ret = msm_property_atomic_set(&psde->property_info,
  3806. &pstate->property_state, property, val);
  3807. if (!ret) {
  3808. idx = msm_property_index(&psde->property_info,
  3809. property);
  3810. switch (idx) {
  3811. case PLANE_PROP_INPUT_FENCE:
  3812. _sde_plane_set_input_fence(psde, pstate, val);
  3813. break;
  3814. case PLANE_PROP_CSC_V1:
  3815. case PLANE_PROP_CSC_DMA_V1:
  3816. _sde_plane_set_csc_v1(psde, (void __user *)val, pstate);
  3817. break;
  3818. case PLANE_PROP_SCALER_V1:
  3819. _sde_plane_set_scaler_v1(psde, pstate,
  3820. (void *)(uintptr_t)val);
  3821. break;
  3822. case PLANE_PROP_SCALER_V2:
  3823. _sde_plane_set_scaler_v2(psde, pstate,
  3824. (void *)(uintptr_t)val);
  3825. break;
  3826. case PLANE_PROP_EXCL_RECT_V1:
  3827. _sde_plane_set_excl_rect_v1(psde, pstate,
  3828. (void *)(uintptr_t)val);
  3829. break;
  3830. case PLANE_PROP_UBWC_STATS_ROI:
  3831. _sde_plane_set_ubwc_stats_roi(psde, pstate,
  3832. (void __user *)(uintptr_t)val);
  3833. break;
  3834. default:
  3835. /* nothing to do */
  3836. break;
  3837. }
  3838. }
  3839. }
  3840. SDE_DEBUG_PLANE(psde, "%s[%d] <= 0x%llx ret=%d\n",
  3841. property->name, property->base.id, val, ret);
  3842. return ret;
  3843. }
  3844. static int sde_plane_atomic_get_property(struct drm_plane *plane,
  3845. const struct drm_plane_state *state,
  3846. struct drm_property *property, uint64_t *val)
  3847. {
  3848. struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
  3849. struct sde_plane_state *pstate;
  3850. int ret = -EINVAL;
  3851. if (!plane) {
  3852. SDE_ERROR("invalid plane\n");
  3853. } else if (!state) {
  3854. SDE_ERROR("invalid state\n");
  3855. } else {
  3856. SDE_DEBUG_PLANE(psde, "\n");
  3857. pstate = to_sde_plane_state(state);
  3858. ret = msm_property_atomic_get(&psde->property_info,
  3859. &pstate->property_state, property, val);
  3860. }
  3861. return ret;
  3862. }
  3863. int sde_plane_helper_reset_custom_properties(struct drm_plane *plane,
  3864. struct drm_plane_state *plane_state)
  3865. {
  3866. struct sde_plane *psde;
  3867. struct sde_plane_state *pstate;
  3868. struct drm_property *drm_prop;
  3869. enum msm_mdp_plane_property prop_idx;
  3870. if (!plane || !plane_state) {
  3871. SDE_ERROR("invalid params\n");
  3872. return -EINVAL;
  3873. }
  3874. psde = to_sde_plane(plane);
  3875. pstate = to_sde_plane_state(plane_state);
  3876. pstate->static_cache_state = CACHE_STATE_DISABLED;
  3877. for (prop_idx = 0; prop_idx < PLANE_PROP_COUNT; prop_idx++) {
  3878. uint64_t val = pstate->property_values[prop_idx].value;
  3879. uint64_t def;
  3880. int ret;
  3881. drm_prop = msm_property_index_to_drm_property(
  3882. &psde->property_info, prop_idx);
  3883. if (!drm_prop) {
  3884. /* not all props will be installed, based on caps */
  3885. SDE_DEBUG_PLANE(psde, "invalid property index %d\n",
  3886. prop_idx);
  3887. continue;
  3888. }
  3889. def = msm_property_get_default(&psde->property_info, prop_idx);
  3890. if (val == def)
  3891. continue;
  3892. SDE_DEBUG_PLANE(psde, "set prop %s idx %d from %llu to %llu\n",
  3893. drm_prop->name, prop_idx, val, def);
  3894. ret = sde_plane_atomic_set_property(plane, plane_state,
  3895. drm_prop, def);
  3896. if (ret) {
  3897. SDE_ERROR_PLANE(psde,
  3898. "set property failed, idx %d ret %d\n",
  3899. prop_idx, ret);
  3900. continue;
  3901. }
  3902. }
  3903. return 0;
  3904. }
  3905. static void sde_plane_destroy(struct drm_plane *plane)
  3906. {
  3907. struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
  3908. SDE_DEBUG_PLANE(psde, "\n");
  3909. if (psde) {
  3910. _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);
  3911. if (psde->blob_info)
  3912. drm_property_blob_put(psde->blob_info);
  3913. msm_property_destroy(&psde->property_info);
  3914. mutex_destroy(&psde->lock);
  3915. /* this will destroy the states as well */
  3916. drm_plane_cleanup(plane);
  3917. if (psde->pipe_hw)
  3918. sde_hw_sspp_destroy(psde->pipe_hw);
  3919. kfree(psde);
  3920. }
  3921. }
  3922. void sde_plane_destroy_fb(struct drm_plane_state *state)
  3923. {
  3924. struct sde_plane_state *pstate;
  3925. if (!state) {
  3926. SDE_ERROR("invalid arg state %d\n", !state);
  3927. return;
  3928. }
  3929. pstate = to_sde_plane_state(state);
  3930. if (sde_plane_get_property(pstate, PLANE_PROP_FB_TRANSLATION_MODE) ==
  3931. SDE_DRM_FB_SEC) {
  3932. /* remove ref count for frame buffers */
  3933. if (state->fb) {
  3934. drm_framebuffer_put(state->fb);
  3935. state->fb = NULL;
  3936. }
  3937. }
  3938. }
  3939. static void sde_plane_destroy_state(struct drm_plane *plane,
  3940. struct drm_plane_state *state)
  3941. {
  3942. struct sde_plane *psde;
  3943. struct sde_plane_state *pstate;
  3944. if (!plane || !state) {
  3945. SDE_ERROR("invalid arg(s), plane %d state %d\n",
  3946. !plane, !state);
  3947. return;
  3948. }
  3949. psde = to_sde_plane(plane);
  3950. pstate = to_sde_plane_state(state);
  3951. SDE_DEBUG_PLANE(psde, "\n");
  3952. /* remove ref count for frame buffers */
  3953. if (state->fb)
  3954. drm_framebuffer_put(state->fb);
  3955. /* remove ref count for fence */
  3956. if (pstate->input_fence)
  3957. sde_sync_put(pstate->input_fence);
  3958. pstate->input_fence = 0;
  3959. /* destroy value helper */
  3960. msm_property_destroy_state(&psde->property_info, pstate,
  3961. &pstate->property_state);
  3962. }
  3963. static struct drm_plane_state *
  3964. sde_plane_duplicate_state(struct drm_plane *plane)
  3965. {
  3966. struct sde_plane *psde;
  3967. struct sde_plane_state *pstate;
  3968. struct sde_plane_state *old_state;
  3969. struct drm_property *drm_prop;
  3970. uint64_t input_fence_default;
  3971. if (!plane) {
  3972. SDE_ERROR("invalid plane\n");
  3973. return NULL;
  3974. } else if (!plane->state) {
  3975. SDE_ERROR("invalid plane state\n");
  3976. return NULL;
  3977. }
  3978. old_state = to_sde_plane_state(plane->state);
  3979. psde = to_sde_plane(plane);
  3980. if (old_state->cont_splash_populated) {
  3981. plane->state->crtc = NULL;
  3982. old_state->cont_splash_populated = false;
  3983. }
  3984. pstate = msm_property_alloc_state(&psde->property_info);
  3985. if (!pstate) {
  3986. SDE_ERROR_PLANE(psde, "failed to allocate state\n");
  3987. return NULL;
  3988. }
  3989. SDE_DEBUG_PLANE(psde, "\n");
  3990. /* duplicate value helper */
  3991. msm_property_duplicate_state(&psde->property_info, old_state, pstate,
  3992. &pstate->property_state, pstate->property_values);
  3993. /* clear out any input fence */
  3994. pstate->input_fence = 0;
  3995. input_fence_default = msm_property_get_default(
  3996. &psde->property_info, PLANE_PROP_INPUT_FENCE);
  3997. drm_prop = msm_property_index_to_drm_property(
  3998. &psde->property_info, PLANE_PROP_INPUT_FENCE);
  3999. if (msm_property_atomic_set(&psde->property_info,
  4000. &pstate->property_state, drm_prop,
  4001. input_fence_default))
  4002. SDE_DEBUG_PLANE(psde,
  4003. "error clearing duplicated input fence\n");
  4004. pstate->dirty = 0x0;
  4005. pstate->pending = false;
  4006. __drm_atomic_helper_plane_duplicate_state(plane, &pstate->base);
  4007. /* reset layout offset */
  4008. if (pstate->layout_offset) {
  4009. if (pstate->layout_offset > 0)
  4010. pstate->base.crtc_x += pstate->layout_offset;
  4011. pstate->layout = SDE_LAYOUT_NONE;
  4012. pstate->layout_offset = 0;
  4013. }
  4014. return &pstate->base;
  4015. }
  4016. static void sde_plane_reset(struct drm_plane *plane)
  4017. {
  4018. struct sde_plane *psde;
  4019. struct sde_plane_state *pstate;
  4020. if (!plane) {
  4021. SDE_ERROR("invalid plane\n");
  4022. return;
  4023. }
  4024. psde = to_sde_plane(plane);
  4025. SDE_DEBUG_PLANE(psde, "\n");
  4026. if (plane->state && !sde_crtc_is_reset_required(plane->state->crtc)) {
  4027. SDE_DEBUG_PLANE(psde, "avoid reset for plane\n");
  4028. return;
  4029. }
  4030. /* remove previous state, if present */
  4031. if (plane->state) {
  4032. sde_plane_destroy_state(plane, plane->state);
  4033. plane->state = 0;
  4034. }
  4035. pstate = msm_property_alloc_state(&psde->property_info);
  4036. if (!pstate) {
  4037. SDE_ERROR_PLANE(psde, "failed to allocate state\n");
  4038. return;
  4039. }
  4040. /* reset value helper */
  4041. msm_property_reset_state(&psde->property_info, pstate,
  4042. &pstate->property_state,
  4043. pstate->property_values);
  4044. pstate->base.plane = plane;
  4045. plane->state = &pstate->base;
  4046. }
  4047. void sde_plane_get_frame_data(struct drm_plane *plane,
  4048. struct sde_drm_plane_frame_data *data)
  4049. {
  4050. struct sde_plane *psde;
  4051. struct sde_plane_state *pstate;
  4052. struct sde_drm_ubwc_stats_data *ubwc_stats;
  4053. if (!plane) {
  4054. SDE_ERROR("invalid plane\n");
  4055. return;
  4056. }
  4057. psde = to_sde_plane(plane);
  4058. pstate = to_sde_plane_state(plane->state);
  4059. ubwc_stats = &data->ubwc_stats;
  4060. data->plane_id = DRMID(plane);
  4061. if (psde->pipe_hw->ops.get_ubwc_stats_data) {
  4062. memcpy(&ubwc_stats->roi, &pstate->ubwc_stats_roi,
  4063. sizeof(struct sde_drm_ubwc_stats_roi));
  4064. psde->pipe_hw->ops.get_ubwc_stats_data(psde->pipe_hw,
  4065. pstate->multirect_index, ubwc_stats);
  4066. }
  4067. if (psde->pipe_hw->ops.get_ubwc_error)
  4068. ubwc_stats->error = psde->pipe_hw->ops.get_ubwc_error(psde->pipe_hw,
  4069. pstate->multirect_index);
  4070. if (psde->pipe_hw->ops.clear_ubwc_error && ubwc_stats->error)
  4071. psde->pipe_hw->ops.clear_ubwc_error(psde->pipe_hw, pstate->multirect_index);
  4072. if (psde->pipe_hw->ops.get_meta_error)
  4073. ubwc_stats->meta_error = psde->pipe_hw->ops.get_meta_error(psde->pipe_hw,
  4074. pstate->multirect_index);
  4075. if (psde->pipe_hw->ops.clear_meta_error && ubwc_stats->meta_error)
  4076. psde->pipe_hw->ops.clear_meta_error(psde->pipe_hw, pstate->multirect_index);
  4077. if (ubwc_stats->error || ubwc_stats->meta_error) {
  4078. SDE_EVT32(DRMID(plane), ubwc_stats->error, ubwc_stats->meta_error,
  4079. SDE_EVTLOG_ERROR);
  4080. SDE_DEBUG_PLANE(psde, "ubwc_error:0x%x meta_error:0x%x\n",
  4081. ubwc_stats->error, ubwc_stats->meta_error);
  4082. }
  4083. }
  4084. #if IS_ENABLED(CONFIG_DEBUG_FS)
  4085. static ssize_t _sde_plane_danger_read(struct file *file,
  4086. char __user *buff, size_t count, loff_t *ppos)
  4087. {
  4088. struct sde_kms *kms = file->private_data;
  4089. struct sde_mdss_cfg *cfg = kms->catalog;
  4090. int len = 0;
  4091. char buf[40] = {'\0'};
  4092. if (!cfg)
  4093. return -ENODEV;
  4094. if (*ppos)
  4095. return 0; /* the end */
  4096. len = snprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl);
  4097. if (len < 0 || len >= sizeof(buf))
  4098. return 0;
  4099. if ((count < sizeof(buf)) || copy_to_user(buff, buf, len))
  4100. return -EFAULT;
  4101. *ppos += len; /* increase offset */
  4102. return len;
  4103. }
  4104. static void _sde_plane_set_danger_state(struct sde_kms *kms, bool enable)
  4105. {
  4106. struct drm_plane *plane;
  4107. drm_for_each_plane(plane, kms->dev) {
  4108. if (plane->fb && plane->state) {
  4109. sde_plane_danger_signal_ctrl(plane, enable);
  4110. SDE_DEBUG("plane:%d img:%dx%d ",
  4111. plane->base.id, plane->fb->width,
  4112. plane->fb->height);
  4113. SDE_DEBUG("src[%d,%d,%d,%d] dst[%d,%d,%d,%d]\n",
  4114. plane->state->src_x >> 16,
  4115. plane->state->src_y >> 16,
  4116. plane->state->src_w >> 16,
  4117. plane->state->src_h >> 16,
  4118. plane->state->crtc_x, plane->state->crtc_y,
  4119. plane->state->crtc_w, plane->state->crtc_h);
  4120. } else {
  4121. SDE_DEBUG("Inactive plane:%d\n", plane->base.id);
  4122. }
  4123. }
  4124. }
  4125. static ssize_t _sde_plane_danger_write(struct file *file,
  4126. const char __user *user_buf, size_t count, loff_t *ppos)
  4127. {
  4128. struct sde_kms *kms = file->private_data;
  4129. struct sde_mdss_cfg *cfg = kms->catalog;
  4130. int disable_panic;
  4131. char buf[10];
  4132. if (!cfg)
  4133. return -EFAULT;
  4134. if (count >= sizeof(buf))
  4135. return -EFAULT;
  4136. if (copy_from_user(buf, user_buf, count))
  4137. return -EFAULT;
  4138. buf[count] = 0; /* end of string */
  4139. if (kstrtoint(buf, 0, &disable_panic))
  4140. return -EFAULT;
  4141. if (disable_panic) {
  4142. /* Disable panic signal for all active pipes */
  4143. SDE_DEBUG("Disabling danger:\n");
  4144. _sde_plane_set_danger_state(kms, false);
  4145. kms->has_danger_ctrl = false;
  4146. } else {
  4147. /* Enable panic signal for all active pipes */
  4148. SDE_DEBUG("Enabling danger:\n");
  4149. kms->has_danger_ctrl = true;
  4150. _sde_plane_set_danger_state(kms, true);
  4151. }
  4152. return count;
  4153. }
  4154. static const struct file_operations sde_plane_danger_enable = {
  4155. .open = simple_open,
  4156. .read = _sde_plane_danger_read,
  4157. .write = _sde_plane_danger_write,
  4158. };
  4159. static int _sde_plane_init_debugfs(struct drm_plane *plane)
  4160. {
  4161. struct sde_plane *psde;
  4162. struct sde_kms *kms;
  4163. struct msm_drm_private *priv;
  4164. const struct sde_sspp_sub_blks *sblk = 0;
  4165. const struct sde_sspp_cfg *cfg = 0;
  4166. if (!plane || !plane->dev) {
  4167. SDE_ERROR("invalid arguments\n");
  4168. return -EINVAL;
  4169. }
  4170. priv = plane->dev->dev_private;
  4171. if (!priv || !priv->kms) {
  4172. SDE_ERROR("invalid KMS reference\n");
  4173. return -EINVAL;
  4174. }
  4175. kms = to_sde_kms(priv->kms);
  4176. psde = to_sde_plane(plane);
  4177. if (psde && psde->pipe_hw)
  4178. cfg = psde->pipe_hw->cap;
  4179. if (cfg)
  4180. sblk = cfg->sblk;
  4181. if (!sblk)
  4182. return 0;
  4183. /* create overall sub-directory for the pipe */
  4184. psde->debugfs_root =
  4185. debugfs_create_dir(psde->pipe_name,
  4186. plane->dev->primary->debugfs_root);
  4187. if (!psde->debugfs_root)
  4188. return -ENOMEM;
  4189. /* don't error check these */
  4190. debugfs_create_x64("features", 0400,
  4191. psde->debugfs_root, &psde->features);
  4192. if (cfg->features & BIT(SDE_SSPP_SCALER_QSEED3) ||
  4193. cfg->features & BIT(SDE_SSPP_SCALER_QSEED3LITE) ||
  4194. cfg->features & BIT(SDE_SSPP_SCALER_QSEED2))
  4195. debugfs_create_bool("default_scaling",
  4196. 0600,
  4197. psde->debugfs_root,
  4198. &psde->debugfs_default_scale);
  4199. if (cfg->features & BIT(SDE_SSPP_TRUE_INLINE_ROT)) {
  4200. debugfs_create_u32("in_rot_max_downscale_rt_num",
  4201. 0600,
  4202. psde->debugfs_root,
  4203. (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_rt_num);
  4204. debugfs_create_u32("in_rot_max_downscale_rt_denom",
  4205. 0600,
  4206. psde->debugfs_root,
  4207. (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_rt_denom);
  4208. debugfs_create_u32("in_rot_max_downscale_nrt",
  4209. 0600,
  4210. psde->debugfs_root,
  4211. (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_nrt);
  4212. debugfs_create_u32("in_rot_max_height",
  4213. 0600,
  4214. psde->debugfs_root,
  4215. (u32 *) &psde->pipe_sblk->in_rot_maxheight);
  4216. }
  4217. debugfs_create_u32("xin_id",
  4218. 0400,
  4219. psde->debugfs_root,
  4220. (u32 *) &cfg->xin_id);
  4221. debugfs_create_x32("creq_vblank",
  4222. 0600,
  4223. psde->debugfs_root,
  4224. (u32 *) &sblk->creq_vblank);
  4225. debugfs_create_x32("danger_vblank",
  4226. 0600,
  4227. psde->debugfs_root,
  4228. (u32 *) &sblk->danger_vblank);
  4229. debugfs_create_file("disable_danger",
  4230. 0600,
  4231. psde->debugfs_root,
  4232. kms, &sde_plane_danger_enable);
  4233. return 0;
  4234. }
  4235. static void _sde_plane_destroy_debugfs(struct drm_plane *plane)
  4236. {
  4237. struct sde_plane *psde;
  4238. if (!plane)
  4239. return;
  4240. psde = to_sde_plane(plane);
  4241. debugfs_remove_recursive(psde->debugfs_root);
  4242. }
  4243. #else
  4244. static int _sde_plane_init_debugfs(struct drm_plane *plane)
  4245. {
  4246. return 0;
  4247. }
  4248. static void _sde_plane_destroy_debugfs(struct drm_plane *plane)
  4249. {
  4250. }
  4251. #endif /* CONFIG_DEBUG_FS */
  4252. static int sde_plane_late_register(struct drm_plane *plane)
  4253. {
  4254. return _sde_plane_init_debugfs(plane);
  4255. }
  4256. static void sde_plane_early_unregister(struct drm_plane *plane)
  4257. {
  4258. _sde_plane_destroy_debugfs(plane);
  4259. }
  4260. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0))
  4261. static bool sde_plane_format_mod_supported(struct drm_plane *plane,
  4262. uint32_t format, uint64_t modifier)
  4263. {
  4264. return (sde_get_sde_format_ext(format, modifier) != NULL);
  4265. }
  4266. #endif
  4267. static const struct drm_plane_funcs sde_plane_funcs = {
  4268. .update_plane = drm_atomic_helper_update_plane,
  4269. .disable_plane = drm_atomic_helper_disable_plane,
  4270. .destroy = sde_plane_destroy,
  4271. .atomic_set_property = sde_plane_atomic_set_property,
  4272. .atomic_get_property = sde_plane_atomic_get_property,
  4273. .reset = sde_plane_reset,
  4274. .atomic_duplicate_state = sde_plane_duplicate_state,
  4275. .atomic_destroy_state = sde_plane_destroy_state,
  4276. .late_register = sde_plane_late_register,
  4277. .early_unregister = sde_plane_early_unregister,
  4278. #if (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0))
  4279. .format_mod_supported = sde_plane_format_mod_supported,
  4280. #endif
  4281. };
  4282. static const struct drm_plane_helper_funcs sde_plane_helper_funcs = {
  4283. .prepare_fb = sde_plane_prepare_fb,
  4284. .cleanup_fb = sde_plane_cleanup_fb,
  4285. .atomic_check = sde_plane_atomic_check,
  4286. .atomic_update = sde_plane_atomic_update,
  4287. };
  4288. enum sde_sspp sde_plane_pipe(struct drm_plane *plane)
  4289. {
  4290. return plane ? to_sde_plane(plane)->pipe : SSPP_NONE;
  4291. }
  4292. bool is_sde_plane_virtual(struct drm_plane *plane)
  4293. {
  4294. return plane ? to_sde_plane(plane)->is_virtual : false;
  4295. }
  4296. /* initialize plane */
  4297. struct drm_plane *sde_plane_init(struct drm_device *dev,
  4298. uint32_t pipe, bool primary_plane,
  4299. unsigned long possible_crtcs, u32 master_plane_id)
  4300. {
  4301. struct drm_plane *plane = NULL, *master_plane = NULL;
  4302. const struct sde_format_extended *format_list;
  4303. struct sde_plane *psde;
  4304. struct msm_drm_private *priv;
  4305. struct sde_kms *kms;
  4306. enum drm_plane_type type;
  4307. struct sde_vbif_clk_client clk_client;
  4308. int ret = -EINVAL;
  4309. if (!dev) {
  4310. SDE_ERROR("[%u]device is NULL\n", pipe);
  4311. goto exit;
  4312. }
  4313. priv = dev->dev_private;
  4314. if (!priv) {
  4315. SDE_ERROR("[%u]private data is NULL\n", pipe);
  4316. goto exit;
  4317. }
  4318. if (!priv->kms) {
  4319. SDE_ERROR("[%u]invalid KMS reference\n", pipe);
  4320. goto exit;
  4321. }
  4322. kms = to_sde_kms(priv->kms);
  4323. if (!kms->catalog) {
  4324. SDE_ERROR("[%u]invalid catalog reference\n", pipe);
  4325. goto exit;
  4326. }
  4327. /* create and zero local structure */
  4328. psde = kzalloc(sizeof(*psde), GFP_KERNEL);
  4329. if (!psde) {
  4330. SDE_ERROR("[%u]failed to allocate local plane struct\n", pipe);
  4331. ret = -ENOMEM;
  4332. goto exit;
  4333. }
  4334. /* cache local stuff for later */
  4335. plane = &psde->base;
  4336. psde->pipe = pipe;
  4337. psde->is_virtual = (master_plane_id != 0);
  4338. INIT_LIST_HEAD(&psde->mplane_list);
  4339. master_plane = drm_plane_find(dev, NULL, master_plane_id);
  4340. if (master_plane) {
  4341. struct sde_plane *mpsde = to_sde_plane(master_plane);
  4342. list_add_tail(&psde->mplane_list, &mpsde->mplane_list);
  4343. }
  4344. /* initialize underlying h/w driver */
  4345. psde->pipe_hw = sde_hw_sspp_init(pipe, kms->mmio, kms->catalog, psde->is_virtual,
  4346. &clk_client);
  4347. if (IS_ERR(psde->pipe_hw)) {
  4348. SDE_ERROR("[%u]SSPP init failed\n", pipe);
  4349. ret = PTR_ERR(psde->pipe_hw);
  4350. goto clean_plane;
  4351. } else if (!psde->pipe_hw->cap || !psde->pipe_hw->cap->sblk) {
  4352. SDE_ERROR("[%u]SSPP init returned invalid cfg\n", pipe);
  4353. goto clean_sspp;
  4354. }
  4355. if (test_bit(SDE_FEATURE_VBIF_CLK_SPLIT, kms->catalog->features)) {
  4356. ret = sde_vbif_clk_register(kms, &clk_client);
  4357. if (ret) {
  4358. SDE_ERROR("failed to register vbif client %d\n",
  4359. clk_client.clk_ctrl);
  4360. goto clean_sspp;
  4361. }
  4362. }
  4363. /* cache features mask for later */
  4364. psde->features = psde->pipe_hw->cap->features_ext;
  4365. psde->perf_features = psde->pipe_hw->cap->perf_features;
  4366. psde->pipe_sblk = psde->pipe_hw->cap->sblk;
  4367. if (!psde->pipe_sblk) {
  4368. SDE_ERROR("[%u]invalid sblk\n", pipe);
  4369. goto clean_sspp;
  4370. }
  4371. if (psde->is_virtual)
  4372. format_list = psde->pipe_sblk->virt_format_list;
  4373. else
  4374. format_list = psde->pipe_sblk->format_list;
  4375. psde->nformats = sde_populate_formats(format_list,
  4376. psde->formats,
  4377. 0,
  4378. ARRAY_SIZE(psde->formats));
  4379. if (!psde->nformats) {
  4380. SDE_ERROR("[%u]no valid formats for plane\n", pipe);
  4381. goto clean_sspp;
  4382. }
  4383. if (primary_plane)
  4384. type = DRM_PLANE_TYPE_PRIMARY;
  4385. else
  4386. type = DRM_PLANE_TYPE_OVERLAY;
  4387. ret = drm_universal_plane_init(dev, plane, 0xff, &sde_plane_funcs,
  4388. psde->formats, psde->nformats,
  4389. NULL, type, NULL);
  4390. if (ret)
  4391. goto clean_sspp;
  4392. /* Populate static array of plane property flags */
  4393. _sde_plane_map_prop_to_dirty_bits();
  4394. /* success! finalize initialization */
  4395. drm_plane_helper_add(plane, &sde_plane_helper_funcs);
  4396. msm_property_init(&psde->property_info, &plane->base, dev,
  4397. priv->plane_property, psde->property_data,
  4398. PLANE_PROP_COUNT, PLANE_PROP_BLOBCOUNT,
  4399. sizeof(struct sde_plane_state));
  4400. _sde_plane_install_properties(plane, kms->catalog, master_plane_id);
  4401. /* save user friendly pipe name for later */
  4402. snprintf(psde->pipe_name, SDE_NAME_SIZE, "plane%u", plane->base.id);
  4403. mutex_init(&psde->lock);
  4404. SDE_DEBUG("%s created for pipe:%u id:%u master:%u\n", psde->pipe_name,
  4405. pipe, plane->base.id, master_plane_id);
  4406. return plane;
  4407. clean_sspp:
  4408. if (psde && psde->pipe_hw)
  4409. sde_hw_sspp_destroy(psde->pipe_hw);
  4410. clean_plane:
  4411. kfree(psde);
  4412. exit:
  4413. return ERR_PTR(ret);
  4414. }
  4415. void sde_plane_add_data_to_minidump_va(struct drm_plane *plane)
  4416. {
  4417. struct sde_plane *sde_plane;
  4418. struct sde_plane_state *pstate;
  4419. sde_plane = to_sde_plane(plane);
  4420. pstate = to_sde_plane_state(plane->state);
  4421. sde_mini_dump_add_va_region("sde_plane", sizeof(*sde_plane), sde_plane);
  4422. sde_mini_dump_add_va_region("plane_state", sizeof(*pstate), pstate);
  4423. }