For usecase with S2-only or TVM buffers, the mapping needs to be done
after the SCM call. This is required to ensure the mapping is done to
the correct SID. Previously with S2-only usecase, the map was returning
the PA which would remain the same, so there were no issues even though
the map sequence was incorrect. But this sequence will cause issues with
CSF-2.5 as it uses 2-stage with TVM, and requires the mapping to be done
after the scm-call. Fix the sequence for legacy secure-camera preview,
legacy secure-display and CSF 2.5 solution.
Change-Id: Id663d30fdbf8725f43f61e67d2d7ce72aa9f9506
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Install volatile enum and range properties for UCSC IGC, GC, UNMULT
and ALPHA_DITHER. This will mark the force dirty property data as
true, and will avoid caching in driver by always applying the
property values set by userspace, rather than checking for modified
values.
Change-Id: Ib8132165fb58ddc829bf8610657e302e0798d72f
Signed-off-by: Alisha Thapaliya <quic_athapali@quicinc.com>
Starting with HW-Fencing, the frames hw kickoff
can take longer to trigger, given that HW will wait for the
input fences signal. Therefore, this change increments
the time-outs to wait up to ~10 secs, which corresponds
to the current input dma-fences timeout. This ~10secs
wait is given in intervals, where the dma-fence is also
checked, so in case that the client producer of the fence
signals the dma-fence, but misses the hw-fence signaling,
Display driver can handle this case and do a sw-override
to start the fetching of the incoming frame without waiting
for the input hw-fence ipc signal.
Change-Id: I6fcacbbaa79ca9847da616bd52efdda4bb8fccae
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
This change adds debug changes to dump the input fences during a
commit done timeout, when input hw-fences are enabled.
Change-Id: Ia778d3d73ab8ee795613587da70ef9bebb7c73ca
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
Map UCSC plane properties to dirty bits to perform operations
correctly.
Change-Id: I6903b62846b8b535477aeca21a6c6e910dd4f6ad
Signed-off-by: Sabarinath M B <quic_sabamb@quicinc.com>
Pipe csc configuration is being cached in the sde plane which can cause
race conditions between hardware programming and caching.
All drm properties should be cached in sde plane state to avoid race
conditions. Change moves caching to sde plane state.
Change-Id: I22470a82b2fc2812f8c526ababc2b517db13a3ce
Signed-off-by: Gopikrishnaiah Anand <quic_agopik@quicinc.com>
This change adds support for updating danger, safe and creq LUT
configuration for WB rotation use case.
Change-Id: I01784be4ea4ac5b027258df2907f3ba745a05850
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
Add support for demura v2 by adding demura blocks
2 and 3 for pineapple target.
Change-Id: I9e6107480ab44853ca49e6396787378c5c70557a
Signed-off-by: Mitika Dodiya <quic_mdodiya@quicinc.com>
Add support for UCSC block parameters that includes unmult,
IGC/GC modes, CSC coefficients, and clamps.
Change-Id: I3ef4b729e9c973a98d53dc583233bf5e004035fa
Signed-off-by: Alisha Thapaliya <quic_athapali@quicinc.com>
This change implements the drm_plane_funcs API format_mod_supported
necessary to correctly check if format modifiers are supported.
Change-Id: I39a26f7b053c44ef7577401d88e7cf6934c198f8
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
This change converts the ubwc stats roi into a blob property. This
allows for the roi data structure to be passed into kernel.
Change-Id: I4b30dcc16bcbd152428861444ff321add860942f
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
Fix UBWC stat error log format to match number of arguments.
Change-Id: I08f1b7a13e370dc7cf3a5a9fc11c089f69e742b5
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
CTL datapath idx can be switched between secondary and external displays
as per current SW code. This change avoids the clearing the SW flush ctx
in prepare_commit during resume use case. It fixes the GPU fence timeouts
seen during below scenario.
Issue scenario:
1. Primary display was using CTL_0 and it is reserved.
2. Secondary display was using CTL_1 and suspend occurred.
CTL_1 is added to RM free list.
3. When external Display is connected, it starts using CTL_1
datapath.
4. Secondary display is resumed and it starts using CTL_2.
During prepare_commit, phys_enc->hw_ctl was CTL_1 and
SW is clearing the flush ctx of external Display.
5. Since CTL_1 flush bits are cleared, SW is not programming the
CTL_FLUSH register for this composition and release/retire fences
are not signaled causing fence timeouts at GPU end and Input fence
timeout at display end finally leading to SF hung.
Change-Id: Ic843ce5c4f06f1620636abd24d443952c2ba8dc5
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
Starting mdss 9.0, dpu supports triggering
the frame fetch through hw-fencing. This change
adds support for this hw-fence feature.
Change-Id: Icc7d0b69fc2a51103d14612f5ac89b44a47ed826
Signed-off-by: Ingrid Gallardo <quic_ingridg@quicinc.com>
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
Toggle LLCC SCID for each consecutive LLCC write
operations and force read allocate when NSE bit
set.
Change-Id: Ice473cb126b627056b7346f142bc84c120e05f0b
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
Currently only LLCC_DISP SCID is used to read and write to
system cache during static display use case.
This changes adds SCID LLCC_DISP_1 to allow each SCID to
have a dedicated function (read/write).
Change-Id: I5604ec1183d99a8492b005ec06ac94e5db60b5f7
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
Currently a boolean variable is used to track if the system
cache feature is enable for a particular SCID.
This change converts it to use a feature bit instead.
Change-Id: I8461fd9fb837b871c4ac5c67a9ab7613aadea7bb
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
Plane cache state is updated based on the crtc's cache state.
The plane is left with state cache state, if the particular plane
is not used in the subsequent frame by the same crtc. Reset the
plane cache state on plane disable and reset_custom_properties to
avoid this case.
Change-Id: Ic6d31567af23906e94c5404d1d366e030b9be199
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Currently, when CWB system cache use case is enabled and multiple planes
are used to fetch the LLCC data only one SSPP is programmed correctly.
This change ensures that whenever the fb_cache_flag is non 0, the SSPP
system cache gets reprogrammed.
Change-Id: Ic90eaae207f6221efb1fc8749093d8b44e092e44
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
Add line insertion support for sspp, this is used to support
display with external splitter. Line insertion logic checks
the difference between screen logical height and physical
height. If any difference is observed adds dummy and active
lines on screen.
Change-Id: Ieec322273df000a53fb39e05174c2d67c3c2da81
Signed-off-by: Rajesh kv <quic_kvrajesh@quicinc.com>
SID registers and offsets are changed in display
MDSS 9.0.0. Changes are made to program these new registers.
Also, added new revision check for backward
compatibility.
Change-Id: I4e1ea374f38c95a4d1019c2596418bb6bb7c5347
Signed-off-by: Raviteja Tamatam <quic_travitej@quicinc.com>
This change avoids null pointer dereference in different APIs.
Change-Id: I01eba9d64fa4ba2fd81f7f39f586867e22d66771
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
* quic/display-kernel.lnx.5.10:
disp: msm: sde: avoid error during fal10_veto override enablement
disp: msm: update copyright description
disp: msm: sde: configure dest_scaler op_mode for two independent displays
disp: msm: dp: updated copyright set for 4nm target
Revert "disp: msm: sde: consider max of actual and default prefill lines"
disp: msm: sde: Reset backlight scale when HWC is stopped
disp: msm: dp: avoid duplicate read of link status
disp: msm: dsi: update vreg_ctrl settings for cape
disp: msm: fail commit if drm_gem_obj was found attached to a sec CB
disp: msm: dp: updated register values for 4nm target
disp: msm: sde: update framedata event handling
disp: msm: dsi: Add new phy comaptible string for cape
disp: msm: sde: software override for fal10 in cwb enable
disp: msm: update cleanup during bind failure in msm_drm_component_init
disp: msm: sde: dump user input_fence info on spec fence timeout
disp: msm: sde: add null pointer check for encoder current master
disp: msm: dsi: enable DMA start window scheduling for broadcast commands
disp: msm: sde: avoid alignment checks for linear formats
disp: msm: reset thread priority work on every new run
disp: msm: sde: send power on event for cont. splash
disp: msm: sde: always set CTL_x_UIDLE_ACTIVE register to "1"
disp: msm: use vzalloc for large allocations
disp: msm: sde: Add support to limit DSC size to 10k
disp: msm: sde: add tx wait during DMS for sim panel
disp: msm: dsi: add check for any queued DSI CMDs before clock force update
disp: msm: sde: correct pp block allocation during dcwb dither programming
disp: msm: sde: avoid setting of max vblank count
disp: msm: sde: add cached lut flag in sde plane
disp: msm: sde: avoid use after free in msm_lastclose
disp: msm: sde: update TEAR_SYNC_WRCOUNT register before vsync counter
disp: msm: dsi: Support uncompressed rgb101010 format
disp: msm: sde: update idle_pc_enabled flag for all encoders
disp: msm: sde: flush esd work before disabling the encoder
disp: msm: sde: allow qsync update along with modeset
disp: msm: dp: avoid dp sw reset on disconnect path
disp: msm: sde: consider max of actual and default prefill lines
disp: msm: ensure vbif debugbus not in use is disabled
disp: msm: sde: update cached encoder mask if required
disp: msm: sde: while timing engine enabling poll for active region
disp: msm: enable cache flag for dumb buffer
disp: msm: sde: disable ot limit for cwb
disp: msm: sde: avoid race condition at vm release
disp: msm: dsi: set qsync min fps list length to zero
disp: msm: sde: reset mixers in crtc when ctl datapath switches
disp: msm: sde: update vm state atomic check for non-primary usecases
disp: msm: sde: reset CTL_UIDLE_ACTIVE register only if uidle is disabled
Change-Id: If480e7f33743eb4788549f853ba05e744ecb38d3
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
Kalama adds support for uidle fill level scaling to allow
fal10 mode for 90 and above fps use cases.
Pre-Kalama, the fill levels are clamped at 4-bit values supported
by the threshold registers. But to achieve the targeted 50us idle
time on fal10 modes with higher FPS use cases, we need fill levels
higher than 15 (max for 4 bit). The hardware change in Kalama
achieves by using a 5 bit scale factor in combination with the
programmed threshold values.
Change-Id: I638705355c03910a83e7d922b6fe48ab11c120a8
Signed-off-by: Jeykumar Sankaran <quic_jeykumar@quicinc.com>
This change fails the drm_atomic_commit and avoids S2 translation
fault if drm_gem_object is found attached to a secure context bank
during non secure session. In the current codeflow, we are detaching
the gem object from secure CB and reattaching it to non secure CB,
but only S1 pagetables entries get modified and S2 pagetables entries
are not corrected since hyp_unassign is not called with CP_PIXEL
VMID which can only be done by client when buffer gets allocated.
Change-Id: I62302064f96276ef82044ee88fb89e295fb96b4b
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
This change updates framedata event and ubwc stats API to
align with userspace handling and expectations.
This change adds the empty irq event handler required to register
the frame data event.
This change also adds handling to the crtc event notify to provide
the payload pointer directly, required for the buffer object,
ensuring pointers are not mismatched while sending drm events.
This change also updates the ubwc roi plane property to process the
uapi defined roi.
Change-Id: I209f2b7418a0ec33aa0488119eb3fdb8ae94e8ba
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
Use #if IS_ENABLED() instead of #ifdef for configurations as vendor module
guidelines.
Use #if IS_ENABLED(CONFIG_XXX) instead of #ifdef CONFIG_XXX to ensure that
the code inside the #if block continues to compile if the config changes
to a tristate config in the future.
The differences are as follows:
1.#if IS_ENABLED(CONFIG_XXX) evaluates to true when CONFIG_XXX is set to
module (=m) or built-in (=y).
2.#ifdef CONFIG_XXX evaluates to true when CONFIG_XXX is set to
built-in(=y) , but doesn't when CONFIG_XXX is set to module(=m).
Use this only when you're certain you want to do the same thing
when the config is set to module or is disabled.
Change-Id: Ia806b9b01ad8414d0e4de027a382cb68e7fb4a6a
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
The HW support for RGB pipes were removed from MDSS 3.x and cursor pipes
from MDSS 4.x. Remove the support from s/w as well with this change.
Change-Id: Ib5b363234e200ee5c421684cf1904a38a5d90b58
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
pm_runtime_get_sync increases the usage_count refcount immaterial of
success/failure of the call, leading to invalid refcount on failures.
Use pm_runtime_resume_and_get instead, which takes care of reducing the
refcount on failure cases before returning from the function.
Change-Id: Ib96050d5d7ecbd717e58b8a0dde2d03312444e15
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
From kalama, add support for QoS fill level calculations based on
line-based QoS calculations.
Change-Id: I524ca29c6e9d1912b44a328a2a88d08341cccefc
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Add support to parse and configure QoS values for offline writeback.
Expose a writeback connector property to allow user-mode to set
the usage type of the writeback block - WFD, CWB, offline-WB.
Change-Id: I864f79c4896ec757ac2d8b0f57a6a5775d164f21
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Update the DT parsing logic to get danger/safe LUT values for
both portrait & landscape for all the usage types.
As part of the change, fix the correct CDP write setting for
CWB usecase.
Change-Id: I4fb6d17537de5df31c9b7f52983c0c3890265174
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Large allocations using kzalloc can lead to timeouts. This updates
the allocation calls accordingly to use vzalloc to remove
requirements on contiguous memory.
Change-Id: I86fa0ae13277d97477210a082703514df792d8a9
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
Below is the sequence during which issue is observed
while using stale lut values:
1) Scaler block is enabled in the VIG pipe along with the
valid lut configuration.
2) Idle work gets scheduled and GDSC is turned off erasing
the saved lut values.
3) At the same time, userspace sends a commit assuming lut
values are still valid resulting in artifacts on the
screen.
In the plane state scaler config, only lut flag will be
reset for subsequent commits and remaining properties such
as filter cfgs, lut_idx etc. remains same. This change
caches the lut flag in sde plane whenever the lut is being
set and reuses this flag to handle above issue.
Change-Id: I7d83d5e7a22a73a2d94b100dffe60316f92ec309
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
Commit ddac29b ("disp: msm: Pass the full state to crtc plane and connector
atomic functions") pass full state to crtc, plane, and connector atomic
functions and retrieve drm_crtc/plane/connector_state within the atomic
function.
This change puts macros in the callers of atomic functions to handle API
changes between kernel version 5.10 and version 5.15.
Change-Id: I8e710e33f0a149bbfaa54820a7174a05810e2da4
Signed-off-by: Bruce Hoo <bingchua@codeaurora.org>
Add a cache_flag in msm_fb object to store the system cache state hints.
Writeback connector will store cache write hints if system cache write
is enabled while HW is writing into this buffer. Plane in the primary
display path, in a 2-pass composition strategy will use this cache hints
to enable the display HW to use system cache for reading the pixel data
from this buffer.
Change-Id: Iff92a453a36d4a60b5a0162832eebd5e8739b5c3
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Add a custom cache_enable property in writeback connector to allow
user-mode to control the cache setting on a frame basis. Configure
the hw and activate/deactivate the llcc based on the property. The
custom property is added based on the availability of the system
cache for writeback.
Change-Id: I812b31955eb36c75c33ac279b56502a13f7cdcbf
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Add support to enable writeback block to use system cache for writing
the output buffer. This is useful in cases where output is routed to
primary source pipes with 2-pass composition. The implementation is
modelled based on existing pipe based cache configuration.
Change-Id: I2b9a96c5b42eb5727d11ca0f337aeeb4e69362c9
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Expand various SSPP and CTL related data structures
to support DMA 4,5.
Change-Id: I0ce052b6a2f1599a9b6eb82ce8e4f34f4c68333d
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
Align the HW catalog to use common naming amongst the "revision"
and "version" structure members.
Change-Id: Ib6c81aee6cb49208b0699db4a75b4eb9dc79e800
Signed-off-by: Steve Cohen <quic_cohens@quicinc.com>
