dp_pll_10nm.h 1.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0-only */
  2. /*
  3. * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
  4. */
  5. #ifndef __MDSS_DP_PLL_10NM_H
  6. #define __MDSS_DP_PLL_10NM_H
  7. #define DP_VCO_HSCLK_RATE_1620MHZDIV1000 1620000UL
  8. #define DP_VCO_HSCLK_RATE_2700MHZDIV1000 2700000UL
  9. #define DP_VCO_HSCLK_RATE_5400MHZDIV1000 5400000UL
  10. #define DP_VCO_HSCLK_RATE_8100MHZDIV1000 8100000UL
  11. struct dp_pll_db {
  12. struct mdss_pll_resources *pll;
  13. /* lane and orientation settings */
  14. u8 lane_cnt;
  15. u8 orientation;
  16. /* COM PHY settings */
  17. u32 hsclk_sel;
  18. u32 dec_start_mode0;
  19. u32 div_frac_start1_mode0;
  20. u32 div_frac_start2_mode0;
  21. u32 div_frac_start3_mode0;
  22. u32 integloop_gain0_mode0;
  23. u32 integloop_gain1_mode0;
  24. u32 vco_tune_map;
  25. u32 lock_cmp1_mode0;
  26. u32 lock_cmp2_mode0;
  27. u32 lock_cmp3_mode0;
  28. u32 lock_cmp_en;
  29. /* PHY vco divider */
  30. u32 phy_vco_div;
  31. };
  32. int dp_vco_set_rate_10nm(struct clk_hw *hw, unsigned long rate,
  33. unsigned long parent_rate);
  34. unsigned long dp_vco_recalc_rate_10nm(struct clk_hw *hw,
  35. unsigned long parent_rate);
  36. long dp_vco_round_rate_10nm(struct clk_hw *hw, unsigned long rate,
  37. unsigned long *parent_rate);
  38. int dp_vco_prepare_10nm(struct clk_hw *hw);
  39. void dp_vco_unprepare_10nm(struct clk_hw *hw);
  40. int dp_mux_set_parent_10nm(void *context,
  41. unsigned int reg, unsigned int val);
  42. int dp_mux_get_parent_10nm(void *context,
  43. unsigned int reg, unsigned int *val);
  44. #endif /* __MDSS_DP_PLL_10NM_H */