sde_kms.c 117 KB

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  1. /*
  2. * Copyright (c) 2014-2021, The Linux Foundation. All rights reserved.
  3. * Copyright (C) 2013 Red Hat
  4. * Author: Rob Clark <[email protected]>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  19. #include <drm/drm_crtc.h>
  20. #include <drm/drm_fixed.h>
  21. #include <drm/drm_panel.h>
  22. #include <linux/debugfs.h>
  23. #include <linux/of_address.h>
  24. #include <linux/of_irq.h>
  25. #include <linux/dma-buf.h>
  26. #include <linux/memblock.h>
  27. #include <drm/drm_atomic_uapi.h>
  28. #include <drm/drm_probe_helper.h>
  29. #include "msm_drv.h"
  30. #include "msm_mmu.h"
  31. #include "msm_gem.h"
  32. #include "dsi_display.h"
  33. #include "dsi_drm.h"
  34. #include "sde_wb.h"
  35. #include "dp_display.h"
  36. #include "dp_drm.h"
  37. #include "dp_mst_drm.h"
  38. #include "sde_kms.h"
  39. #include "sde_core_irq.h"
  40. #include "sde_formats.h"
  41. #include "sde_hw_vbif.h"
  42. #include "sde_vbif.h"
  43. #include "sde_encoder.h"
  44. #include "sde_plane.h"
  45. #include "sde_crtc.h"
  46. #include "sde_color_processing.h"
  47. #include "sde_reg_dma.h"
  48. #include "sde_connector.h"
  49. #include "sde_vm.h"
  50. #include <linux/qcom_scm.h>
  51. #include "soc/qcom/secure_buffer.h"
  52. #include <linux/qtee_shmbridge.h>
  53. #include <linux/haven/hh_irq_lend.h>
  54. #define CREATE_TRACE_POINTS
  55. #include "sde_trace.h"
  56. /* defines for secure channel call */
  57. #define MEM_PROTECT_SD_CTRL_SWITCH 0x18
  58. #define MDP_DEVICE_ID 0x1A
  59. EXPORT_TRACEPOINT_SYMBOL(tracing_mark_write);
  60. static const char * const iommu_ports[] = {
  61. "mdp_0",
  62. };
  63. /**
  64. * Controls size of event log buffer. Specified as a power of 2.
  65. */
  66. #define SDE_EVTLOG_SIZE 1024
  67. /*
  68. * To enable overall DRM driver logging
  69. * # echo 0x2 > /sys/module/drm/parameters/debug
  70. *
  71. * To enable DRM driver h/w logging
  72. * # echo <mask> > /sys/kernel/debug/dri/0/debug/hw_log_mask
  73. *
  74. * See sde_hw_mdss.h for h/w logging mask definitions (search for SDE_DBG_MASK_)
  75. */
  76. #define SDE_DEBUGFS_DIR "msm_sde"
  77. #define SDE_DEBUGFS_HWMASKNAME "hw_log_mask"
  78. #define SDE_KMS_MODESET_LOCK_TIMEOUT_US 500
  79. #define SDE_KMS_MODESET_LOCK_MAX_TRIALS 20
  80. /**
  81. * sdecustom - enable certain driver customizations for sde clients
  82. * Enabling this modifies the standard DRM behavior slightly and assumes
  83. * that the clients have specific knowledge about the modifications that
  84. * are involved, so don't enable this unless you know what you're doing.
  85. *
  86. * Parts of the driver that are affected by this setting may be located by
  87. * searching for invocations of the 'sde_is_custom_client()' function.
  88. *
  89. * This is disabled by default.
  90. */
  91. static bool sdecustom = true;
  92. module_param(sdecustom, bool, 0400);
  93. MODULE_PARM_DESC(sdecustom, "Enable customizations for sde clients");
  94. static int sde_kms_hw_init(struct msm_kms *kms);
  95. static int _sde_kms_mmu_destroy(struct sde_kms *sde_kms);
  96. static int _sde_kms_mmu_init(struct sde_kms *sde_kms);
  97. static int _sde_kms_register_events(struct msm_kms *kms,
  98. struct drm_mode_object *obj, u32 event, bool en);
  99. bool sde_is_custom_client(void)
  100. {
  101. return sdecustom;
  102. }
  103. #ifdef CONFIG_DEBUG_FS
  104. void *sde_debugfs_get_root(struct sde_kms *sde_kms)
  105. {
  106. struct msm_drm_private *priv;
  107. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private)
  108. return NULL;
  109. priv = sde_kms->dev->dev_private;
  110. return priv->debug_root;
  111. }
  112. static int _sde_debugfs_init(struct sde_kms *sde_kms)
  113. {
  114. void *p;
  115. int rc;
  116. void *debugfs_root;
  117. p = sde_hw_util_get_log_mask_ptr();
  118. if (!sde_kms || !p)
  119. return -EINVAL;
  120. debugfs_root = sde_debugfs_get_root(sde_kms);
  121. if (!debugfs_root)
  122. return -EINVAL;
  123. /* allow debugfs_root to be NULL */
  124. debugfs_create_x32(SDE_DEBUGFS_HWMASKNAME, 0600, debugfs_root, p);
  125. (void) sde_debugfs_vbif_init(sde_kms, debugfs_root);
  126. (void) sde_debugfs_core_irq_init(sde_kms, debugfs_root);
  127. rc = sde_core_perf_debugfs_init(&sde_kms->perf, debugfs_root);
  128. if (rc) {
  129. SDE_ERROR("failed to init perf %d\n", rc);
  130. return rc;
  131. }
  132. if (sde_kms->catalog->qdss_count)
  133. debugfs_create_u32("qdss", 0600, debugfs_root,
  134. (u32 *)&sde_kms->qdss_enabled);
  135. debugfs_create_u32("pm_suspend_clk_dump", 0600, debugfs_root,
  136. (u32 *)&sde_kms->pm_suspend_clk_dump);
  137. return 0;
  138. }
  139. static void sde_kms_debugfs_destroy(struct msm_kms *kms)
  140. {
  141. struct sde_kms *sde_kms = to_sde_kms(kms);
  142. /* don't need to NULL check debugfs_root */
  143. if (sde_kms) {
  144. sde_debugfs_vbif_destroy(sde_kms);
  145. sde_debugfs_core_irq_destroy(sde_kms);
  146. }
  147. }
  148. static int _sde_kms_dump_clks_state(struct sde_kms *sde_kms)
  149. {
  150. int i;
  151. struct device *dev = sde_kms->dev->dev;
  152. SDE_INFO("runtime PM suspended:%d", pm_runtime_suspended(dev));
  153. for (i = 0; i < sde_kms->dsi_display_count; i++)
  154. dsi_display_dump_clks_state(sde_kms->dsi_displays[i]);
  155. return 0;
  156. }
  157. #else
  158. static int _sde_debugfs_init(struct sde_kms *sde_kms)
  159. {
  160. return 0;
  161. }
  162. static void sde_kms_debugfs_destroy(struct msm_kms *kms)
  163. {
  164. }
  165. static int _sde_kms_dump_clks_state(struct sde_kms *sde_kms)
  166. {
  167. return 0;
  168. }
  169. #endif
  170. static void sde_kms_wait_for_frame_transfer_complete(struct msm_kms *kms,
  171. struct drm_crtc *crtc)
  172. {
  173. struct drm_encoder *encoder;
  174. struct drm_device *dev;
  175. int ret;
  176. if (!kms || !crtc || !crtc->state || !crtc->dev) {
  177. SDE_ERROR("invalid params\n");
  178. return;
  179. }
  180. if (!crtc->state->enable) {
  181. SDE_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
  182. return;
  183. }
  184. if (!crtc->state->active) {
  185. SDE_DEBUG("[crtc:%d] not active\n", crtc->base.id);
  186. return;
  187. }
  188. dev = crtc->dev;
  189. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  190. if (encoder->crtc != crtc)
  191. continue;
  192. /*
  193. * Video Mode - Wait for VSYNC
  194. * Cmd Mode - Wait for PP_DONE. Will be no-op if transfer is
  195. * complete
  196. */
  197. SDE_EVT32_VERBOSE(DRMID(crtc));
  198. ret = sde_encoder_wait_for_event(encoder, MSM_ENC_TX_COMPLETE);
  199. if (ret && ret != -EWOULDBLOCK) {
  200. SDE_ERROR(
  201. "[crtc: %d][enc: %d] wait for commit done returned %d\n",
  202. crtc->base.id, encoder->base.id, ret);
  203. break;
  204. }
  205. }
  206. }
  207. static int _sde_kms_secure_ctrl_xin_clients(struct sde_kms *sde_kms,
  208. struct drm_crtc *crtc, bool enable)
  209. {
  210. struct drm_device *dev;
  211. struct msm_drm_private *priv;
  212. struct sde_mdss_cfg *sde_cfg;
  213. struct drm_plane *plane;
  214. int i, ret;
  215. dev = sde_kms->dev;
  216. priv = dev->dev_private;
  217. sde_cfg = sde_kms->catalog;
  218. ret = sde_vbif_halt_xin_mask(sde_kms,
  219. sde_cfg->sui_block_xin_mask, enable);
  220. if (ret) {
  221. SDE_ERROR("failed to halt some xin-clients, ret:%d\n", ret);
  222. return ret;
  223. }
  224. if (enable) {
  225. for (i = 0; i < priv->num_planes; i++) {
  226. plane = priv->planes[i];
  227. sde_plane_secure_ctrl_xin_client(plane, crtc);
  228. }
  229. }
  230. return 0;
  231. }
  232. /**
  233. * _sde_kms_scm_call - makes secure channel call to switch the VMIDs
  234. * @sde_kms: Pointer to sde_kms struct
  235. * @vimd: switch the stage 2 translation to this VMID
  236. */
  237. static int _sde_kms_scm_call(struct sde_kms *sde_kms, int vmid)
  238. {
  239. struct device dummy = {};
  240. dma_addr_t dma_handle;
  241. uint32_t num_sids;
  242. uint32_t *sec_sid;
  243. struct sde_mdss_cfg *sde_cfg = sde_kms->catalog;
  244. int ret = 0, i;
  245. struct qtee_shm shm;
  246. bool qtee_en = qtee_shmbridge_is_enabled();
  247. phys_addr_t mem_addr;
  248. u64 mem_size;
  249. num_sids = sde_cfg->sec_sid_mask_count;
  250. if (!num_sids) {
  251. SDE_ERROR("secure SID masks not configured, vmid 0x%x\n", vmid);
  252. return -EINVAL;
  253. }
  254. if (qtee_en) {
  255. ret = qtee_shmbridge_allocate_shm(num_sids * sizeof(uint32_t),
  256. &shm);
  257. if (ret)
  258. return -ENOMEM;
  259. sec_sid = (uint32_t *) shm.vaddr;
  260. mem_addr = shm.paddr;
  261. /**
  262. * SMMUSecureModeSwitch requires the size to be number of SID's
  263. * but shm allocates size in pages. Modify the args as per
  264. * client requirement.
  265. */
  266. mem_size = sizeof(uint32_t) * num_sids;
  267. } else {
  268. sec_sid = kcalloc(num_sids, sizeof(uint32_t), GFP_KERNEL);
  269. if (!sec_sid)
  270. return -ENOMEM;
  271. mem_addr = virt_to_phys(sec_sid);
  272. mem_size = sizeof(uint32_t) * num_sids;
  273. }
  274. for (i = 0; i < num_sids; i++) {
  275. sec_sid[i] = sde_cfg->sec_sid_mask[i];
  276. SDE_DEBUG("sid_mask[%d]: %d\n", i, sec_sid[i]);
  277. }
  278. ret = dma_coerce_mask_and_coherent(&dummy, DMA_BIT_MASK(64));
  279. if (ret) {
  280. SDE_ERROR("Failed to set dma mask for dummy dev %d\n", ret);
  281. goto map_error;
  282. }
  283. set_dma_ops(&dummy, NULL);
  284. dma_handle = dma_map_single(&dummy, sec_sid,
  285. num_sids * sizeof(uint32_t), DMA_TO_DEVICE);
  286. if (dma_mapping_error(&dummy, dma_handle)) {
  287. SDE_ERROR("dma_map_single for dummy dev failed vmid 0x%x\n",
  288. vmid);
  289. goto map_error;
  290. }
  291. SDE_DEBUG("calling scm_call for vmid 0x%x, num_sids %d, qtee_en %d",
  292. vmid, num_sids, qtee_en);
  293. ret = qcom_scm_mem_protect_sd_ctrl(MDP_DEVICE_ID, mem_addr,
  294. mem_size, vmid);
  295. if (ret)
  296. SDE_ERROR("Error:scm_call2, vmid %lld, ret%d\n",
  297. vmid, ret);
  298. SDE_EVT32(MEM_PROTECT_SD_CTRL_SWITCH, MDP_DEVICE_ID, mem_size,
  299. vmid, qtee_en, num_sids, ret);
  300. dma_unmap_single(&dummy, dma_handle,
  301. num_sids * sizeof(uint32_t), DMA_TO_DEVICE);
  302. map_error:
  303. if (qtee_en)
  304. qtee_shmbridge_free_shm(&shm);
  305. else
  306. kfree(sec_sid);
  307. return ret;
  308. }
  309. static int _sde_kms_detach_all_cb(struct sde_kms *sde_kms, u32 vmid)
  310. {
  311. u32 ret;
  312. if (atomic_inc_return(&sde_kms->detach_all_cb) > 1)
  313. return 0;
  314. /* detach_all_contexts */
  315. ret = sde_kms_mmu_detach(sde_kms, false);
  316. if (ret) {
  317. SDE_ERROR("failed to detach all cb ret:%d\n", ret);
  318. goto mmu_error;
  319. }
  320. ret = _sde_kms_scm_call(sde_kms, vmid);
  321. if (ret) {
  322. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  323. goto scm_error;
  324. }
  325. return 0;
  326. scm_error:
  327. sde_kms_mmu_attach(sde_kms, false);
  328. mmu_error:
  329. atomic_dec(&sde_kms->detach_all_cb);
  330. return ret;
  331. }
  332. static int _sde_kms_attach_all_cb(struct sde_kms *sde_kms, u32 vmid,
  333. u32 old_vmid)
  334. {
  335. u32 ret;
  336. if (atomic_dec_return(&sde_kms->detach_all_cb) != 0)
  337. return 0;
  338. ret = _sde_kms_scm_call(sde_kms, vmid);
  339. if (ret) {
  340. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  341. goto scm_error;
  342. }
  343. /* attach_all_contexts */
  344. ret = sde_kms_mmu_attach(sde_kms, false);
  345. if (ret) {
  346. SDE_ERROR("failed to attach all cb ret:%d\n", ret);
  347. goto mmu_error;
  348. }
  349. return 0;
  350. mmu_error:
  351. _sde_kms_scm_call(sde_kms, old_vmid);
  352. scm_error:
  353. atomic_inc(&sde_kms->detach_all_cb);
  354. return ret;
  355. }
  356. static int _sde_kms_detach_sec_cb(struct sde_kms *sde_kms, int vmid)
  357. {
  358. u32 ret;
  359. if (atomic_inc_return(&sde_kms->detach_sec_cb) > 1)
  360. return 0;
  361. /* detach secure_context */
  362. ret = sde_kms_mmu_detach(sde_kms, true);
  363. if (ret) {
  364. SDE_ERROR("failed to detach sec cb ret:%d\n", ret);
  365. goto mmu_error;
  366. }
  367. ret = _sde_kms_scm_call(sde_kms, vmid);
  368. if (ret) {
  369. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  370. goto scm_error;
  371. }
  372. return 0;
  373. scm_error:
  374. sde_kms_mmu_attach(sde_kms, true);
  375. mmu_error:
  376. atomic_dec(&sde_kms->detach_sec_cb);
  377. return ret;
  378. }
  379. static int _sde_kms_attach_sec_cb(struct sde_kms *sde_kms, u32 vmid,
  380. u32 old_vmid)
  381. {
  382. u32 ret;
  383. if (atomic_dec_return(&sde_kms->detach_sec_cb) != 0)
  384. return 0;
  385. ret = _sde_kms_scm_call(sde_kms, vmid);
  386. if (ret) {
  387. goto scm_error;
  388. SDE_ERROR("scm call failed for vmid:%d\n", vmid);
  389. }
  390. ret = sde_kms_mmu_attach(sde_kms, true);
  391. if (ret) {
  392. SDE_ERROR("failed to attach sec cb ret:%d\n", ret);
  393. goto mmu_error;
  394. }
  395. return 0;
  396. mmu_error:
  397. _sde_kms_scm_call(sde_kms, old_vmid);
  398. scm_error:
  399. atomic_inc(&sde_kms->detach_sec_cb);
  400. return ret;
  401. }
  402. static int _sde_kms_sui_misr_ctrl(struct sde_kms *sde_kms,
  403. struct drm_crtc *crtc, bool enable)
  404. {
  405. int ret;
  406. if (enable) {
  407. ret = pm_runtime_get_sync(sde_kms->dev->dev);
  408. if (ret < 0) {
  409. SDE_ERROR("failed to enable resource, ret:%d\n", ret);
  410. return ret;
  411. }
  412. sde_crtc_misr_setup(crtc, true, 1);
  413. ret = _sde_kms_secure_ctrl_xin_clients(sde_kms, crtc, true);
  414. if (ret) {
  415. sde_crtc_misr_setup(crtc, false, 0);
  416. pm_runtime_put_sync(sde_kms->dev->dev);
  417. return ret;
  418. }
  419. } else {
  420. _sde_kms_secure_ctrl_xin_clients(sde_kms, crtc, false);
  421. sde_crtc_misr_setup(crtc, false, 0);
  422. pm_runtime_put_sync(sde_kms->dev->dev);
  423. }
  424. return 0;
  425. }
  426. static int _sde_kms_secure_ctrl(struct sde_kms *sde_kms, struct drm_crtc *crtc,
  427. bool post_commit)
  428. {
  429. struct sde_kms_smmu_state_data *smmu_state = &sde_kms->smmu_state;
  430. int old_smmu_state = smmu_state->state;
  431. int ret = 0;
  432. u32 vmid;
  433. if (!sde_kms || !crtc) {
  434. SDE_ERROR("invalid argument(s)\n");
  435. return -EINVAL;
  436. }
  437. SDE_EVT32(DRMID(crtc), smmu_state->state, smmu_state->transition_type,
  438. post_commit, smmu_state->sui_misr_state,
  439. smmu_state->secure_level, SDE_EVTLOG_FUNC_ENTRY);
  440. if ((!smmu_state->transition_type) ||
  441. ((smmu_state->transition_type == POST_COMMIT) && !post_commit))
  442. /* Bail out */
  443. return 0;
  444. /* enable sui misr if requested, before the transition */
  445. if (smmu_state->sui_misr_state == SUI_MISR_ENABLE_REQ) {
  446. ret = _sde_kms_sui_misr_ctrl(sde_kms, crtc, true);
  447. if (ret) {
  448. smmu_state->sui_misr_state = NONE;
  449. goto end;
  450. }
  451. }
  452. mutex_lock(&sde_kms->secure_transition_lock);
  453. switch (smmu_state->state) {
  454. case DETACH_ALL_REQ:
  455. ret = _sde_kms_detach_all_cb(sde_kms, VMID_CP_SEC_DISPLAY);
  456. if (!ret)
  457. smmu_state->state = DETACHED;
  458. break;
  459. case ATTACH_ALL_REQ:
  460. ret = _sde_kms_attach_all_cb(sde_kms, VMID_CP_PIXEL,
  461. VMID_CP_SEC_DISPLAY);
  462. if (!ret) {
  463. smmu_state->state = ATTACHED;
  464. smmu_state->secure_level = SDE_DRM_SEC_NON_SEC;
  465. }
  466. break;
  467. case DETACH_SEC_REQ:
  468. vmid = (smmu_state->secure_level == SDE_DRM_SEC_ONLY) ?
  469. VMID_CP_SEC_DISPLAY : VMID_CP_CAMERA_PREVIEW;
  470. ret = _sde_kms_detach_sec_cb(sde_kms, vmid);
  471. if (!ret)
  472. smmu_state->state = DETACHED_SEC;
  473. break;
  474. case ATTACH_SEC_REQ:
  475. vmid = (smmu_state->secure_level == SDE_DRM_SEC_ONLY) ?
  476. VMID_CP_SEC_DISPLAY : VMID_CP_CAMERA_PREVIEW;
  477. ret = _sde_kms_attach_sec_cb(sde_kms, VMID_CP_PIXEL, vmid);
  478. if (!ret) {
  479. smmu_state->state = ATTACHED;
  480. smmu_state->secure_level = SDE_DRM_SEC_NON_SEC;
  481. }
  482. break;
  483. default:
  484. SDE_ERROR("crtc%d: invalid smmu state %d transition type %d\n",
  485. DRMID(crtc), smmu_state->state,
  486. smmu_state->transition_type);
  487. ret = -EINVAL;
  488. break;
  489. }
  490. mutex_unlock(&sde_kms->secure_transition_lock);
  491. /* disable sui misr if requested, after the transition */
  492. if (!ret && (smmu_state->sui_misr_state == SUI_MISR_DISABLE_REQ)) {
  493. ret = _sde_kms_sui_misr_ctrl(sde_kms, crtc, false);
  494. if (ret)
  495. goto end;
  496. }
  497. end:
  498. smmu_state->transition_error = false;
  499. if (ret) {
  500. smmu_state->transition_error = true;
  501. SDE_ERROR(
  502. "crtc%d: req_state %d, new_state %d, sec_lvl %d, ret %d\n",
  503. DRMID(crtc), old_smmu_state, smmu_state->state,
  504. smmu_state->secure_level, ret);
  505. smmu_state->state = smmu_state->prev_state;
  506. smmu_state->secure_level = smmu_state->prev_secure_level;
  507. if (smmu_state->sui_misr_state == SUI_MISR_ENABLE_REQ)
  508. _sde_kms_sui_misr_ctrl(sde_kms, crtc, false);
  509. }
  510. SDE_DEBUG("crtc %d: req_state %d, new_state %d, sec_lvl %d, ret %d\n",
  511. DRMID(crtc), old_smmu_state, smmu_state->state,
  512. smmu_state->secure_level, ret);
  513. SDE_EVT32(DRMID(crtc), smmu_state->state, smmu_state->prev_state,
  514. smmu_state->transition_type,
  515. smmu_state->transition_error,
  516. smmu_state->secure_level, smmu_state->prev_secure_level,
  517. smmu_state->sui_misr_state, ret, SDE_EVTLOG_FUNC_EXIT);
  518. smmu_state->sui_misr_state = NONE;
  519. smmu_state->transition_type = NONE;
  520. return ret;
  521. }
  522. static int sde_kms_prepare_secure_transition(struct msm_kms *kms,
  523. struct drm_atomic_state *state)
  524. {
  525. struct drm_crtc *crtc;
  526. struct drm_crtc_state *old_crtc_state;
  527. struct drm_plane_state *old_plane_state, *new_plane_state;
  528. struct drm_plane *plane;
  529. struct drm_plane_state *plane_state;
  530. struct sde_kms *sde_kms = to_sde_kms(kms);
  531. struct drm_device *dev = sde_kms->dev;
  532. int i, ops = 0, ret = 0;
  533. bool old_valid_fb = false;
  534. struct sde_kms_smmu_state_data *smmu_state = &sde_kms->smmu_state;
  535. for_each_old_crtc_in_state(state, crtc, old_crtc_state, i) {
  536. if (!crtc->state || !crtc->state->active)
  537. continue;
  538. /*
  539. * It is safe to assume only one active crtc,
  540. * and compatible translation modes on the
  541. * planes staged on this crtc.
  542. * otherwise validation would have failed.
  543. * For this CRTC,
  544. */
  545. /*
  546. * 1. Check if old state on the CRTC has planes
  547. * staged with valid fbs
  548. */
  549. for_each_old_plane_in_state(state, plane, plane_state, i) {
  550. if (!plane_state->crtc)
  551. continue;
  552. if (plane_state->fb) {
  553. old_valid_fb = true;
  554. break;
  555. }
  556. }
  557. /*
  558. * 2.Get the operations needed to be performed before
  559. * secure transition can be initiated.
  560. */
  561. ops = sde_crtc_get_secure_transition_ops(crtc,
  562. old_crtc_state, old_valid_fb);
  563. if (ops < 0) {
  564. SDE_ERROR("invalid secure operations %x\n", ops);
  565. return ops;
  566. }
  567. if (!ops) {
  568. smmu_state->transition_error = false;
  569. goto no_ops;
  570. }
  571. SDE_DEBUG("%d:secure operations(%x) started on state:%pK\n",
  572. crtc->base.id, ops, crtc->state);
  573. SDE_EVT32(DRMID(crtc), ops, crtc->state, old_valid_fb);
  574. /* 3. Perform operations needed for secure transition */
  575. if (ops & SDE_KMS_OPS_WAIT_FOR_TX_DONE) {
  576. SDE_DEBUG("wait_for_transfer_done\n");
  577. sde_kms_wait_for_frame_transfer_complete(kms, crtc);
  578. }
  579. if (ops & SDE_KMS_OPS_CLEANUP_PLANE_FB) {
  580. SDE_DEBUG("cleanup planes\n");
  581. drm_atomic_helper_cleanup_planes(dev, state);
  582. for_each_oldnew_plane_in_state(state, plane,
  583. old_plane_state, new_plane_state, i)
  584. sde_plane_destroy_fb(old_plane_state);
  585. }
  586. if (ops & SDE_KMS_OPS_SECURE_STATE_CHANGE) {
  587. SDE_DEBUG("secure ctrl\n");
  588. _sde_kms_secure_ctrl(sde_kms, crtc, false);
  589. }
  590. if (ops & SDE_KMS_OPS_PREPARE_PLANE_FB) {
  591. SDE_DEBUG("prepare planes %d",
  592. crtc->state->plane_mask);
  593. drm_atomic_crtc_for_each_plane(plane,
  594. crtc) {
  595. const struct drm_plane_helper_funcs *funcs;
  596. plane_state = plane->state;
  597. funcs = plane->helper_private;
  598. SDE_DEBUG("psde:%d FB[%u]\n",
  599. plane->base.id,
  600. plane->fb->base.id);
  601. if (!funcs)
  602. continue;
  603. if (funcs->prepare_fb(plane, plane_state)) {
  604. ret = funcs->prepare_fb(plane,
  605. plane_state);
  606. if (ret)
  607. return ret;
  608. }
  609. }
  610. }
  611. SDE_EVT32(DRMID(crtc), SDE_EVTLOG_FUNC_EXIT);
  612. SDE_DEBUG("secure operations completed\n");
  613. }
  614. no_ops:
  615. return 0;
  616. }
  617. static int _sde_kms_release_splash_buffer(unsigned int mem_addr,
  618. unsigned int splash_buffer_size,
  619. unsigned int ramdump_base,
  620. unsigned int ramdump_buffer_size)
  621. {
  622. unsigned long pfn_start, pfn_end, pfn_idx;
  623. int ret = 0;
  624. if (!mem_addr || !splash_buffer_size) {
  625. SDE_ERROR("invalid params\n");
  626. return -EINVAL;
  627. }
  628. /* leave ramdump memory only if base address matches */
  629. if (ramdump_base == mem_addr &&
  630. ramdump_buffer_size <= splash_buffer_size) {
  631. mem_addr += ramdump_buffer_size;
  632. splash_buffer_size -= ramdump_buffer_size;
  633. }
  634. pfn_start = mem_addr >> PAGE_SHIFT;
  635. pfn_end = (mem_addr + splash_buffer_size) >> PAGE_SHIFT;
  636. ret = memblock_free(mem_addr, splash_buffer_size);
  637. if (ret) {
  638. SDE_ERROR("continuous splash memory free failed:%d\n", ret);
  639. return ret;
  640. }
  641. for (pfn_idx = pfn_start; pfn_idx < pfn_end; pfn_idx++)
  642. free_reserved_page(pfn_to_page(pfn_idx));
  643. return ret;
  644. }
  645. static int _sde_kms_splash_mem_get(struct sde_kms *sde_kms,
  646. struct sde_splash_mem *splash)
  647. {
  648. struct msm_mmu *mmu = NULL;
  649. int ret = 0;
  650. if (!sde_kms->aspace[0]) {
  651. SDE_ERROR("aspace not found for sde kms node\n");
  652. return -EINVAL;
  653. }
  654. mmu = sde_kms->aspace[0]->mmu;
  655. if (!mmu) {
  656. SDE_ERROR("mmu not found for aspace\n");
  657. return -EINVAL;
  658. }
  659. if (!splash || !mmu->funcs || !mmu->funcs->one_to_one_map) {
  660. SDE_ERROR("invalid input params for map\n");
  661. return -EINVAL;
  662. }
  663. if (!splash->ref_cnt) {
  664. ret = mmu->funcs->one_to_one_map(mmu, splash->splash_buf_base,
  665. splash->splash_buf_base,
  666. splash->splash_buf_size,
  667. IOMMU_READ | IOMMU_NOEXEC);
  668. if (ret)
  669. SDE_ERROR("splash memory smmu map failed:%d\n", ret);
  670. }
  671. splash->ref_cnt++;
  672. SDE_DEBUG("one2one mapping done for base:%lx size:%x ref_cnt:%d\n",
  673. splash->splash_buf_base,
  674. splash->splash_buf_size,
  675. splash->ref_cnt);
  676. return ret;
  677. }
  678. static int _sde_kms_map_all_splash_regions(struct sde_kms *sde_kms)
  679. {
  680. int i = 0;
  681. int ret = 0;
  682. if (!sde_kms)
  683. return -EINVAL;
  684. for (i = 0; i < sde_kms->splash_data.num_splash_displays; i++) {
  685. ret = _sde_kms_splash_mem_get(sde_kms,
  686. sde_kms->splash_data.splash_display[i].splash);
  687. if (ret)
  688. return ret;
  689. }
  690. return ret;
  691. }
  692. static int _sde_kms_splash_mem_put(struct sde_kms *sde_kms,
  693. struct sde_splash_mem *splash)
  694. {
  695. struct msm_mmu *mmu = NULL;
  696. int rc = 0;
  697. if (!sde_kms || !sde_kms->aspace[0] || !sde_kms->aspace[0]->mmu) {
  698. SDE_ERROR("invalid params\n");
  699. return -EINVAL;
  700. }
  701. mmu = sde_kms->aspace[0]->mmu;
  702. if (!splash || !splash->ref_cnt ||
  703. !mmu || !mmu->funcs || !mmu->funcs->one_to_one_unmap)
  704. return -EINVAL;
  705. splash->ref_cnt--;
  706. SDE_DEBUG("splash base:%lx refcnt:%d\n",
  707. splash->splash_buf_base, splash->ref_cnt);
  708. if (!splash->ref_cnt) {
  709. mmu->funcs->one_to_one_unmap(mmu, splash->splash_buf_base,
  710. splash->splash_buf_size);
  711. rc = _sde_kms_release_splash_buffer(splash->splash_buf_base,
  712. splash->splash_buf_size, splash->ramdump_base,
  713. splash->ramdump_size);
  714. splash->splash_buf_base = 0;
  715. splash->splash_buf_size = 0;
  716. }
  717. return rc;
  718. }
  719. static int _sde_kms_unmap_all_splash_regions(struct sde_kms *sde_kms)
  720. {
  721. int i = 0;
  722. int ret = 0;
  723. if (!sde_kms || !sde_kms->splash_data.num_splash_regions)
  724. return -EINVAL;
  725. for (i = 0; i < sde_kms->splash_data.num_splash_displays; i++) {
  726. ret = _sde_kms_splash_mem_put(sde_kms,
  727. sde_kms->splash_data.splash_display[i].splash);
  728. if (ret)
  729. return ret;
  730. }
  731. return ret;
  732. }
  733. static int _sde_kms_get_blank(struct drm_crtc_state *crtc_state,
  734. struct drm_connector_state *conn_state)
  735. {
  736. int lp_mode, blank;
  737. if (crtc_state->active)
  738. lp_mode = sde_connector_get_property(conn_state,
  739. CONNECTOR_PROP_LP);
  740. else
  741. lp_mode = SDE_MODE_DPMS_OFF;
  742. switch (lp_mode) {
  743. case SDE_MODE_DPMS_ON:
  744. blank = DRM_PANEL_BLANK_UNBLANK;
  745. break;
  746. case SDE_MODE_DPMS_LP1:
  747. case SDE_MODE_DPMS_LP2:
  748. blank = DRM_PANEL_BLANK_LP;
  749. break;
  750. case SDE_MODE_DPMS_OFF:
  751. default:
  752. blank = DRM_PANEL_BLANK_POWERDOWN;
  753. break;
  754. }
  755. return blank;
  756. }
  757. static void _sde_kms_drm_check_dpms(struct drm_atomic_state *old_state,
  758. unsigned long event)
  759. {
  760. struct drm_connector *connector;
  761. struct drm_connector_state *old_conn_state;
  762. struct drm_crtc_state *old_crtc_state;
  763. struct drm_crtc *crtc;
  764. struct sde_connector *c_conn;
  765. int i, old_mode, new_mode, old_fps, new_fps;
  766. for_each_old_connector_in_state(old_state, connector,
  767. old_conn_state, i) {
  768. crtc = connector->state->crtc ? connector->state->crtc :
  769. old_conn_state->crtc;
  770. if (!crtc)
  771. continue;
  772. new_fps = crtc->state->mode.vrefresh;
  773. new_mode = _sde_kms_get_blank(crtc->state, connector->state);
  774. if (old_conn_state->crtc) {
  775. old_crtc_state = drm_atomic_get_existing_crtc_state(
  776. old_state, old_conn_state->crtc);
  777. old_fps = old_crtc_state->mode.vrefresh;
  778. old_mode = _sde_kms_get_blank(old_crtc_state,
  779. old_conn_state);
  780. } else {
  781. old_fps = 0;
  782. old_mode = DRM_PANEL_BLANK_POWERDOWN;
  783. }
  784. if ((old_mode != new_mode) || (old_fps != new_fps)) {
  785. c_conn = to_sde_connector(connector);
  786. SDE_EVT32(old_mode, new_mode, old_fps, new_fps,
  787. c_conn->panel, crtc->state->active,
  788. old_conn_state->crtc, event);
  789. pr_debug("change detected (power mode %d->%d, fps %d->%d)\n",
  790. old_mode, new_mode, old_fps, new_fps);
  791. /* If suspend resume and fps change are happening
  792. * at the same time, give preference to power mode
  793. * changes rather than fps change.
  794. */
  795. if ((old_mode == new_mode) && (old_fps != new_fps))
  796. new_mode = DRM_PANEL_BLANK_FPS_CHANGE;
  797. }
  798. }
  799. }
  800. static struct drm_crtc *sde_kms_vm_get_vm_crtc(
  801. struct drm_atomic_state *state)
  802. {
  803. int i;
  804. enum sde_crtc_vm_req vm_req = VM_REQ_NONE;
  805. struct drm_crtc *crtc, *vm_crtc = NULL;
  806. struct drm_crtc_state *new_cstate, *old_cstate;
  807. struct sde_crtc_state *vm_cstate;
  808. for_each_oldnew_crtc_in_state(state, crtc, old_cstate, new_cstate, i) {
  809. if (!new_cstate->active && !old_cstate->active)
  810. continue;
  811. vm_cstate = to_sde_crtc_state(new_cstate);
  812. vm_req = sde_crtc_get_property(vm_cstate,
  813. CRTC_PROP_VM_REQ_STATE);
  814. if (vm_req != VM_REQ_NONE) {
  815. SDE_DEBUG("valid vm request:%d found on crtc-%d\n",
  816. vm_req, crtc->base.id);
  817. vm_crtc = crtc;
  818. break;
  819. }
  820. }
  821. return vm_crtc;
  822. }
  823. int sde_kms_vm_primary_prepare_commit(struct sde_kms *sde_kms,
  824. struct drm_atomic_state *state)
  825. {
  826. struct drm_device *ddev;
  827. struct drm_crtc *crtc;
  828. struct drm_crtc_state *new_cstate;
  829. struct drm_encoder *encoder;
  830. struct drm_connector *connector;
  831. struct sde_vm_ops *vm_ops;
  832. struct sde_crtc_state *cstate;
  833. enum sde_crtc_vm_req vm_req;
  834. int rc = 0;
  835. ddev = sde_kms->dev;
  836. vm_ops = sde_vm_get_ops(sde_kms);
  837. if (!vm_ops)
  838. return -EINVAL;
  839. crtc = sde_kms_vm_get_vm_crtc(state);
  840. if (!crtc)
  841. return 0;
  842. new_cstate = drm_atomic_get_new_crtc_state(state, crtc);
  843. cstate = to_sde_crtc_state(new_cstate);
  844. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  845. if (vm_req != VM_REQ_ACQUIRE)
  846. return 0;
  847. /* enable MDSS irq line */
  848. sde_irq_update(&sde_kms->base, true);
  849. /* clear the stale IRQ status bits */
  850. if (sde_kms->hw_intr && sde_kms->hw_intr->ops.clear_all_irqs)
  851. sde_kms->hw_intr->ops.clear_all_irqs(sde_kms->hw_intr);
  852. /* enable the display path IRQ's */
  853. drm_for_each_encoder_mask(encoder, crtc->dev,
  854. crtc->state->encoder_mask) {
  855. if (sde_encoder_in_clone_mode(encoder))
  856. continue;
  857. sde_encoder_irq_control(encoder, true);
  858. }
  859. /* Schedule ESD work */
  860. list_for_each_entry(connector, &ddev->mode_config.connector_list, head)
  861. if (drm_connector_mask(connector) & crtc->state->connector_mask)
  862. sde_connector_schedule_status_work(connector, true);
  863. /* enable vblank events */
  864. drm_crtc_vblank_on(crtc);
  865. /* handle non-SDE pre_acquire */
  866. if (vm_ops->vm_client_post_acquire)
  867. rc = vm_ops->vm_client_post_acquire(sde_kms);
  868. return rc;
  869. }
  870. int sde_kms_vm_trusted_prepare_commit(struct sde_kms *sde_kms,
  871. struct drm_atomic_state *state)
  872. {
  873. struct drm_device *ddev;
  874. struct drm_plane *plane;
  875. struct drm_crtc *crtc;
  876. struct drm_crtc_state *new_cstate;
  877. struct sde_crtc_state *cstate;
  878. enum sde_crtc_vm_req vm_req;
  879. ddev = sde_kms->dev;
  880. crtc = sde_kms_vm_get_vm_crtc(state);
  881. if (!crtc)
  882. return 0;
  883. new_cstate = drm_atomic_get_new_crtc_state(state, crtc);
  884. cstate = to_sde_crtc_state(new_cstate);
  885. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  886. if (vm_req != VM_REQ_ACQUIRE)
  887. return 0;
  888. /* Clear the stale IRQ status bits */
  889. if (sde_kms->hw_intr && sde_kms->hw_intr->ops.clear_all_irqs)
  890. sde_kms->hw_intr->ops.clear_all_irqs(sde_kms->hw_intr);
  891. /* Program the SID's for the trusted VM */
  892. list_for_each_entry(plane, &ddev->mode_config.plane_list, head)
  893. sde_plane_set_sid(plane, 1);
  894. sde_hw_set_lutdma_sid(sde_kms->hw_sid, 1);
  895. return 0;
  896. }
  897. static void sde_kms_prepare_commit(struct msm_kms *kms,
  898. struct drm_atomic_state *state)
  899. {
  900. struct sde_kms *sde_kms;
  901. struct msm_drm_private *priv;
  902. struct drm_device *dev;
  903. struct drm_encoder *encoder;
  904. struct drm_crtc *crtc;
  905. struct drm_crtc_state *crtc_state;
  906. struct sde_vm_ops *vm_ops;
  907. int i, rc;
  908. if (!kms)
  909. return;
  910. sde_kms = to_sde_kms(kms);
  911. dev = sde_kms->dev;
  912. if (!dev || !dev->dev_private)
  913. return;
  914. priv = dev->dev_private;
  915. SDE_ATRACE_BEGIN("prepare_commit");
  916. rc = pm_runtime_get_sync(sde_kms->dev->dev);
  917. if (rc < 0) {
  918. SDE_ERROR("failed to enable power resources %d\n", rc);
  919. SDE_EVT32(rc, SDE_EVTLOG_ERROR);
  920. goto end;
  921. }
  922. if (sde_kms->first_kickoff) {
  923. sde_power_scale_reg_bus(&priv->phandle, VOTE_INDEX_HIGH, false);
  924. sde_kms->first_kickoff = false;
  925. }
  926. for_each_old_crtc_in_state(state, crtc, crtc_state, i) {
  927. list_for_each_entry(encoder, &dev->mode_config.encoder_list,
  928. head) {
  929. if (encoder->crtc != crtc)
  930. continue;
  931. if (sde_encoder_prepare_commit(encoder) == -ETIMEDOUT) {
  932. SDE_ERROR("crtc:%d, initiating hw reset\n",
  933. DRMID(crtc));
  934. sde_encoder_needs_hw_reset(encoder);
  935. sde_crtc_set_needs_hw_reset(crtc);
  936. }
  937. }
  938. }
  939. /*
  940. * NOTE: for secure use cases we want to apply the new HW
  941. * configuration only after completing preparation for secure
  942. * transitions prepare below if any transtions is required.
  943. */
  944. sde_kms_prepare_secure_transition(kms, state);
  945. vm_ops = sde_vm_get_ops(sde_kms);
  946. if (!vm_ops)
  947. goto end_vm;
  948. if (vm_ops->vm_prepare_commit)
  949. vm_ops->vm_prepare_commit(sde_kms, state);
  950. end_vm:
  951. _sde_kms_drm_check_dpms(state, DRM_PANEL_EARLY_EVENT_BLANK);
  952. end:
  953. SDE_ATRACE_END("prepare_commit");
  954. }
  955. static void sde_kms_commit(struct msm_kms *kms,
  956. struct drm_atomic_state *old_state)
  957. {
  958. struct sde_kms *sde_kms;
  959. struct drm_crtc *crtc;
  960. struct drm_crtc_state *old_crtc_state;
  961. int i;
  962. if (!kms || !old_state)
  963. return;
  964. sde_kms = to_sde_kms(kms);
  965. if (!sde_kms_power_resource_is_enabled(sde_kms->dev)) {
  966. SDE_ERROR("power resource is not enabled\n");
  967. return;
  968. }
  969. SDE_ATRACE_BEGIN("sde_kms_commit");
  970. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  971. if (crtc->state->active) {
  972. SDE_EVT32(DRMID(crtc), old_state);
  973. sde_crtc_commit_kickoff(crtc, old_crtc_state);
  974. }
  975. }
  976. SDE_ATRACE_END("sde_kms_commit");
  977. }
  978. static void _sde_kms_free_splash_display_data(struct sde_kms *sde_kms,
  979. struct sde_splash_display *splash_display)
  980. {
  981. if (!sde_kms || !splash_display ||
  982. !sde_kms->splash_data.num_splash_displays)
  983. return;
  984. if (sde_kms->splash_data.num_splash_regions)
  985. _sde_kms_splash_mem_put(sde_kms, splash_display->splash);
  986. sde_kms->splash_data.num_splash_displays--;
  987. SDE_DEBUG("cont_splash handoff done, remaining:%d\n",
  988. sde_kms->splash_data.num_splash_displays);
  989. memset(splash_display, 0x0, sizeof(struct sde_splash_display));
  990. }
  991. static void _sde_kms_release_splash_resource(struct sde_kms *sde_kms,
  992. struct drm_crtc *crtc)
  993. {
  994. struct msm_drm_private *priv;
  995. struct sde_splash_display *splash_display;
  996. int i;
  997. if (!sde_kms || !crtc)
  998. return;
  999. priv = sde_kms->dev->dev_private;
  1000. if (!crtc->state->active || !sde_kms->splash_data.num_splash_displays)
  1001. return;
  1002. SDE_EVT32(DRMID(crtc), crtc->state->active,
  1003. sde_kms->splash_data.num_splash_displays);
  1004. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  1005. splash_display = &sde_kms->splash_data.splash_display[i];
  1006. if (splash_display->encoder &&
  1007. crtc == splash_display->encoder->crtc)
  1008. break;
  1009. }
  1010. if (i >= MAX_DSI_DISPLAYS)
  1011. return;
  1012. if (splash_display->cont_splash_enabled) {
  1013. sde_encoder_update_caps_for_cont_splash(splash_display->encoder,
  1014. splash_display, false);
  1015. _sde_kms_free_splash_display_data(sde_kms, splash_display);
  1016. }
  1017. /* remove the votes if all displays are done with splash */
  1018. if (!sde_kms->splash_data.num_splash_displays) {
  1019. for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++)
  1020. sde_power_data_bus_set_quota(&priv->phandle, i,
  1021. SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA,
  1022. SDE_POWER_HANDLE_ENABLE_BUS_IB_QUOTA);
  1023. pm_runtime_put_sync(sde_kms->dev->dev);
  1024. }
  1025. }
  1026. int sde_kms_vm_trusted_post_commit(struct sde_kms *sde_kms,
  1027. struct drm_atomic_state *state)
  1028. {
  1029. struct sde_vm_ops *vm_ops;
  1030. struct drm_device *ddev;
  1031. struct drm_crtc *crtc;
  1032. struct drm_plane *plane;
  1033. struct drm_encoder *encoder;
  1034. struct sde_crtc_state *cstate;
  1035. struct drm_crtc_state *new_cstate;
  1036. enum sde_crtc_vm_req vm_req;
  1037. int rc = 0;
  1038. if (!sde_kms || !sde_vm_is_enabled(sde_kms))
  1039. return -EINVAL;
  1040. vm_ops = sde_vm_get_ops(sde_kms);
  1041. ddev = sde_kms->dev;
  1042. crtc = sde_kms_vm_get_vm_crtc(state);
  1043. if (!crtc)
  1044. return 0;
  1045. new_cstate = drm_atomic_get_new_crtc_state(state, crtc);
  1046. cstate = to_sde_crtc_state(new_cstate);
  1047. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  1048. if (vm_req != VM_REQ_RELEASE)
  1049. return 0;
  1050. /* if vm_req is enabled, once CRTC on the commit is guaranteed */
  1051. sde_kms_wait_for_frame_transfer_complete(&sde_kms->base, crtc);
  1052. drm_for_each_encoder_mask(encoder, crtc->dev,
  1053. crtc->state->encoder_mask) {
  1054. if (sde_encoder_in_clone_mode(encoder))
  1055. continue;
  1056. sde_encoder_irq_control(encoder, false);
  1057. }
  1058. list_for_each_entry(plane, &ddev->mode_config.plane_list, head)
  1059. sde_plane_set_sid(plane, 0);
  1060. sde_hw_set_lutdma_sid(sde_kms->hw_sid, 0);
  1061. sde_vm_lock(sde_kms);
  1062. if (vm_ops->vm_release)
  1063. rc = vm_ops->vm_release(sde_kms);
  1064. sde_vm_unlock(sde_kms);
  1065. return rc;
  1066. }
  1067. int sde_kms_vm_pre_release(struct sde_kms *sde_kms,
  1068. struct drm_atomic_state *state)
  1069. {
  1070. struct drm_device *ddev;
  1071. struct drm_crtc *crtc;
  1072. struct drm_encoder *encoder;
  1073. struct drm_connector *connector;
  1074. int rc = 0;
  1075. ddev = sde_kms->dev;
  1076. crtc = sde_kms_vm_get_vm_crtc(state);
  1077. if (!crtc)
  1078. return 0;
  1079. /* if vm_req is enabled, once CRTC on the commit is guaranteed */
  1080. sde_kms_wait_for_frame_transfer_complete(&sde_kms->base, crtc);
  1081. /* disable ESD work */
  1082. list_for_each_entry(connector,
  1083. &ddev->mode_config.connector_list, head) {
  1084. if (drm_connector_mask(connector) & crtc->state->connector_mask)
  1085. sde_connector_schedule_status_work(connector, false);
  1086. }
  1087. /* disable SDE irq's */
  1088. drm_for_each_encoder_mask(encoder, crtc->dev,
  1089. crtc->state->encoder_mask) {
  1090. if (sde_encoder_in_clone_mode(encoder))
  1091. continue;
  1092. sde_encoder_irq_control(encoder, false);
  1093. }
  1094. /* disable IRQ line */
  1095. sde_irq_update(&sde_kms->base, false);
  1096. /* disable vblank events */
  1097. drm_crtc_vblank_off(crtc);
  1098. /* reset sw state */
  1099. sde_crtc_reset_sw_state(crtc);
  1100. return rc;
  1101. }
  1102. int sde_kms_vm_primary_post_commit(struct sde_kms *sde_kms,
  1103. struct drm_atomic_state *state)
  1104. {
  1105. struct sde_vm_ops *vm_ops;
  1106. struct sde_crtc_state *cstate;
  1107. struct drm_crtc *crtc;
  1108. struct drm_crtc_state *new_cstate;
  1109. enum sde_crtc_vm_req vm_req;
  1110. int rc = 0;
  1111. if (!sde_kms || !sde_vm_is_enabled(sde_kms))
  1112. return -EINVAL;
  1113. vm_ops = sde_vm_get_ops(sde_kms);
  1114. crtc = sde_kms_vm_get_vm_crtc(state);
  1115. if (!crtc)
  1116. return 0;
  1117. new_cstate = drm_atomic_get_new_crtc_state(state, crtc);
  1118. cstate = to_sde_crtc_state(new_cstate);
  1119. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  1120. if (vm_req != VM_REQ_RELEASE)
  1121. return 0;
  1122. /* handle SDE pre-release */
  1123. rc = sde_kms_vm_pre_release(sde_kms, state);
  1124. if (rc) {
  1125. SDE_ERROR("sde vm pre_release failed, rc=%d\n", rc);
  1126. goto exit;
  1127. }
  1128. /* properly handoff color processing features */
  1129. sde_cp_crtc_vm_primary_handoff(crtc);
  1130. /* handle non-SDE clients pre-release */
  1131. if (vm_ops->vm_client_pre_release) {
  1132. rc = vm_ops->vm_client_pre_release(sde_kms);
  1133. if (rc) {
  1134. SDE_ERROR("sde vm client pre_release failed, rc=%d\n",
  1135. rc);
  1136. goto exit;
  1137. }
  1138. }
  1139. sde_vm_lock(sde_kms);
  1140. /* release HW */
  1141. if (vm_ops->vm_release) {
  1142. rc = vm_ops->vm_release(sde_kms);
  1143. if (rc)
  1144. SDE_ERROR("sde vm assign failed, rc=%d\n", rc);
  1145. }
  1146. sde_vm_unlock(sde_kms);
  1147. exit:
  1148. return rc;
  1149. }
  1150. static void sde_kms_complete_commit(struct msm_kms *kms,
  1151. struct drm_atomic_state *old_state)
  1152. {
  1153. struct sde_kms *sde_kms;
  1154. struct msm_drm_private *priv;
  1155. struct drm_crtc *crtc;
  1156. struct drm_crtc_state *old_crtc_state;
  1157. struct drm_connector *connector;
  1158. struct drm_connector_state *old_conn_state;
  1159. struct msm_display_conn_params params;
  1160. struct sde_vm_ops *vm_ops;
  1161. int i, rc = 0;
  1162. if (!kms || !old_state)
  1163. return;
  1164. sde_kms = to_sde_kms(kms);
  1165. if (!sde_kms->dev || !sde_kms->dev->dev_private)
  1166. return;
  1167. priv = sde_kms->dev->dev_private;
  1168. if (!sde_kms_power_resource_is_enabled(sde_kms->dev)) {
  1169. SDE_ERROR("power resource is not enabled\n");
  1170. return;
  1171. }
  1172. SDE_ATRACE_BEGIN("sde_kms_complete_commit");
  1173. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  1174. sde_crtc_complete_commit(crtc, old_crtc_state);
  1175. /* complete secure transitions if any */
  1176. if (sde_kms->smmu_state.transition_type == POST_COMMIT)
  1177. _sde_kms_secure_ctrl(sde_kms, crtc, true);
  1178. }
  1179. for_each_old_connector_in_state(old_state, connector,
  1180. old_conn_state, i) {
  1181. struct sde_connector *c_conn;
  1182. c_conn = to_sde_connector(connector);
  1183. if (!c_conn->ops.post_kickoff)
  1184. continue;
  1185. memset(&params, 0, sizeof(params));
  1186. sde_connector_complete_qsync_commit(connector, &params);
  1187. rc = c_conn->ops.post_kickoff(connector, &params);
  1188. if (rc) {
  1189. pr_err("Connector Post kickoff failed rc=%d\n",
  1190. rc);
  1191. }
  1192. }
  1193. vm_ops = sde_vm_get_ops(sde_kms);
  1194. if (vm_ops && vm_ops->vm_post_commit) {
  1195. rc = vm_ops->vm_post_commit(sde_kms, old_state);
  1196. if (rc)
  1197. SDE_ERROR("vm post commit failed, rc = %d\n",
  1198. rc);
  1199. }
  1200. _sde_kms_drm_check_dpms(old_state, DRM_PANEL_EVENT_BLANK);
  1201. pm_runtime_put_sync(sde_kms->dev->dev);
  1202. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i)
  1203. _sde_kms_release_splash_resource(sde_kms, crtc);
  1204. SDE_EVT32_VERBOSE(SDE_EVTLOG_FUNC_EXIT);
  1205. SDE_ATRACE_END("sde_kms_complete_commit");
  1206. }
  1207. static void sde_kms_wait_for_commit_done(struct msm_kms *kms,
  1208. struct drm_crtc *crtc)
  1209. {
  1210. struct drm_encoder *encoder;
  1211. struct drm_device *dev;
  1212. int ret;
  1213. bool cwb_disabling;
  1214. if (!kms || !crtc || !crtc->state) {
  1215. SDE_ERROR("invalid params\n");
  1216. return;
  1217. }
  1218. dev = crtc->dev;
  1219. if (!crtc->state->enable) {
  1220. SDE_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
  1221. return;
  1222. }
  1223. if (!crtc->state->active) {
  1224. SDE_DEBUG("[crtc:%d] not active\n", crtc->base.id);
  1225. return;
  1226. }
  1227. if (!sde_kms_power_resource_is_enabled(crtc->dev)) {
  1228. SDE_ERROR("power resource is not enabled\n");
  1229. return;
  1230. }
  1231. SDE_ATRACE_BEGIN("sde_kms_wait_for_commit_done");
  1232. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  1233. cwb_disabling = false;
  1234. if (encoder->crtc != crtc) {
  1235. cwb_disabling = sde_encoder_is_cwb_disabling(encoder,
  1236. crtc);
  1237. if (!cwb_disabling)
  1238. continue;
  1239. }
  1240. /*
  1241. * Wait for post-flush if necessary to delay before
  1242. * plane_cleanup. For example, wait for vsync in case of video
  1243. * mode panels. This may be a no-op for command mode panels.
  1244. */
  1245. SDE_EVT32_VERBOSE(DRMID(crtc));
  1246. ret = sde_encoder_wait_for_event(encoder, MSM_ENC_COMMIT_DONE);
  1247. if (ret && ret != -EWOULDBLOCK) {
  1248. SDE_ERROR("wait for commit done returned %d\n", ret);
  1249. sde_crtc_request_frame_reset(crtc);
  1250. break;
  1251. }
  1252. sde_crtc_complete_flip(crtc, NULL);
  1253. if (cwb_disabling)
  1254. sde_encoder_virt_reset(encoder);
  1255. }
  1256. sde_crtc_static_cache_read_kickoff(crtc);
  1257. SDE_ATRACE_END("sde_ksm_wait_for_commit_done");
  1258. }
  1259. static void sde_kms_prepare_fence(struct msm_kms *kms,
  1260. struct drm_atomic_state *old_state)
  1261. {
  1262. struct drm_crtc *crtc;
  1263. struct drm_crtc_state *old_crtc_state;
  1264. int i, rc;
  1265. if (!kms || !old_state || !old_state->dev || !old_state->acquire_ctx) {
  1266. SDE_ERROR("invalid argument(s)\n");
  1267. return;
  1268. }
  1269. SDE_ATRACE_BEGIN("sde_kms_prepare_fence");
  1270. retry:
  1271. /* attempt to acquire ww mutex for connection */
  1272. rc = drm_modeset_lock(&old_state->dev->mode_config.connection_mutex,
  1273. old_state->acquire_ctx);
  1274. if (rc == -EDEADLK) {
  1275. drm_modeset_backoff(old_state->acquire_ctx);
  1276. goto retry;
  1277. }
  1278. /* old_state actually contains updated crtc pointers */
  1279. for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) {
  1280. if (crtc->state->active || crtc->state->active_changed)
  1281. sde_crtc_prepare_commit(crtc, old_crtc_state);
  1282. }
  1283. SDE_ATRACE_END("sde_kms_prepare_fence");
  1284. }
  1285. /**
  1286. * _sde_kms_get_displays - query for underlying display handles and cache them
  1287. * @sde_kms: Pointer to sde kms structure
  1288. * Returns: Zero on success
  1289. */
  1290. static int _sde_kms_get_displays(struct sde_kms *sde_kms)
  1291. {
  1292. int rc = -ENOMEM;
  1293. if (!sde_kms) {
  1294. SDE_ERROR("invalid sde kms\n");
  1295. return -EINVAL;
  1296. }
  1297. /* dsi */
  1298. sde_kms->dsi_displays = NULL;
  1299. sde_kms->dsi_display_count = dsi_display_get_num_of_displays();
  1300. if (sde_kms->dsi_display_count) {
  1301. sde_kms->dsi_displays = kcalloc(sde_kms->dsi_display_count,
  1302. sizeof(void *),
  1303. GFP_KERNEL);
  1304. if (!sde_kms->dsi_displays) {
  1305. SDE_ERROR("failed to allocate dsi displays\n");
  1306. goto exit_deinit_dsi;
  1307. }
  1308. sde_kms->dsi_display_count =
  1309. dsi_display_get_active_displays(sde_kms->dsi_displays,
  1310. sde_kms->dsi_display_count);
  1311. }
  1312. /* wb */
  1313. sde_kms->wb_displays = NULL;
  1314. sde_kms->wb_display_count = sde_wb_get_num_of_displays();
  1315. if (sde_kms->wb_display_count) {
  1316. sde_kms->wb_displays = kcalloc(sde_kms->wb_display_count,
  1317. sizeof(void *),
  1318. GFP_KERNEL);
  1319. if (!sde_kms->wb_displays) {
  1320. SDE_ERROR("failed to allocate wb displays\n");
  1321. goto exit_deinit_wb;
  1322. }
  1323. sde_kms->wb_display_count =
  1324. wb_display_get_displays(sde_kms->wb_displays,
  1325. sde_kms->wb_display_count);
  1326. }
  1327. /* dp */
  1328. sde_kms->dp_displays = NULL;
  1329. sde_kms->dp_display_count = dp_display_get_num_of_displays();
  1330. if (sde_kms->dp_display_count) {
  1331. sde_kms->dp_displays = kcalloc(sde_kms->dp_display_count,
  1332. sizeof(void *), GFP_KERNEL);
  1333. if (!sde_kms->dp_displays) {
  1334. SDE_ERROR("failed to allocate dp displays\n");
  1335. goto exit_deinit_dp;
  1336. }
  1337. sde_kms->dp_display_count =
  1338. dp_display_get_displays(sde_kms->dp_displays,
  1339. sde_kms->dp_display_count);
  1340. sde_kms->dp_stream_count = dp_display_get_num_of_streams();
  1341. }
  1342. return 0;
  1343. exit_deinit_dp:
  1344. kfree(sde_kms->dp_displays);
  1345. sde_kms->dp_stream_count = 0;
  1346. sde_kms->dp_display_count = 0;
  1347. sde_kms->dp_displays = NULL;
  1348. exit_deinit_wb:
  1349. kfree(sde_kms->wb_displays);
  1350. sde_kms->wb_display_count = 0;
  1351. sde_kms->wb_displays = NULL;
  1352. exit_deinit_dsi:
  1353. kfree(sde_kms->dsi_displays);
  1354. sde_kms->dsi_display_count = 0;
  1355. sde_kms->dsi_displays = NULL;
  1356. return rc;
  1357. }
  1358. /**
  1359. * _sde_kms_release_displays - release cache of underlying display handles
  1360. * @sde_kms: Pointer to sde kms structure
  1361. */
  1362. static void _sde_kms_release_displays(struct sde_kms *sde_kms)
  1363. {
  1364. if (!sde_kms) {
  1365. SDE_ERROR("invalid sde kms\n");
  1366. return;
  1367. }
  1368. kfree(sde_kms->wb_displays);
  1369. sde_kms->wb_displays = NULL;
  1370. sde_kms->wb_display_count = 0;
  1371. kfree(sde_kms->dsi_displays);
  1372. sde_kms->dsi_displays = NULL;
  1373. sde_kms->dsi_display_count = 0;
  1374. }
  1375. /**
  1376. * _sde_kms_setup_displays - create encoders, bridges and connectors
  1377. * for underlying displays
  1378. * @dev: Pointer to drm device structure
  1379. * @priv: Pointer to private drm device data
  1380. * @sde_kms: Pointer to sde kms structure
  1381. * Returns: Zero on success
  1382. */
  1383. static int _sde_kms_setup_displays(struct drm_device *dev,
  1384. struct msm_drm_private *priv,
  1385. struct sde_kms *sde_kms)
  1386. {
  1387. static const struct sde_connector_ops dsi_ops = {
  1388. .set_info_blob = dsi_conn_set_info_blob,
  1389. .detect = dsi_conn_detect,
  1390. .get_modes = dsi_connector_get_modes,
  1391. .pre_destroy = dsi_connector_put_modes,
  1392. .mode_valid = dsi_conn_mode_valid,
  1393. .get_info = dsi_display_get_info,
  1394. .set_backlight = dsi_display_set_backlight,
  1395. .soft_reset = dsi_display_soft_reset,
  1396. .pre_kickoff = dsi_conn_pre_kickoff,
  1397. .clk_ctrl = dsi_display_clk_ctrl,
  1398. .set_power = dsi_display_set_power,
  1399. .get_mode_info = dsi_conn_get_mode_info,
  1400. .get_dst_format = dsi_display_get_dst_format,
  1401. .post_kickoff = dsi_conn_post_kickoff,
  1402. .check_status = dsi_display_check_status,
  1403. .enable_event = dsi_conn_enable_event,
  1404. .cmd_transfer = dsi_display_cmd_transfer,
  1405. .cont_splash_config = dsi_display_cont_splash_config,
  1406. .cont_splash_res_disable = dsi_display_cont_splash_res_disable,
  1407. .get_panel_vfp = dsi_display_get_panel_vfp,
  1408. .get_default_lms = dsi_display_get_default_lms,
  1409. .cmd_receive = dsi_display_cmd_receive,
  1410. .install_properties = NULL,
  1411. .set_allowed_mode_switch = dsi_conn_set_allowed_mode_switch,
  1412. .get_qsync_min_fps = dsi_display_get_qsync_min_fps,
  1413. .prepare_commit = dsi_conn_prepare_commit,
  1414. };
  1415. static const struct sde_connector_ops wb_ops = {
  1416. .post_init = sde_wb_connector_post_init,
  1417. .set_info_blob = sde_wb_connector_set_info_blob,
  1418. .detect = sde_wb_connector_detect,
  1419. .get_modes = sde_wb_connector_get_modes,
  1420. .set_property = sde_wb_connector_set_property,
  1421. .get_info = sde_wb_get_info,
  1422. .soft_reset = NULL,
  1423. .get_mode_info = sde_wb_get_mode_info,
  1424. .get_dst_format = NULL,
  1425. .check_status = NULL,
  1426. .cmd_transfer = NULL,
  1427. .cont_splash_config = NULL,
  1428. .cont_splash_res_disable = NULL,
  1429. .get_panel_vfp = NULL,
  1430. .cmd_receive = NULL,
  1431. .install_properties = NULL,
  1432. .set_allowed_mode_switch = NULL,
  1433. };
  1434. static const struct sde_connector_ops dp_ops = {
  1435. .post_init = dp_connector_post_init,
  1436. .detect = dp_connector_detect,
  1437. .get_modes = dp_connector_get_modes,
  1438. .atomic_check = dp_connector_atomic_check,
  1439. .mode_valid = dp_connector_mode_valid,
  1440. .get_info = dp_connector_get_info,
  1441. .get_mode_info = dp_connector_get_mode_info,
  1442. .post_open = dp_connector_post_open,
  1443. .check_status = NULL,
  1444. .set_colorspace = dp_connector_set_colorspace,
  1445. .config_hdr = dp_connector_config_hdr,
  1446. .cmd_transfer = NULL,
  1447. .cont_splash_config = NULL,
  1448. .cont_splash_res_disable = NULL,
  1449. .get_panel_vfp = NULL,
  1450. .update_pps = dp_connector_update_pps,
  1451. .cmd_receive = NULL,
  1452. .install_properties = dp_connector_install_properties,
  1453. .set_allowed_mode_switch = NULL,
  1454. };
  1455. struct msm_display_info info;
  1456. struct drm_encoder *encoder;
  1457. void *display, *connector;
  1458. int i, max_encoders;
  1459. int rc = 0;
  1460. u32 dsc_count = 0, mixer_count = 0;
  1461. u32 max_dp_dsc_count, max_dp_mixer_count;
  1462. if (!dev || !priv || !sde_kms) {
  1463. SDE_ERROR("invalid argument(s)\n");
  1464. return -EINVAL;
  1465. }
  1466. max_encoders = sde_kms->dsi_display_count + sde_kms->wb_display_count +
  1467. sde_kms->dp_display_count +
  1468. sde_kms->dp_stream_count;
  1469. if (max_encoders > ARRAY_SIZE(priv->encoders)) {
  1470. max_encoders = ARRAY_SIZE(priv->encoders);
  1471. SDE_ERROR("capping number of displays to %d", max_encoders);
  1472. }
  1473. /* wb */
  1474. for (i = 0; i < sde_kms->wb_display_count &&
  1475. priv->num_encoders < max_encoders; ++i) {
  1476. display = sde_kms->wb_displays[i];
  1477. encoder = NULL;
  1478. memset(&info, 0x0, sizeof(info));
  1479. rc = sde_wb_get_info(NULL, &info, display);
  1480. if (rc) {
  1481. SDE_ERROR("wb get_info %d failed\n", i);
  1482. continue;
  1483. }
  1484. encoder = sde_encoder_init(dev, &info);
  1485. if (IS_ERR_OR_NULL(encoder)) {
  1486. SDE_ERROR("encoder init failed for wb %d\n", i);
  1487. continue;
  1488. }
  1489. rc = sde_wb_drm_init(display, encoder);
  1490. if (rc) {
  1491. SDE_ERROR("wb bridge %d init failed, %d\n", i, rc);
  1492. sde_encoder_destroy(encoder);
  1493. continue;
  1494. }
  1495. connector = sde_connector_init(dev,
  1496. encoder,
  1497. 0,
  1498. display,
  1499. &wb_ops,
  1500. DRM_CONNECTOR_POLL_HPD,
  1501. DRM_MODE_CONNECTOR_VIRTUAL);
  1502. if (connector) {
  1503. priv->encoders[priv->num_encoders++] = encoder;
  1504. priv->connectors[priv->num_connectors++] = connector;
  1505. } else {
  1506. SDE_ERROR("wb %d connector init failed\n", i);
  1507. sde_wb_drm_deinit(display);
  1508. sde_encoder_destroy(encoder);
  1509. }
  1510. }
  1511. /* dsi */
  1512. for (i = 0; i < sde_kms->dsi_display_count &&
  1513. priv->num_encoders < max_encoders; ++i) {
  1514. display = sde_kms->dsi_displays[i];
  1515. encoder = NULL;
  1516. memset(&info, 0x0, sizeof(info));
  1517. rc = dsi_display_get_info(NULL, &info, display);
  1518. if (rc) {
  1519. SDE_ERROR("dsi get_info %d failed\n", i);
  1520. continue;
  1521. }
  1522. encoder = sde_encoder_init(dev, &info);
  1523. if (IS_ERR_OR_NULL(encoder)) {
  1524. SDE_ERROR("encoder init failed for dsi %d\n", i);
  1525. continue;
  1526. }
  1527. rc = dsi_display_drm_bridge_init(display, encoder);
  1528. if (rc) {
  1529. SDE_ERROR("dsi bridge %d init failed, %d\n", i, rc);
  1530. sde_encoder_destroy(encoder);
  1531. continue;
  1532. }
  1533. connector = sde_connector_init(dev,
  1534. encoder,
  1535. dsi_display_get_drm_panel(display),
  1536. display,
  1537. &dsi_ops,
  1538. DRM_CONNECTOR_POLL_HPD,
  1539. DRM_MODE_CONNECTOR_DSI);
  1540. if (connector) {
  1541. priv->encoders[priv->num_encoders++] = encoder;
  1542. priv->connectors[priv->num_connectors++] = connector;
  1543. } else {
  1544. SDE_ERROR("dsi %d connector init failed\n", i);
  1545. dsi_display_drm_bridge_deinit(display);
  1546. sde_encoder_destroy(encoder);
  1547. continue;
  1548. }
  1549. rc = dsi_display_drm_ext_bridge_init(display,
  1550. encoder, connector);
  1551. if (rc) {
  1552. SDE_ERROR("dsi %d ext bridge init failed\n", rc);
  1553. dsi_display_drm_bridge_deinit(display);
  1554. sde_connector_destroy(connector);
  1555. sde_encoder_destroy(encoder);
  1556. }
  1557. dsc_count += info.dsc_count;
  1558. mixer_count += info.lm_count;
  1559. }
  1560. max_dp_mixer_count = sde_kms->catalog->mixer_count > mixer_count ?
  1561. sde_kms->catalog->mixer_count - mixer_count : 0;
  1562. max_dp_dsc_count = sde_kms->catalog->dsc_count > dsc_count ?
  1563. sde_kms->catalog->dsc_count - dsc_count : 0;
  1564. /* dp */
  1565. for (i = 0; i < sde_kms->dp_display_count &&
  1566. priv->num_encoders < max_encoders; ++i) {
  1567. int idx;
  1568. display = sde_kms->dp_displays[i];
  1569. encoder = NULL;
  1570. memset(&info, 0x0, sizeof(info));
  1571. rc = dp_connector_get_info(NULL, &info, display);
  1572. if (rc) {
  1573. SDE_ERROR("dp get_info %d failed\n", i);
  1574. continue;
  1575. }
  1576. encoder = sde_encoder_init(dev, &info);
  1577. if (IS_ERR_OR_NULL(encoder)) {
  1578. SDE_ERROR("dp encoder init failed %d\n", i);
  1579. continue;
  1580. }
  1581. rc = dp_drm_bridge_init(display, encoder,
  1582. max_dp_mixer_count, max_dp_dsc_count);
  1583. if (rc) {
  1584. SDE_ERROR("dp bridge %d init failed, %d\n", i, rc);
  1585. sde_encoder_destroy(encoder);
  1586. continue;
  1587. }
  1588. connector = sde_connector_init(dev,
  1589. encoder,
  1590. NULL,
  1591. display,
  1592. &dp_ops,
  1593. DRM_CONNECTOR_POLL_HPD,
  1594. DRM_MODE_CONNECTOR_DisplayPort);
  1595. if (connector) {
  1596. priv->encoders[priv->num_encoders++] = encoder;
  1597. priv->connectors[priv->num_connectors++] = connector;
  1598. } else {
  1599. SDE_ERROR("dp %d connector init failed\n", i);
  1600. dp_drm_bridge_deinit(display);
  1601. sde_encoder_destroy(encoder);
  1602. }
  1603. /* update display cap to MST_MODE for DP MST encoders */
  1604. info.capabilities |= MSM_DISPLAY_CAP_MST_MODE;
  1605. for (idx = 0; idx < sde_kms->dp_stream_count &&
  1606. priv->num_encoders < max_encoders; idx++) {
  1607. info.h_tile_instance[0] = idx;
  1608. encoder = sde_encoder_init(dev, &info);
  1609. if (IS_ERR_OR_NULL(encoder)) {
  1610. SDE_ERROR("dp mst encoder init failed %d\n", i);
  1611. continue;
  1612. }
  1613. rc = dp_mst_drm_bridge_init(display, encoder);
  1614. if (rc) {
  1615. SDE_ERROR("dp mst bridge %d init failed, %d\n",
  1616. i, rc);
  1617. sde_encoder_destroy(encoder);
  1618. continue;
  1619. }
  1620. priv->encoders[priv->num_encoders++] = encoder;
  1621. }
  1622. }
  1623. return 0;
  1624. }
  1625. static void _sde_kms_drm_obj_destroy(struct sde_kms *sde_kms)
  1626. {
  1627. struct msm_drm_private *priv;
  1628. int i;
  1629. if (!sde_kms) {
  1630. SDE_ERROR("invalid sde_kms\n");
  1631. return;
  1632. } else if (!sde_kms->dev) {
  1633. SDE_ERROR("invalid dev\n");
  1634. return;
  1635. } else if (!sde_kms->dev->dev_private) {
  1636. SDE_ERROR("invalid dev_private\n");
  1637. return;
  1638. }
  1639. priv = sde_kms->dev->dev_private;
  1640. for (i = 0; i < priv->num_crtcs; i++)
  1641. priv->crtcs[i]->funcs->destroy(priv->crtcs[i]);
  1642. priv->num_crtcs = 0;
  1643. for (i = 0; i < priv->num_planes; i++)
  1644. priv->planes[i]->funcs->destroy(priv->planes[i]);
  1645. priv->num_planes = 0;
  1646. for (i = 0; i < priv->num_connectors; i++)
  1647. priv->connectors[i]->funcs->destroy(priv->connectors[i]);
  1648. priv->num_connectors = 0;
  1649. for (i = 0; i < priv->num_encoders; i++)
  1650. priv->encoders[i]->funcs->destroy(priv->encoders[i]);
  1651. priv->num_encoders = 0;
  1652. _sde_kms_release_displays(sde_kms);
  1653. }
  1654. static int _sde_kms_drm_obj_init(struct sde_kms *sde_kms)
  1655. {
  1656. struct drm_device *dev;
  1657. struct drm_plane *primary_planes[MAX_PLANES], *plane;
  1658. struct drm_crtc *crtc;
  1659. struct msm_drm_private *priv;
  1660. struct sde_mdss_cfg *catalog;
  1661. int primary_planes_idx = 0, i, ret;
  1662. int max_crtc_count;
  1663. u32 sspp_id[MAX_PLANES];
  1664. u32 master_plane_id[MAX_PLANES];
  1665. u32 num_virt_planes = 0;
  1666. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  1667. SDE_ERROR("invalid sde_kms\n");
  1668. return -EINVAL;
  1669. }
  1670. dev = sde_kms->dev;
  1671. priv = dev->dev_private;
  1672. catalog = sde_kms->catalog;
  1673. ret = sde_core_irq_domain_add(sde_kms);
  1674. if (ret)
  1675. goto fail_irq;
  1676. /*
  1677. * Query for underlying display drivers, and create connectors,
  1678. * bridges and encoders for them.
  1679. */
  1680. if (!_sde_kms_get_displays(sde_kms))
  1681. (void)_sde_kms_setup_displays(dev, priv, sde_kms);
  1682. max_crtc_count = min(catalog->mixer_count, priv->num_encoders);
  1683. /* Create the planes */
  1684. for (i = 0; i < catalog->sspp_count; i++) {
  1685. bool primary = true;
  1686. if (catalog->sspp[i].features & BIT(SDE_SSPP_CURSOR)
  1687. || primary_planes_idx >= max_crtc_count)
  1688. primary = false;
  1689. plane = sde_plane_init(dev, catalog->sspp[i].id, primary,
  1690. (1UL << max_crtc_count) - 1, 0);
  1691. if (IS_ERR(plane)) {
  1692. SDE_ERROR("sde_plane_init failed\n");
  1693. ret = PTR_ERR(plane);
  1694. goto fail;
  1695. }
  1696. priv->planes[priv->num_planes++] = plane;
  1697. if (primary)
  1698. primary_planes[primary_planes_idx++] = plane;
  1699. if (sde_hw_sspp_multirect_enabled(&catalog->sspp[i]) &&
  1700. sde_is_custom_client()) {
  1701. int priority =
  1702. catalog->sspp[i].sblk->smart_dma_priority;
  1703. sspp_id[priority - 1] = catalog->sspp[i].id;
  1704. master_plane_id[priority - 1] = plane->base.id;
  1705. num_virt_planes++;
  1706. }
  1707. }
  1708. /* Initialize smart DMA virtual planes */
  1709. for (i = 0; i < num_virt_planes; i++) {
  1710. plane = sde_plane_init(dev, sspp_id[i], false,
  1711. (1UL << max_crtc_count) - 1, master_plane_id[i]);
  1712. if (IS_ERR(plane)) {
  1713. SDE_ERROR("sde_plane for virtual SSPP init failed\n");
  1714. ret = PTR_ERR(plane);
  1715. goto fail;
  1716. }
  1717. priv->planes[priv->num_planes++] = plane;
  1718. }
  1719. max_crtc_count = min(max_crtc_count, primary_planes_idx);
  1720. /* Create one CRTC per encoder */
  1721. for (i = 0; i < max_crtc_count; i++) {
  1722. crtc = sde_crtc_init(dev, primary_planes[i]);
  1723. if (IS_ERR(crtc)) {
  1724. ret = PTR_ERR(crtc);
  1725. goto fail;
  1726. }
  1727. priv->crtcs[priv->num_crtcs++] = crtc;
  1728. }
  1729. if (sde_is_custom_client()) {
  1730. /* All CRTCs are compatible with all planes */
  1731. for (i = 0; i < priv->num_planes; i++)
  1732. priv->planes[i]->possible_crtcs =
  1733. (1 << priv->num_crtcs) - 1;
  1734. }
  1735. /* All CRTCs are compatible with all encoders */
  1736. for (i = 0; i < priv->num_encoders; i++)
  1737. priv->encoders[i]->possible_crtcs = (1 << priv->num_crtcs) - 1;
  1738. return 0;
  1739. fail:
  1740. _sde_kms_drm_obj_destroy(sde_kms);
  1741. fail_irq:
  1742. sde_core_irq_domain_fini(sde_kms);
  1743. return ret;
  1744. }
  1745. /**
  1746. * sde_kms_timeline_status - provides current timeline status
  1747. * This API should be called without mode config lock.
  1748. * @dev: Pointer to drm device
  1749. */
  1750. void sde_kms_timeline_status(struct drm_device *dev)
  1751. {
  1752. struct drm_crtc *crtc;
  1753. struct drm_connector *conn;
  1754. struct drm_connector_list_iter conn_iter;
  1755. if (!dev) {
  1756. SDE_ERROR("invalid drm device node\n");
  1757. return;
  1758. }
  1759. drm_for_each_crtc(crtc, dev)
  1760. sde_crtc_timeline_status(crtc);
  1761. if (mutex_is_locked(&dev->mode_config.mutex)) {
  1762. /*
  1763. *Probably locked from last close dumping status anyway
  1764. */
  1765. SDE_ERROR("dumping conn_timeline without mode_config lock\n");
  1766. drm_connector_list_iter_begin(dev, &conn_iter);
  1767. drm_for_each_connector_iter(conn, &conn_iter)
  1768. sde_conn_timeline_status(conn);
  1769. drm_connector_list_iter_end(&conn_iter);
  1770. return;
  1771. }
  1772. mutex_lock(&dev->mode_config.mutex);
  1773. drm_connector_list_iter_begin(dev, &conn_iter);
  1774. drm_for_each_connector_iter(conn, &conn_iter)
  1775. sde_conn_timeline_status(conn);
  1776. drm_connector_list_iter_end(&conn_iter);
  1777. mutex_unlock(&dev->mode_config.mutex);
  1778. }
  1779. static int sde_kms_postinit(struct msm_kms *kms)
  1780. {
  1781. struct sde_kms *sde_kms = to_sde_kms(kms);
  1782. struct drm_device *dev;
  1783. struct drm_crtc *crtc;
  1784. int rc;
  1785. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  1786. SDE_ERROR("invalid sde_kms\n");
  1787. return -EINVAL;
  1788. }
  1789. dev = sde_kms->dev;
  1790. rc = _sde_debugfs_init(sde_kms);
  1791. if (rc)
  1792. SDE_ERROR("sde_debugfs init failed: %d\n", rc);
  1793. drm_for_each_crtc(crtc, dev)
  1794. sde_crtc_post_init(dev, crtc);
  1795. return rc;
  1796. }
  1797. static long sde_kms_round_pixclk(struct msm_kms *kms, unsigned long rate,
  1798. struct drm_encoder *encoder)
  1799. {
  1800. return rate;
  1801. }
  1802. static void _sde_kms_hw_destroy(struct sde_kms *sde_kms,
  1803. struct platform_device *pdev)
  1804. {
  1805. struct drm_device *dev;
  1806. struct msm_drm_private *priv;
  1807. struct sde_vm_ops *vm_ops;
  1808. int i;
  1809. if (!sde_kms || !pdev)
  1810. return;
  1811. dev = sde_kms->dev;
  1812. if (!dev)
  1813. return;
  1814. priv = dev->dev_private;
  1815. if (!priv)
  1816. return;
  1817. if (sde_kms->genpd_init) {
  1818. sde_kms->genpd_init = false;
  1819. pm_genpd_remove(&sde_kms->genpd);
  1820. of_genpd_del_provider(pdev->dev.of_node);
  1821. }
  1822. vm_ops = sde_vm_get_ops(sde_kms);
  1823. if (vm_ops && vm_ops->vm_deinit)
  1824. vm_ops->vm_deinit(sde_kms, vm_ops);
  1825. if (sde_kms->hw_intr)
  1826. sde_hw_intr_destroy(sde_kms->hw_intr);
  1827. sde_kms->hw_intr = NULL;
  1828. if (sde_kms->power_event)
  1829. sde_power_handle_unregister_event(
  1830. &priv->phandle, sde_kms->power_event);
  1831. _sde_kms_release_displays(sde_kms);
  1832. _sde_kms_unmap_all_splash_regions(sde_kms);
  1833. if (sde_kms->catalog) {
  1834. for (i = 0; i < sde_kms->catalog->vbif_count; i++) {
  1835. u32 vbif_idx = sde_kms->catalog->vbif[i].id;
  1836. if ((vbif_idx < VBIF_MAX) && sde_kms->hw_vbif[vbif_idx])
  1837. sde_hw_vbif_destroy(sde_kms->hw_vbif[vbif_idx]);
  1838. }
  1839. }
  1840. if (sde_kms->rm_init)
  1841. sde_rm_destroy(&sde_kms->rm);
  1842. sde_kms->rm_init = false;
  1843. if (sde_kms->catalog)
  1844. sde_hw_catalog_deinit(sde_kms->catalog);
  1845. sde_kms->catalog = NULL;
  1846. if (sde_kms->sid)
  1847. msm_iounmap(pdev, sde_kms->sid);
  1848. sde_kms->sid = NULL;
  1849. if (sde_kms->reg_dma)
  1850. msm_iounmap(pdev, sde_kms->reg_dma);
  1851. sde_kms->reg_dma = NULL;
  1852. if (sde_kms->vbif[VBIF_NRT])
  1853. msm_iounmap(pdev, sde_kms->vbif[VBIF_NRT]);
  1854. sde_kms->vbif[VBIF_NRT] = NULL;
  1855. if (sde_kms->vbif[VBIF_RT])
  1856. msm_iounmap(pdev, sde_kms->vbif[VBIF_RT]);
  1857. sde_kms->vbif[VBIF_RT] = NULL;
  1858. if (sde_kms->mmio)
  1859. msm_iounmap(pdev, sde_kms->mmio);
  1860. sde_kms->mmio = NULL;
  1861. sde_reg_dma_deinit();
  1862. _sde_kms_mmu_destroy(sde_kms);
  1863. }
  1864. int sde_kms_mmu_detach(struct sde_kms *sde_kms, bool secure_only)
  1865. {
  1866. int i;
  1867. if (!sde_kms)
  1868. return -EINVAL;
  1869. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  1870. struct msm_mmu *mmu;
  1871. struct msm_gem_address_space *aspace = sde_kms->aspace[i];
  1872. if (!aspace)
  1873. continue;
  1874. mmu = sde_kms->aspace[i]->mmu;
  1875. if (secure_only &&
  1876. !aspace->mmu->funcs->is_domain_secure(mmu))
  1877. continue;
  1878. /* cleanup aspace before detaching */
  1879. msm_gem_aspace_domain_attach_detach_update(aspace, true);
  1880. SDE_DEBUG("Detaching domain:%d\n", i);
  1881. aspace->mmu->funcs->detach(mmu, (const char **)iommu_ports,
  1882. ARRAY_SIZE(iommu_ports));
  1883. aspace->domain_attached = false;
  1884. }
  1885. return 0;
  1886. }
  1887. int sde_kms_mmu_attach(struct sde_kms *sde_kms, bool secure_only)
  1888. {
  1889. int i;
  1890. if (!sde_kms)
  1891. return -EINVAL;
  1892. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  1893. struct msm_mmu *mmu;
  1894. struct msm_gem_address_space *aspace = sde_kms->aspace[i];
  1895. if (!aspace)
  1896. continue;
  1897. mmu = sde_kms->aspace[i]->mmu;
  1898. if (secure_only &&
  1899. !aspace->mmu->funcs->is_domain_secure(mmu))
  1900. continue;
  1901. SDE_DEBUG("Attaching domain:%d\n", i);
  1902. aspace->mmu->funcs->attach(mmu, (const char **)iommu_ports,
  1903. ARRAY_SIZE(iommu_ports));
  1904. aspace->domain_attached = true;
  1905. msm_gem_aspace_domain_attach_detach_update(aspace, false);
  1906. }
  1907. return 0;
  1908. }
  1909. static void sde_kms_destroy(struct msm_kms *kms)
  1910. {
  1911. struct sde_kms *sde_kms;
  1912. struct drm_device *dev;
  1913. if (!kms) {
  1914. SDE_ERROR("invalid kms\n");
  1915. return;
  1916. }
  1917. sde_kms = to_sde_kms(kms);
  1918. dev = sde_kms->dev;
  1919. if (!dev || !dev->dev) {
  1920. SDE_ERROR("invalid device\n");
  1921. return;
  1922. }
  1923. _sde_kms_hw_destroy(sde_kms, to_platform_device(dev->dev));
  1924. kfree(sde_kms);
  1925. }
  1926. static int _sde_kms_helper_reset_custom_properties(struct sde_kms *sde_kms,
  1927. struct drm_atomic_state *state)
  1928. {
  1929. struct drm_device *dev = sde_kms->dev;
  1930. struct drm_plane *plane;
  1931. struct drm_plane_state *plane_state;
  1932. struct drm_crtc *crtc;
  1933. struct drm_crtc_state *crtc_state;
  1934. struct drm_connector *conn;
  1935. struct drm_connector_state *conn_state;
  1936. struct drm_connector_list_iter conn_iter;
  1937. int ret = 0;
  1938. drm_for_each_plane(plane, dev) {
  1939. plane_state = drm_atomic_get_plane_state(state, plane);
  1940. if (IS_ERR(plane_state)) {
  1941. ret = PTR_ERR(plane_state);
  1942. SDE_ERROR("error %d getting plane %d state\n",
  1943. ret, DRMID(plane));
  1944. return ret;
  1945. }
  1946. ret = sde_plane_helper_reset_custom_properties(plane,
  1947. plane_state);
  1948. if (ret) {
  1949. SDE_ERROR("error %d resetting plane props %d\n",
  1950. ret, DRMID(plane));
  1951. return ret;
  1952. }
  1953. }
  1954. drm_for_each_crtc(crtc, dev) {
  1955. crtc_state = drm_atomic_get_crtc_state(state, crtc);
  1956. if (IS_ERR(crtc_state)) {
  1957. ret = PTR_ERR(crtc_state);
  1958. SDE_ERROR("error %d getting crtc %d state\n",
  1959. ret, DRMID(crtc));
  1960. return ret;
  1961. }
  1962. ret = sde_crtc_helper_reset_custom_properties(crtc, crtc_state);
  1963. if (ret) {
  1964. SDE_ERROR("error %d resetting crtc props %d\n",
  1965. ret, DRMID(crtc));
  1966. return ret;
  1967. }
  1968. }
  1969. drm_connector_list_iter_begin(dev, &conn_iter);
  1970. drm_for_each_connector_iter(conn, &conn_iter) {
  1971. conn_state = drm_atomic_get_connector_state(state, conn);
  1972. if (IS_ERR(conn_state)) {
  1973. ret = PTR_ERR(conn_state);
  1974. SDE_ERROR("error %d getting connector %d state\n",
  1975. ret, DRMID(conn));
  1976. return ret;
  1977. }
  1978. ret = sde_connector_helper_reset_custom_properties(conn,
  1979. conn_state);
  1980. if (ret) {
  1981. SDE_ERROR("error %d resetting connector props %d\n",
  1982. ret, DRMID(conn));
  1983. return ret;
  1984. }
  1985. }
  1986. drm_connector_list_iter_end(&conn_iter);
  1987. return ret;
  1988. }
  1989. static void sde_kms_lastclose(struct msm_kms *kms)
  1990. {
  1991. struct sde_kms *sde_kms;
  1992. struct drm_device *dev;
  1993. struct drm_atomic_state *state;
  1994. struct drm_modeset_acquire_ctx ctx;
  1995. int ret;
  1996. if (!kms) {
  1997. SDE_ERROR("invalid argument\n");
  1998. return;
  1999. }
  2000. sde_kms = to_sde_kms(kms);
  2001. dev = sde_kms->dev;
  2002. drm_modeset_acquire_init(&ctx, 0);
  2003. state = drm_atomic_state_alloc(dev);
  2004. if (!state) {
  2005. ret = -ENOMEM;
  2006. goto out_ctx;
  2007. }
  2008. state->acquire_ctx = &ctx;
  2009. SDE_EVT32(SDE_EVTLOG_FUNC_ENTRY);
  2010. retry:
  2011. ret = drm_modeset_lock_all_ctx(dev, &ctx);
  2012. if (ret)
  2013. goto out_state;
  2014. ret = _sde_kms_helper_reset_custom_properties(sde_kms, state);
  2015. if (ret)
  2016. goto out_state;
  2017. ret = drm_atomic_commit(state);
  2018. out_state:
  2019. if (ret == -EDEADLK)
  2020. goto backoff;
  2021. drm_atomic_state_put(state);
  2022. out_ctx:
  2023. drm_modeset_drop_locks(&ctx);
  2024. drm_modeset_acquire_fini(&ctx);
  2025. if (ret)
  2026. SDE_ERROR("kms lastclose failed: %d\n", ret);
  2027. SDE_EVT32(ret, SDE_EVTLOG_FUNC_EXIT);
  2028. return;
  2029. backoff:
  2030. drm_atomic_state_clear(state);
  2031. drm_modeset_backoff(&ctx);
  2032. SDE_EVT32(ret, SDE_EVTLOG_FUNC_CASE1);
  2033. goto retry;
  2034. }
  2035. static int sde_kms_check_vm_request(struct msm_kms *kms,
  2036. struct drm_atomic_state *state)
  2037. {
  2038. struct sde_kms *sde_kms;
  2039. struct drm_device *dev;
  2040. struct drm_crtc *crtc;
  2041. struct drm_encoder *encoder;
  2042. struct drm_crtc_state *new_cstate, *old_cstate, *active_cstate;
  2043. uint32_t i, commit_crtc_cnt = 0, global_crtc_cnt = 0;
  2044. uint32_t crtc_encoder_cnt = 0;
  2045. struct drm_crtc *active_crtc = NULL, *global_active_crtc = NULL;
  2046. enum sde_crtc_vm_req old_vm_req = VM_REQ_NONE, new_vm_req = VM_REQ_NONE;
  2047. struct sde_vm_ops *vm_ops;
  2048. bool vm_req_active = false;
  2049. enum sde_crtc_idle_pc_state idle_pc_state;
  2050. struct sde_mdss_cfg *catalog;
  2051. int rc = 0;
  2052. struct sde_connector *sde_conn;
  2053. struct dsi_display *dsi_display;
  2054. struct drm_connector *connector;
  2055. struct drm_connector_state *new_connstate;
  2056. if (!kms || !state)
  2057. return -EINVAL;
  2058. sde_kms = to_sde_kms(kms);
  2059. dev = sde_kms->dev;
  2060. catalog = sde_kms->catalog;
  2061. vm_ops = sde_vm_get_ops(sde_kms);
  2062. if (!vm_ops)
  2063. return 0;
  2064. if (!vm_ops->vm_request_valid || !vm_ops->vm_owns_hw ||
  2065. !vm_ops->vm_acquire)
  2066. return -EINVAL;
  2067. sde_vm_lock(sde_kms);
  2068. for_each_oldnew_crtc_in_state(state, crtc, old_cstate, new_cstate, i) {
  2069. struct sde_crtc_state *old_state = NULL, *new_state = NULL;
  2070. if (!new_cstate->active && !old_cstate->active)
  2071. continue;
  2072. new_state = to_sde_crtc_state(new_cstate);
  2073. new_vm_req = sde_crtc_get_property(new_state,
  2074. CRTC_PROP_VM_REQ_STATE);
  2075. old_state = to_sde_crtc_state(old_cstate);
  2076. old_vm_req = sde_crtc_get_property(old_state,
  2077. CRTC_PROP_VM_REQ_STATE);
  2078. /*
  2079. * No active request if the transition is from
  2080. * VM_REQ_NONE to VM_REQ_NONE
  2081. */
  2082. if (old_vm_req || new_vm_req) {
  2083. rc = vm_ops->vm_request_valid(sde_kms,
  2084. old_vm_req, new_vm_req);
  2085. if (rc) {
  2086. SDE_ERROR(
  2087. "VM transition check failed; o_state:%d, n_state:%d, hw_owner:%d, rc:%d\n",
  2088. old_vm_req, new_vm_req,
  2089. vm_ops->vm_owns_hw(sde_kms), rc);
  2090. goto end;
  2091. } else if (old_vm_req == VM_REQ_ACQUIRE &&
  2092. new_vm_req == VM_REQ_NONE) {
  2093. SDE_DEBUG(
  2094. "VM transition valid; ignore further checks\n");
  2095. } else {
  2096. vm_req_active = true;
  2097. }
  2098. }
  2099. idle_pc_state = sde_crtc_get_property(new_state,
  2100. CRTC_PROP_IDLE_PC_STATE);
  2101. active_crtc = crtc;
  2102. active_cstate = new_cstate;
  2103. commit_crtc_cnt++;
  2104. }
  2105. /* return early if no active vm request */
  2106. if (!vm_req_active)
  2107. goto end;
  2108. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  2109. if (!crtc->state->active)
  2110. continue;
  2111. global_crtc_cnt++;
  2112. global_active_crtc = crtc;
  2113. }
  2114. if (active_crtc) {
  2115. drm_for_each_encoder_mask(encoder, active_crtc->dev,
  2116. active_cstate->encoder_mask)
  2117. crtc_encoder_cnt++;
  2118. }
  2119. SDE_EVT32(old_vm_req, new_vm_req, vm_ops->vm_owns_hw(sde_kms));
  2120. SDE_DEBUG("VM o_state:%d, n_state:%d, hw_owner:%d\n", old_vm_req,
  2121. new_vm_req, vm_ops->vm_owns_hw(sde_kms));
  2122. for_each_new_connector_in_state(state, connector, new_connstate, i) {
  2123. int conn_mask = active_cstate->connector_mask;
  2124. if (drm_connector_mask(connector) & conn_mask) {
  2125. sde_conn = to_sde_connector(connector);
  2126. dsi_display = (struct dsi_display *) sde_conn->display;
  2127. SDE_EVT32(DRMID(connector), DRMID(active_crtc), i,
  2128. dsi_display->type,
  2129. dsi_display->trusted_vm_env);
  2130. SDE_DEBUG(
  2131. "VM display:%s, conn:%d, crtc:%d, type:%d, tvm:%d,",
  2132. dsi_display->name, DRMID(connector),
  2133. DRMID(active_crtc), dsi_display->type,
  2134. dsi_display->trusted_vm_env);
  2135. break;
  2136. }
  2137. }
  2138. /* Check for single crtc commits only on valid VM requests */
  2139. if (active_crtc && global_active_crtc &&
  2140. (commit_crtc_cnt > catalog->max_trusted_vm_displays ||
  2141. global_crtc_cnt > catalog->max_trusted_vm_displays ||
  2142. active_crtc != global_active_crtc)) {
  2143. SDE_ERROR(
  2144. "VM switch failed; MAX:%d a_cnt:%d g_cnt:%d a_crtc:%d g_crtc:%d\n",
  2145. catalog->max_trusted_vm_displays,
  2146. commit_crtc_cnt, global_crtc_cnt, DRMID(active_crtc),
  2147. DRMID(global_active_crtc));
  2148. rc = -E2BIG;
  2149. goto end;
  2150. } else if ((new_vm_req == VM_REQ_RELEASE) &&
  2151. ((idle_pc_state == IDLE_PC_ENABLE) ||
  2152. (crtc_encoder_cnt > TRUSTED_VM_MAX_ENCODER_PER_CRTC))) {
  2153. /*
  2154. * disable idle-pc before releasing the HW
  2155. * allow only specified number of encoders on a given crtc
  2156. */
  2157. SDE_ERROR(
  2158. "VM switch failed; idle-pc:%d max:%d encoder_cnt:%d\n",
  2159. idle_pc_state, TRUSTED_VM_MAX_ENCODER_PER_CRTC,
  2160. crtc_encoder_cnt);
  2161. rc = -EINVAL;
  2162. goto end;
  2163. }
  2164. if ((new_vm_req == VM_REQ_ACQUIRE) && !vm_ops->vm_owns_hw(sde_kms)) {
  2165. rc = vm_ops->vm_acquire(sde_kms);
  2166. if (rc) {
  2167. SDE_ERROR(
  2168. "VM acquire failed; o_state:%d, n_state:%d, hw_owner:%d, rc:%d\n",
  2169. old_vm_req, new_vm_req,
  2170. vm_ops->vm_owns_hw(sde_kms), rc);
  2171. goto end;
  2172. }
  2173. if (vm_ops->vm_resource_init)
  2174. rc = vm_ops->vm_resource_init(sde_kms, state);
  2175. }
  2176. end:
  2177. sde_vm_unlock(sde_kms);
  2178. return rc;
  2179. }
  2180. static int sde_kms_check_secure_transition(struct msm_kms *kms,
  2181. struct drm_atomic_state *state)
  2182. {
  2183. struct sde_kms *sde_kms;
  2184. struct drm_device *dev;
  2185. struct drm_crtc *crtc;
  2186. struct drm_crtc *cur_crtc = NULL, *global_crtc = NULL;
  2187. struct drm_crtc_state *crtc_state;
  2188. int active_crtc_cnt = 0, global_active_crtc_cnt = 0;
  2189. bool sec_session = false, global_sec_session = false;
  2190. uint32_t fb_ns = 0, fb_sec = 0, fb_sec_dir = 0;
  2191. int i;
  2192. if (!kms || !state) {
  2193. return -EINVAL;
  2194. SDE_ERROR("invalid arguments\n");
  2195. }
  2196. sde_kms = to_sde_kms(kms);
  2197. dev = sde_kms->dev;
  2198. /* iterate state object for active secure/non-secure crtc */
  2199. for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
  2200. if (!crtc_state->active)
  2201. continue;
  2202. active_crtc_cnt++;
  2203. sde_crtc_state_find_plane_fb_modes(crtc_state, &fb_ns,
  2204. &fb_sec, &fb_sec_dir);
  2205. if (fb_sec_dir)
  2206. sec_session = true;
  2207. cur_crtc = crtc;
  2208. }
  2209. /* iterate global list for active and secure/non-secure crtc */
  2210. list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
  2211. if (!crtc->state->active)
  2212. continue;
  2213. global_active_crtc_cnt++;
  2214. /* update only when crtc is not the same as current crtc */
  2215. if (crtc != cur_crtc) {
  2216. fb_ns = fb_sec = fb_sec_dir = 0;
  2217. sde_crtc_find_plane_fb_modes(crtc, &fb_ns,
  2218. &fb_sec, &fb_sec_dir);
  2219. if (fb_sec_dir)
  2220. global_sec_session = true;
  2221. global_crtc = crtc;
  2222. }
  2223. }
  2224. if (!global_sec_session && !sec_session)
  2225. return 0;
  2226. /*
  2227. * - fail crtc commit, if secure-camera/secure-ui session is
  2228. * in-progress in any other display
  2229. * - fail secure-camera/secure-ui crtc commit, if any other display
  2230. * session is in-progress
  2231. */
  2232. if ((global_active_crtc_cnt > MAX_ALLOWED_CRTC_CNT_DURING_SECURE) ||
  2233. (active_crtc_cnt > MAX_ALLOWED_CRTC_CNT_DURING_SECURE)) {
  2234. SDE_ERROR(
  2235. "crtc%d secure check failed global_active:%d active:%d\n",
  2236. cur_crtc ? cur_crtc->base.id : -1,
  2237. global_active_crtc_cnt, active_crtc_cnt);
  2238. return -EPERM;
  2239. /*
  2240. * As only one crtc is allowed during secure session, the crtc
  2241. * in this commit should match with the global crtc
  2242. */
  2243. } else if (global_crtc && cur_crtc && (global_crtc != cur_crtc)) {
  2244. SDE_ERROR("crtc%d-sec%d not allowed during crtc%d-sec%d\n",
  2245. cur_crtc->base.id, sec_session,
  2246. global_crtc->base.id, global_sec_session);
  2247. return -EPERM;
  2248. }
  2249. return 0;
  2250. }
  2251. static void sde_kms_vm_res_release(struct msm_kms *kms,
  2252. struct drm_atomic_state *state)
  2253. {
  2254. struct drm_crtc *crtc;
  2255. struct drm_crtc_state *new_cstate;
  2256. struct sde_crtc_state *cstate;
  2257. struct sde_vm_ops *vm_ops;
  2258. enum sde_crtc_vm_req vm_req;
  2259. struct sde_kms *sde_kms = to_sde_kms(kms);
  2260. vm_ops = sde_vm_get_ops(sde_kms);
  2261. if (!vm_ops)
  2262. return;
  2263. crtc = sde_kms_vm_get_vm_crtc(state);
  2264. if (!crtc)
  2265. return;
  2266. new_cstate = drm_atomic_get_new_crtc_state(state, crtc);
  2267. cstate = to_sde_crtc_state(new_cstate);
  2268. vm_req = sde_crtc_get_property(cstate, CRTC_PROP_VM_REQ_STATE);
  2269. if (vm_req != VM_REQ_ACQUIRE)
  2270. return;
  2271. sde_vm_lock(sde_kms);
  2272. if (vm_ops->vm_acquire_fail_handler)
  2273. vm_ops->vm_acquire_fail_handler(sde_kms);
  2274. sde_vm_unlock(sde_kms);
  2275. }
  2276. static int sde_kms_atomic_check(struct msm_kms *kms,
  2277. struct drm_atomic_state *state)
  2278. {
  2279. struct sde_kms *sde_kms;
  2280. struct drm_device *dev;
  2281. int ret;
  2282. if (!kms || !state)
  2283. return -EINVAL;
  2284. sde_kms = to_sde_kms(kms);
  2285. dev = sde_kms->dev;
  2286. SDE_ATRACE_BEGIN("atomic_check");
  2287. if (sde_kms_is_suspend_blocked(dev)) {
  2288. SDE_DEBUG("suspended, skip atomic_check\n");
  2289. ret = -EBUSY;
  2290. goto end;
  2291. }
  2292. ret = sde_kms_check_vm_request(kms, state);
  2293. if (ret) {
  2294. SDE_ERROR("vm switch request checks failed\n");
  2295. goto end;
  2296. }
  2297. ret = drm_atomic_helper_check(dev, state);
  2298. if (ret)
  2299. goto vm_clean_up;
  2300. /*
  2301. * Check if any secure transition(moving CRTC between secure and
  2302. * non-secure state and vice-versa) is allowed or not. when moving
  2303. * to secure state, planes with fb_mode set to dir_translated only can
  2304. * be staged on the CRTC, and only one CRTC can be active during
  2305. * Secure state
  2306. */
  2307. ret = sde_kms_check_secure_transition(kms, state);
  2308. if (ret)
  2309. goto vm_clean_up;
  2310. goto end;
  2311. vm_clean_up:
  2312. sde_kms_vm_res_release(kms, state);
  2313. end:
  2314. SDE_ATRACE_END("atomic_check");
  2315. return ret;
  2316. }
  2317. static struct msm_gem_address_space*
  2318. _sde_kms_get_address_space(struct msm_kms *kms,
  2319. unsigned int domain)
  2320. {
  2321. struct sde_kms *sde_kms;
  2322. if (!kms) {
  2323. SDE_ERROR("invalid kms\n");
  2324. return NULL;
  2325. }
  2326. sde_kms = to_sde_kms(kms);
  2327. if (!sde_kms) {
  2328. SDE_ERROR("invalid sde_kms\n");
  2329. return NULL;
  2330. }
  2331. if (domain >= MSM_SMMU_DOMAIN_MAX)
  2332. return NULL;
  2333. return (sde_kms->aspace[domain] &&
  2334. sde_kms->aspace[domain]->domain_attached) ?
  2335. sde_kms->aspace[domain] : NULL;
  2336. }
  2337. static struct device *_sde_kms_get_address_space_device(struct msm_kms *kms,
  2338. unsigned int domain)
  2339. {
  2340. struct sde_kms *sde_kms;
  2341. struct msm_gem_address_space *aspace;
  2342. if (!kms) {
  2343. SDE_ERROR("invalid kms\n");
  2344. return NULL;
  2345. }
  2346. sde_kms = to_sde_kms(kms);
  2347. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev) {
  2348. SDE_ERROR("invalid params\n");
  2349. return NULL;
  2350. }
  2351. aspace = _sde_kms_get_address_space(kms, domain);
  2352. return (aspace && aspace->domain_attached) ?
  2353. msm_gem_get_aspace_device(aspace) : NULL;
  2354. }
  2355. static void _sde_kms_post_open(struct msm_kms *kms, struct drm_file *file)
  2356. {
  2357. struct drm_device *dev = NULL;
  2358. struct sde_kms *sde_kms = NULL;
  2359. struct drm_connector *connector = NULL;
  2360. struct drm_connector_list_iter conn_iter;
  2361. struct sde_connector *sde_conn = NULL;
  2362. if (!kms) {
  2363. SDE_ERROR("invalid kms\n");
  2364. return;
  2365. }
  2366. sde_kms = to_sde_kms(kms);
  2367. dev = sde_kms->dev;
  2368. if (!dev) {
  2369. SDE_ERROR("invalid device\n");
  2370. return;
  2371. }
  2372. if (!dev->mode_config.poll_enabled)
  2373. return;
  2374. mutex_lock(&dev->mode_config.mutex);
  2375. drm_connector_list_iter_begin(dev, &conn_iter);
  2376. drm_for_each_connector_iter(connector, &conn_iter) {
  2377. /* Only handle HPD capable connectors. */
  2378. if (!(connector->polled & DRM_CONNECTOR_POLL_HPD))
  2379. continue;
  2380. sde_conn = to_sde_connector(connector);
  2381. if (sde_conn->ops.post_open)
  2382. sde_conn->ops.post_open(&sde_conn->base,
  2383. sde_conn->display);
  2384. }
  2385. drm_connector_list_iter_end(&conn_iter);
  2386. mutex_unlock(&dev->mode_config.mutex);
  2387. }
  2388. static int _sde_kms_update_planes_for_cont_splash(struct sde_kms *sde_kms,
  2389. struct sde_splash_display *splash_display,
  2390. struct drm_crtc *crtc)
  2391. {
  2392. struct msm_drm_private *priv;
  2393. struct drm_plane *plane;
  2394. struct sde_splash_mem *splash;
  2395. enum sde_sspp plane_id;
  2396. bool is_virtual;
  2397. int i, j;
  2398. if (!sde_kms || !splash_display || !crtc) {
  2399. SDE_ERROR("invalid input args\n");
  2400. return -EINVAL;
  2401. }
  2402. priv = sde_kms->dev->dev_private;
  2403. for (i = 0; i < priv->num_planes; i++) {
  2404. plane = priv->planes[i];
  2405. plane_id = sde_plane_pipe(plane);
  2406. is_virtual = is_sde_plane_virtual(plane);
  2407. splash = splash_display->splash;
  2408. for (j = 0; j < splash_display->pipe_cnt; j++) {
  2409. if ((plane_id != splash_display->pipes[j].sspp) ||
  2410. (splash_display->pipes[j].is_virtual
  2411. != is_virtual))
  2412. continue;
  2413. if (splash && sde_plane_validate_src_addr(plane,
  2414. splash->splash_buf_base,
  2415. splash->splash_buf_size)) {
  2416. SDE_ERROR("invalid adr on pipe:%d crtc:%d\n",
  2417. plane_id, crtc->base.id);
  2418. }
  2419. SDE_DEBUG("set crtc:%d for plane:%d rect:%d\n",
  2420. crtc->base.id, plane_id, is_virtual);
  2421. }
  2422. }
  2423. return 0;
  2424. }
  2425. static int sde_kms_inform_cont_splash_res_disable(struct msm_kms *kms,
  2426. struct dsi_display *dsi_display)
  2427. {
  2428. void *display;
  2429. struct drm_encoder *encoder = NULL;
  2430. struct msm_display_info info;
  2431. struct drm_device *dev;
  2432. struct sde_kms *sde_kms;
  2433. struct drm_connector_list_iter conn_iter;
  2434. struct drm_connector *connector = NULL;
  2435. struct sde_connector *sde_conn = NULL;
  2436. int rc = 0;
  2437. sde_kms = to_sde_kms(kms);
  2438. dev = sde_kms->dev;
  2439. display = dsi_display;
  2440. if (dsi_display) {
  2441. if (dsi_display->bridge->base.encoder) {
  2442. encoder = dsi_display->bridge->base.encoder;
  2443. SDE_DEBUG("encoder name = %s\n", encoder->name);
  2444. }
  2445. memset(&info, 0x0, sizeof(info));
  2446. rc = dsi_display_get_info(NULL, &info, display);
  2447. if (rc) {
  2448. SDE_ERROR("%s: dsi get_info failed: %d\n",
  2449. rc, __func__);
  2450. encoder = NULL;
  2451. }
  2452. }
  2453. drm_connector_list_iter_begin(dev, &conn_iter);
  2454. drm_for_each_connector_iter(connector, &conn_iter) {
  2455. struct drm_encoder *c_encoder;
  2456. drm_connector_for_each_possible_encoder(connector,
  2457. c_encoder)
  2458. break;
  2459. if (!c_encoder) {
  2460. SDE_ERROR("c_encoder not found\n");
  2461. return -EINVAL;
  2462. }
  2463. /**
  2464. * Inform cont_splash is disabled to each interface/connector.
  2465. * This is currently supported for DSI interface.
  2466. */
  2467. sde_conn = to_sde_connector(connector);
  2468. if (sde_conn && sde_conn->ops.cont_splash_res_disable) {
  2469. if (!dsi_display || !encoder) {
  2470. sde_conn->ops.cont_splash_res_disable
  2471. (sde_conn->display);
  2472. } else if (c_encoder->base.id == encoder->base.id) {
  2473. /**
  2474. * This handles dual DSI
  2475. * configuration where one DSI
  2476. * interface has cont_splash
  2477. * enabled and the other doesn't.
  2478. */
  2479. sde_conn->ops.cont_splash_res_disable
  2480. (sde_conn->display);
  2481. break;
  2482. }
  2483. }
  2484. }
  2485. drm_connector_list_iter_end(&conn_iter);
  2486. return 0;
  2487. }
  2488. static int sde_kms_vm_trusted_cont_splash_res_init(struct sde_kms *sde_kms)
  2489. {
  2490. int i;
  2491. void *display;
  2492. struct dsi_display *dsi_display;
  2493. struct drm_encoder *encoder;
  2494. if (!sde_kms)
  2495. return -EINVAL;
  2496. if (!sde_in_trusted_vm(sde_kms))
  2497. return 0;
  2498. for (i = 0; i < sde_kms->dsi_display_count; i++) {
  2499. display = sde_kms->dsi_displays[i];
  2500. dsi_display = (struct dsi_display *)display;
  2501. if (!dsi_display->bridge->base.encoder) {
  2502. SDE_ERROR("no encoder on dsi display:%d", i);
  2503. return -EINVAL;
  2504. }
  2505. encoder = dsi_display->bridge->base.encoder;
  2506. encoder->possible_crtcs = 1 << i;
  2507. SDE_DEBUG(
  2508. "dsi-display:%d encoder id[%d]=%d name=%s crtcs=%x\n", i,
  2509. encoder->index, encoder->base.id,
  2510. encoder->name, encoder->possible_crtcs);
  2511. }
  2512. return 0;
  2513. }
  2514. static struct drm_display_mode *_sde_kms_get_splash_mode(
  2515. struct sde_kms *sde_kms, struct drm_connector *connector,
  2516. struct drm_atomic_state *state)
  2517. {
  2518. struct drm_display_mode *mode, *cur_mode = NULL;
  2519. struct drm_crtc *crtc;
  2520. struct drm_crtc_state *new_cstate, *old_cstate;
  2521. u32 i = 0;
  2522. if (sde_kms->splash_data.type == SDE_SPLASH_HANDOFF) {
  2523. list_for_each_entry(mode, &connector->modes, head) {
  2524. if (mode->type & DRM_MODE_TYPE_PREFERRED) {
  2525. cur_mode = mode;
  2526. break;
  2527. }
  2528. }
  2529. } else if (state) {
  2530. /* get the mode from first atomic_check phase for trusted_vm*/
  2531. for_each_oldnew_crtc_in_state(state, crtc, old_cstate,
  2532. new_cstate, i) {
  2533. if (!new_cstate->active && !old_cstate->active)
  2534. continue;
  2535. list_for_each_entry(mode, &connector->modes, head) {
  2536. if (drm_mode_equal(&new_cstate->mode, mode)) {
  2537. cur_mode = mode;
  2538. break;
  2539. }
  2540. }
  2541. }
  2542. }
  2543. return cur_mode;
  2544. }
  2545. static int sde_kms_cont_splash_config(struct msm_kms *kms,
  2546. struct drm_atomic_state *state)
  2547. {
  2548. void *display;
  2549. struct dsi_display *dsi_display;
  2550. struct msm_display_info info;
  2551. struct drm_encoder *encoder = NULL;
  2552. struct drm_crtc *crtc = NULL;
  2553. int i, rc = 0;
  2554. struct drm_display_mode *drm_mode = NULL;
  2555. struct drm_device *dev;
  2556. struct msm_drm_private *priv;
  2557. struct sde_kms *sde_kms;
  2558. struct drm_connector_list_iter conn_iter;
  2559. struct drm_connector *connector = NULL;
  2560. struct sde_connector *sde_conn = NULL;
  2561. struct sde_splash_display *splash_display;
  2562. if (!kms) {
  2563. SDE_ERROR("invalid kms\n");
  2564. return -EINVAL;
  2565. }
  2566. sde_kms = to_sde_kms(kms);
  2567. dev = sde_kms->dev;
  2568. if (!dev) {
  2569. SDE_ERROR("invalid device\n");
  2570. return -EINVAL;
  2571. }
  2572. rc = sde_kms_vm_trusted_cont_splash_res_init(sde_kms);
  2573. if (rc) {
  2574. SDE_ERROR("failed vm cont splash resource init, rc=%d", rc);
  2575. return -EINVAL;
  2576. }
  2577. if (((sde_kms->splash_data.type == SDE_SPLASH_HANDOFF)
  2578. && (!sde_kms->splash_data.num_splash_regions)) ||
  2579. !sde_kms->splash_data.num_splash_displays) {
  2580. DRM_INFO("cont_splash feature not enabled\n");
  2581. sde_kms_inform_cont_splash_res_disable(kms, NULL);
  2582. return rc;
  2583. }
  2584. DRM_INFO("cont_splash enabled in %d of %d display(s)\n",
  2585. sde_kms->splash_data.num_splash_displays,
  2586. sde_kms->dsi_display_count);
  2587. /* dsi */
  2588. for (i = 0; i < sde_kms->dsi_display_count; ++i) {
  2589. display = sde_kms->dsi_displays[i];
  2590. dsi_display = (struct dsi_display *)display;
  2591. splash_display = &sde_kms->splash_data.splash_display[i];
  2592. if (!splash_display->cont_splash_enabled) {
  2593. SDE_DEBUG("display->name = %s splash not enabled\n",
  2594. dsi_display->name);
  2595. sde_kms_inform_cont_splash_res_disable(kms,
  2596. dsi_display);
  2597. continue;
  2598. }
  2599. SDE_DEBUG("display->name = %s\n", dsi_display->name);
  2600. if (dsi_display->bridge->base.encoder) {
  2601. encoder = dsi_display->bridge->base.encoder;
  2602. SDE_DEBUG("encoder name = %s\n", encoder->name);
  2603. }
  2604. memset(&info, 0x0, sizeof(info));
  2605. rc = dsi_display_get_info(NULL, &info, display);
  2606. if (rc) {
  2607. SDE_ERROR("dsi get_info %d failed\n", i);
  2608. encoder = NULL;
  2609. continue;
  2610. }
  2611. SDE_DEBUG("info.is_connected = %s, info.display_type = %d\n",
  2612. ((info.is_connected) ? "true" : "false"),
  2613. info.display_type);
  2614. if (!encoder) {
  2615. SDE_ERROR("encoder not initialized\n");
  2616. return -EINVAL;
  2617. }
  2618. priv = sde_kms->dev->dev_private;
  2619. encoder->crtc = priv->crtcs[i];
  2620. crtc = encoder->crtc;
  2621. splash_display->encoder = encoder;
  2622. SDE_DEBUG("for dsi-display:%d crtc id[%d]:%d enc id[%d]:%d\n",
  2623. i, crtc->index, crtc->base.id, encoder->index,
  2624. encoder->base.id);
  2625. mutex_lock(&dev->mode_config.mutex);
  2626. drm_connector_list_iter_begin(dev, &conn_iter);
  2627. drm_for_each_connector_iter(connector, &conn_iter) {
  2628. struct drm_encoder *c_encoder;
  2629. drm_connector_for_each_possible_encoder(connector,
  2630. c_encoder)
  2631. break;
  2632. if (!c_encoder) {
  2633. SDE_ERROR("c_encoder not found\n");
  2634. mutex_unlock(&dev->mode_config.mutex);
  2635. return -EINVAL;
  2636. }
  2637. /**
  2638. * SDE_KMS doesn't attach more than one encoder to
  2639. * a DSI connector. So it is safe to check only with
  2640. * the first encoder entry. Revisit this logic if we
  2641. * ever have to support continuous splash for
  2642. * external displays in MST configuration.
  2643. */
  2644. if (c_encoder->base.id == encoder->base.id)
  2645. break;
  2646. }
  2647. drm_connector_list_iter_end(&conn_iter);
  2648. if (!connector) {
  2649. SDE_ERROR("connector not initialized\n");
  2650. mutex_unlock(&dev->mode_config.mutex);
  2651. return -EINVAL;
  2652. }
  2653. mutex_unlock(&dev->mode_config.mutex);
  2654. crtc->state->encoder_mask = (1 << drm_encoder_index(encoder));
  2655. drm_mode = _sde_kms_get_splash_mode(sde_kms, connector, state);
  2656. if (!drm_mode) {
  2657. SDE_ERROR("drm_mode not found; handoff_type:%d\n",
  2658. sde_kms->splash_data.type);
  2659. return -EINVAL;
  2660. }
  2661. SDE_DEBUG(
  2662. "drm_mode->name:%s, type:0x%x, flags:0x%x, handoff_type:%d\n",
  2663. drm_mode->name, drm_mode->type,
  2664. drm_mode->flags, sde_kms->splash_data.type);
  2665. /* Update CRTC drm structure */
  2666. crtc->state->active = true;
  2667. rc = drm_atomic_set_mode_for_crtc(crtc->state, drm_mode);
  2668. if (rc) {
  2669. SDE_ERROR("Failed: set mode for crtc. rc = %d\n", rc);
  2670. return rc;
  2671. }
  2672. drm_mode_copy(&crtc->state->adjusted_mode, drm_mode);
  2673. drm_mode_copy(&crtc->mode, drm_mode);
  2674. /* Update encoder structure */
  2675. sde_encoder_update_caps_for_cont_splash(encoder,
  2676. splash_display, true);
  2677. sde_crtc_update_cont_splash_settings(crtc);
  2678. sde_conn = to_sde_connector(connector);
  2679. if (sde_conn && sde_conn->ops.cont_splash_config)
  2680. sde_conn->ops.cont_splash_config(sde_conn->display);
  2681. rc = _sde_kms_update_planes_for_cont_splash(sde_kms,
  2682. splash_display, crtc);
  2683. if (rc) {
  2684. SDE_ERROR("Failed: updating plane status rc=%d\n", rc);
  2685. return rc;
  2686. }
  2687. }
  2688. return rc;
  2689. }
  2690. static bool sde_kms_check_for_splash(struct msm_kms *kms)
  2691. {
  2692. struct sde_kms *sde_kms;
  2693. if (!kms) {
  2694. SDE_ERROR("invalid kms\n");
  2695. return false;
  2696. }
  2697. sde_kms = to_sde_kms(kms);
  2698. return sde_kms->splash_data.num_splash_displays;
  2699. }
  2700. static int sde_kms_get_mixer_count(const struct msm_kms *kms,
  2701. const struct drm_display_mode *mode,
  2702. const struct msm_resource_caps_info *res, u32 *num_lm)
  2703. {
  2704. struct sde_kms *sde_kms;
  2705. s64 mode_clock_hz = 0;
  2706. s64 max_mdp_clock_hz = 0;
  2707. s64 max_lm_width = 0;
  2708. s64 hdisplay_fp = 0;
  2709. s64 htotal_fp = 0;
  2710. s64 vtotal_fp = 0;
  2711. s64 vrefresh_fp = 0;
  2712. s64 mdp_fudge_factor = 0;
  2713. s64 num_lm_fp = 0;
  2714. s64 lm_clk_fp = 0;
  2715. s64 lm_width_fp = 0;
  2716. int rc = 0;
  2717. if (!num_lm) {
  2718. SDE_ERROR("invalid num_lm pointer\n");
  2719. return -EINVAL;
  2720. }
  2721. /* default to 1 layer mixer */
  2722. *num_lm = 1;
  2723. if (!kms || !mode || !res) {
  2724. SDE_ERROR("invalid input args\n");
  2725. return -EINVAL;
  2726. }
  2727. sde_kms = to_sde_kms(kms);
  2728. max_mdp_clock_hz = drm_int2fixp(sde_kms->perf.max_core_clk_rate);
  2729. max_lm_width = drm_int2fixp(res->max_mixer_width);
  2730. hdisplay_fp = drm_int2fixp(mode->hdisplay);
  2731. htotal_fp = drm_int2fixp(mode->htotal);
  2732. vtotal_fp = drm_int2fixp(mode->vtotal);
  2733. vrefresh_fp = drm_int2fixp(mode->vrefresh);
  2734. mdp_fudge_factor = drm_fixp_from_fraction(105, 100);
  2735. /* mode clock = [(h * v * fps * 1.05) / (num_lm)] */
  2736. mode_clock_hz = drm_fixp_mul(htotal_fp, vtotal_fp);
  2737. mode_clock_hz = drm_fixp_mul(mode_clock_hz, vrefresh_fp);
  2738. mode_clock_hz = drm_fixp_mul(mode_clock_hz, mdp_fudge_factor);
  2739. if (mode_clock_hz > max_mdp_clock_hz ||
  2740. hdisplay_fp > max_lm_width) {
  2741. *num_lm = 0;
  2742. do {
  2743. *num_lm += 2;
  2744. num_lm_fp = drm_int2fixp(*num_lm);
  2745. lm_clk_fp = drm_fixp_div(mode_clock_hz, num_lm_fp);
  2746. lm_width_fp = drm_fixp_div(hdisplay_fp, num_lm_fp);
  2747. if (*num_lm > 4) {
  2748. rc = -EINVAL;
  2749. goto error;
  2750. }
  2751. } while (lm_clk_fp > max_mdp_clock_hz ||
  2752. lm_width_fp > max_lm_width);
  2753. mode_clock_hz = lm_clk_fp;
  2754. }
  2755. SDE_DEBUG("[%s] h=%d v=%d fps=%d lm=%d mode_clk=%llu max_clk=%llu\n",
  2756. mode->name, mode->htotal, mode->vtotal, mode->vrefresh,
  2757. *num_lm, drm_fixp2int(mode_clock_hz),
  2758. sde_kms->perf.max_core_clk_rate);
  2759. return 0;
  2760. error:
  2761. SDE_ERROR("required mode clk exceeds max mdp clk\n");
  2762. SDE_ERROR("[%s] h=%d v=%d fps=%d lm=%d mode_clk=%llu max_clk=%llu\n",
  2763. mode->name, mode->htotal, mode->vtotal, mode->vrefresh,
  2764. *num_lm, drm_fixp2int(mode_clock_hz),
  2765. sde_kms->perf.max_core_clk_rate);
  2766. return rc;
  2767. }
  2768. static int sde_kms_get_dsc_count(const struct msm_kms *kms,
  2769. u32 hdisplay, u32 *num_dsc)
  2770. {
  2771. struct sde_kms *sde_kms;
  2772. uint32_t max_dsc_width;
  2773. if (!num_dsc) {
  2774. SDE_ERROR("invalid num_dsc pointer\n");
  2775. return -EINVAL;
  2776. }
  2777. *num_dsc = 0;
  2778. if (!kms || !hdisplay) {
  2779. SDE_ERROR("invalid input args\n");
  2780. return -EINVAL;
  2781. }
  2782. sde_kms = to_sde_kms(kms);
  2783. max_dsc_width = sde_kms->catalog->max_dsc_width;
  2784. *num_dsc = DIV_ROUND_UP(hdisplay, max_dsc_width);
  2785. SDE_DEBUG("h=%d, max_dsc_width=%d, num_dsc=%d\n",
  2786. hdisplay, max_dsc_width,
  2787. *num_dsc);
  2788. return 0;
  2789. }
  2790. static void _sde_kms_null_commit(struct drm_device *dev,
  2791. struct drm_encoder *enc)
  2792. {
  2793. struct drm_modeset_acquire_ctx ctx;
  2794. struct drm_connector *conn = NULL;
  2795. struct drm_connector *tmp_conn = NULL;
  2796. struct drm_connector_list_iter conn_iter;
  2797. struct drm_atomic_state *state = NULL;
  2798. struct drm_crtc_state *crtc_state = NULL;
  2799. struct drm_connector_state *conn_state = NULL;
  2800. int retry_cnt = 0;
  2801. int ret = 0;
  2802. drm_modeset_acquire_init(&ctx, 0);
  2803. retry:
  2804. ret = drm_modeset_lock_all_ctx(dev, &ctx);
  2805. if (ret == -EDEADLK && retry_cnt < SDE_KMS_MODESET_LOCK_MAX_TRIALS) {
  2806. drm_modeset_backoff(&ctx);
  2807. retry_cnt++;
  2808. udelay(SDE_KMS_MODESET_LOCK_TIMEOUT_US);
  2809. goto retry;
  2810. } else if (WARN_ON(ret)) {
  2811. goto end;
  2812. }
  2813. state = drm_atomic_state_alloc(dev);
  2814. if (!state) {
  2815. DRM_ERROR("failed to allocate atomic state, %d\n", ret);
  2816. goto end;
  2817. }
  2818. state->acquire_ctx = &ctx;
  2819. drm_connector_list_iter_begin(dev, &conn_iter);
  2820. drm_for_each_connector_iter(tmp_conn, &conn_iter) {
  2821. if (enc == tmp_conn->state->best_encoder) {
  2822. conn = tmp_conn;
  2823. break;
  2824. }
  2825. }
  2826. drm_connector_list_iter_end(&conn_iter);
  2827. if (!conn) {
  2828. SDE_ERROR("error in finding conn for enc:%d\n", DRMID(enc));
  2829. goto end;
  2830. }
  2831. crtc_state = drm_atomic_get_crtc_state(state, enc->crtc);
  2832. conn_state = drm_atomic_get_connector_state(state, conn);
  2833. if (IS_ERR(conn_state)) {
  2834. SDE_ERROR("error %d getting connector %d state\n",
  2835. ret, DRMID(conn));
  2836. goto end;
  2837. }
  2838. crtc_state->active = true;
  2839. ret = drm_atomic_set_crtc_for_connector(conn_state, enc->crtc);
  2840. if (ret)
  2841. SDE_ERROR("error %d setting the crtc\n", ret);
  2842. ret = drm_atomic_commit(state);
  2843. if (ret)
  2844. SDE_ERROR("Error %d doing the atomic commit\n", ret);
  2845. end:
  2846. if (state)
  2847. drm_atomic_state_put(state);
  2848. drm_modeset_drop_locks(&ctx);
  2849. drm_modeset_acquire_fini(&ctx);
  2850. }
  2851. void sde_kms_display_early_wakeup(struct drm_device *dev,
  2852. const int32_t connector_id)
  2853. {
  2854. struct drm_connector_list_iter conn_iter;
  2855. struct drm_connector *conn;
  2856. struct drm_encoder *drm_enc;
  2857. drm_connector_list_iter_begin(dev, &conn_iter);
  2858. drm_for_each_connector_iter(conn, &conn_iter) {
  2859. if (connector_id != DRM_MSM_WAKE_UP_ALL_DISPLAYS &&
  2860. connector_id != conn->base.id)
  2861. continue;
  2862. if (conn->state && conn->state->best_encoder)
  2863. drm_enc = conn->state->best_encoder;
  2864. else
  2865. drm_enc = conn->encoder;
  2866. if (drm_enc)
  2867. sde_encoder_early_wakeup(drm_enc);
  2868. }
  2869. drm_connector_list_iter_end(&conn_iter);
  2870. }
  2871. static void _sde_kms_pm_suspend_idle_helper(struct sde_kms *sde_kms,
  2872. struct device *dev)
  2873. {
  2874. int i, ret, crtc_id = 0;
  2875. struct drm_device *ddev = dev_get_drvdata(dev);
  2876. struct drm_connector *conn;
  2877. struct drm_connector_list_iter conn_iter;
  2878. struct msm_drm_private *priv = sde_kms->dev->dev_private;
  2879. drm_connector_list_iter_begin(ddev, &conn_iter);
  2880. drm_for_each_connector_iter(conn, &conn_iter) {
  2881. uint64_t lp;
  2882. lp = sde_connector_get_lp(conn);
  2883. if (lp != SDE_MODE_DPMS_LP2)
  2884. continue;
  2885. if (sde_encoder_in_clone_mode(conn->encoder))
  2886. continue;
  2887. ret = sde_encoder_wait_for_event(conn->encoder,
  2888. MSM_ENC_TX_COMPLETE);
  2889. if (ret && ret != -EWOULDBLOCK) {
  2890. SDE_ERROR(
  2891. "[conn: %d] wait for commit done returned %d\n",
  2892. conn->base.id, ret);
  2893. } else if (!ret) {
  2894. crtc_id = drm_crtc_index(conn->state->crtc);
  2895. if (priv->event_thread[crtc_id].thread)
  2896. kthread_flush_worker(
  2897. &priv->event_thread[crtc_id].worker);
  2898. sde_encoder_idle_request(conn->encoder);
  2899. }
  2900. }
  2901. drm_connector_list_iter_end(&conn_iter);
  2902. for (i = 0; i < priv->num_crtcs; i++) {
  2903. if (priv->disp_thread[i].thread)
  2904. kthread_flush_worker(
  2905. &priv->disp_thread[i].worker);
  2906. if (priv->event_thread[i].thread)
  2907. kthread_flush_worker(
  2908. &priv->event_thread[i].worker);
  2909. }
  2910. kthread_flush_worker(&priv->pp_event_worker);
  2911. }
  2912. struct msm_display_mode *sde_kms_get_msm_mode(struct drm_crtc_state *c_state)
  2913. {
  2914. return sde_crtc_get_msm_mode(c_state);
  2915. }
  2916. static int sde_kms_pm_suspend(struct device *dev)
  2917. {
  2918. struct drm_device *ddev;
  2919. struct drm_modeset_acquire_ctx ctx;
  2920. struct drm_connector *conn;
  2921. struct drm_encoder *enc;
  2922. struct drm_connector_list_iter conn_iter;
  2923. struct drm_atomic_state *state = NULL;
  2924. struct sde_kms *sde_kms;
  2925. int ret = 0, num_crtcs = 0;
  2926. if (!dev)
  2927. return -EINVAL;
  2928. ddev = dev_get_drvdata(dev);
  2929. if (!ddev || !ddev_to_msm_kms(ddev))
  2930. return -EINVAL;
  2931. sde_kms = to_sde_kms(ddev_to_msm_kms(ddev));
  2932. SDE_EVT32(0);
  2933. /* disable hot-plug polling */
  2934. drm_kms_helper_poll_disable(ddev);
  2935. /* if a display stuck in CS trigger a null commit to complete handoff */
  2936. drm_for_each_encoder(enc, ddev) {
  2937. if (sde_encoder_in_cont_splash(enc) && enc->crtc)
  2938. _sde_kms_null_commit(ddev, enc);
  2939. }
  2940. /* acquire modeset lock(s) */
  2941. drm_modeset_acquire_init(&ctx, 0);
  2942. retry:
  2943. ret = drm_modeset_lock_all_ctx(ddev, &ctx);
  2944. if (ret)
  2945. goto unlock;
  2946. /* save current state for resume */
  2947. if (sde_kms->suspend_state)
  2948. drm_atomic_state_put(sde_kms->suspend_state);
  2949. sde_kms->suspend_state = drm_atomic_helper_duplicate_state(ddev, &ctx);
  2950. if (IS_ERR_OR_NULL(sde_kms->suspend_state)) {
  2951. ret = PTR_ERR(sde_kms->suspend_state);
  2952. DRM_ERROR("failed to back up suspend state, %d\n", ret);
  2953. sde_kms->suspend_state = NULL;
  2954. goto unlock;
  2955. }
  2956. /* create atomic state to disable all CRTCs */
  2957. state = drm_atomic_state_alloc(ddev);
  2958. if (!state) {
  2959. ret = -ENOMEM;
  2960. DRM_ERROR("failed to allocate crtc disable state, %d\n", ret);
  2961. goto unlock;
  2962. }
  2963. state->acquire_ctx = &ctx;
  2964. drm_connector_list_iter_begin(ddev, &conn_iter);
  2965. drm_for_each_connector_iter(conn, &conn_iter) {
  2966. struct drm_crtc_state *crtc_state;
  2967. uint64_t lp;
  2968. if (!conn->state || !conn->state->crtc ||
  2969. conn->dpms != DRM_MODE_DPMS_ON ||
  2970. sde_encoder_in_clone_mode(conn->encoder))
  2971. continue;
  2972. lp = sde_connector_get_lp(conn);
  2973. if (lp == SDE_MODE_DPMS_LP1) {
  2974. /* transition LP1->LP2 on pm suspend */
  2975. ret = sde_connector_set_property_for_commit(conn, state,
  2976. CONNECTOR_PROP_LP, SDE_MODE_DPMS_LP2);
  2977. if (ret) {
  2978. DRM_ERROR("failed to set lp2 for conn %d\n",
  2979. conn->base.id);
  2980. drm_connector_list_iter_end(&conn_iter);
  2981. goto unlock;
  2982. }
  2983. }
  2984. if (lp != SDE_MODE_DPMS_LP2) {
  2985. /* force CRTC to be inactive */
  2986. crtc_state = drm_atomic_get_crtc_state(state,
  2987. conn->state->crtc);
  2988. if (IS_ERR_OR_NULL(crtc_state)) {
  2989. DRM_ERROR("failed to get crtc %d state\n",
  2990. conn->state->crtc->base.id);
  2991. drm_connector_list_iter_end(&conn_iter);
  2992. goto unlock;
  2993. }
  2994. if (lp != SDE_MODE_DPMS_LP1)
  2995. crtc_state->active = false;
  2996. ++num_crtcs;
  2997. }
  2998. }
  2999. drm_connector_list_iter_end(&conn_iter);
  3000. /* check for nothing to do */
  3001. if (num_crtcs == 0) {
  3002. DRM_DEBUG("all crtcs are already in the off state\n");
  3003. sde_kms->suspend_block = true;
  3004. _sde_kms_pm_suspend_idle_helper(sde_kms, dev);
  3005. goto unlock;
  3006. }
  3007. /* commit the "disable all" state */
  3008. ret = drm_atomic_commit(state);
  3009. if (ret < 0) {
  3010. DRM_ERROR("failed to disable crtcs, %d\n", ret);
  3011. goto unlock;
  3012. }
  3013. sde_kms->suspend_block = true;
  3014. _sde_kms_pm_suspend_idle_helper(sde_kms, dev);
  3015. unlock:
  3016. if (state) {
  3017. drm_atomic_state_put(state);
  3018. state = NULL;
  3019. }
  3020. if (ret == -EDEADLK) {
  3021. drm_modeset_backoff(&ctx);
  3022. goto retry;
  3023. }
  3024. drm_modeset_drop_locks(&ctx);
  3025. drm_modeset_acquire_fini(&ctx);
  3026. /*
  3027. * pm runtime driver avoids multiple runtime_suspend API call by
  3028. * checking runtime_status. However, this call helps when there is a
  3029. * race condition between pm_suspend call and doze_suspend/power_off
  3030. * commit. It removes the extra vote from suspend and adds it back
  3031. * later to allow power collapse during pm_suspend call
  3032. */
  3033. pm_runtime_put_sync(dev);
  3034. pm_runtime_get_noresume(dev);
  3035. /* dump clock state before entering suspend */
  3036. if (sde_kms->pm_suspend_clk_dump)
  3037. _sde_kms_dump_clks_state(sde_kms);
  3038. return ret;
  3039. }
  3040. static int sde_kms_pm_resume(struct device *dev)
  3041. {
  3042. struct drm_device *ddev;
  3043. struct sde_kms *sde_kms;
  3044. struct drm_modeset_acquire_ctx ctx;
  3045. int ret, i;
  3046. if (!dev)
  3047. return -EINVAL;
  3048. ddev = dev_get_drvdata(dev);
  3049. if (!ddev || !ddev_to_msm_kms(ddev))
  3050. return -EINVAL;
  3051. sde_kms = to_sde_kms(ddev_to_msm_kms(ddev));
  3052. SDE_EVT32(sde_kms->suspend_state != NULL);
  3053. drm_mode_config_reset(ddev);
  3054. drm_modeset_acquire_init(&ctx, 0);
  3055. retry:
  3056. ret = drm_modeset_lock_all_ctx(ddev, &ctx);
  3057. if (ret == -EDEADLK) {
  3058. drm_modeset_backoff(&ctx);
  3059. goto retry;
  3060. } else if (WARN_ON(ret)) {
  3061. goto end;
  3062. }
  3063. sde_kms->suspend_block = false;
  3064. if (sde_kms->suspend_state) {
  3065. sde_kms->suspend_state->acquire_ctx = &ctx;
  3066. for (i = 0; i < TEARDOWN_DEADLOCK_RETRY_MAX; i++) {
  3067. ret = drm_atomic_helper_commit_duplicated_state(
  3068. sde_kms->suspend_state, &ctx);
  3069. if (ret != -EDEADLK)
  3070. break;
  3071. drm_modeset_backoff(&ctx);
  3072. }
  3073. if (ret < 0)
  3074. DRM_ERROR("failed to restore state, %d\n", ret);
  3075. drm_atomic_state_put(sde_kms->suspend_state);
  3076. sde_kms->suspend_state = NULL;
  3077. }
  3078. end:
  3079. drm_modeset_drop_locks(&ctx);
  3080. drm_modeset_acquire_fini(&ctx);
  3081. /* enable hot-plug polling */
  3082. drm_kms_helper_poll_enable(ddev);
  3083. return 0;
  3084. }
  3085. static const struct msm_kms_funcs kms_funcs = {
  3086. .hw_init = sde_kms_hw_init,
  3087. .postinit = sde_kms_postinit,
  3088. .irq_preinstall = sde_irq_preinstall,
  3089. .irq_postinstall = sde_irq_postinstall,
  3090. .irq_uninstall = sde_irq_uninstall,
  3091. .irq = sde_irq,
  3092. .lastclose = sde_kms_lastclose,
  3093. .prepare_fence = sde_kms_prepare_fence,
  3094. .prepare_commit = sde_kms_prepare_commit,
  3095. .commit = sde_kms_commit,
  3096. .complete_commit = sde_kms_complete_commit,
  3097. .get_msm_mode = sde_kms_get_msm_mode,
  3098. .wait_for_crtc_commit_done = sde_kms_wait_for_commit_done,
  3099. .wait_for_tx_complete = sde_kms_wait_for_frame_transfer_complete,
  3100. .check_modified_format = sde_format_check_modified_format,
  3101. .atomic_check = sde_kms_atomic_check,
  3102. .get_format = sde_get_msm_format,
  3103. .round_pixclk = sde_kms_round_pixclk,
  3104. .display_early_wakeup = sde_kms_display_early_wakeup,
  3105. .pm_suspend = sde_kms_pm_suspend,
  3106. .pm_resume = sde_kms_pm_resume,
  3107. .destroy = sde_kms_destroy,
  3108. .debugfs_destroy = sde_kms_debugfs_destroy,
  3109. .cont_splash_config = sde_kms_cont_splash_config,
  3110. .register_events = _sde_kms_register_events,
  3111. .get_address_space = _sde_kms_get_address_space,
  3112. .get_address_space_device = _sde_kms_get_address_space_device,
  3113. .postopen = _sde_kms_post_open,
  3114. .check_for_splash = sde_kms_check_for_splash,
  3115. .get_mixer_count = sde_kms_get_mixer_count,
  3116. .get_dsc_count = sde_kms_get_dsc_count,
  3117. };
  3118. static int _sde_kms_mmu_destroy(struct sde_kms *sde_kms)
  3119. {
  3120. int i;
  3121. for (i = ARRAY_SIZE(sde_kms->aspace) - 1; i >= 0; i--) {
  3122. if (!sde_kms->aspace[i])
  3123. continue;
  3124. msm_gem_address_space_put(sde_kms->aspace[i]);
  3125. sde_kms->aspace[i] = NULL;
  3126. }
  3127. return 0;
  3128. }
  3129. static int _sde_kms_mmu_init(struct sde_kms *sde_kms)
  3130. {
  3131. struct msm_mmu *mmu;
  3132. int i, ret;
  3133. int early_map = 0;
  3134. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev)
  3135. return -EINVAL;
  3136. for (i = 0; i < MSM_SMMU_DOMAIN_MAX; i++) {
  3137. struct msm_gem_address_space *aspace;
  3138. mmu = msm_smmu_new(sde_kms->dev->dev, i);
  3139. if (IS_ERR(mmu)) {
  3140. ret = PTR_ERR(mmu);
  3141. SDE_DEBUG("failed to init iommu id %d: rc:%d\n",
  3142. i, ret);
  3143. continue;
  3144. }
  3145. aspace = msm_gem_smmu_address_space_create(sde_kms->dev,
  3146. mmu, "sde");
  3147. if (IS_ERR(aspace)) {
  3148. ret = PTR_ERR(aspace);
  3149. mmu->funcs->destroy(mmu);
  3150. goto fail;
  3151. }
  3152. sde_kms->aspace[i] = aspace;
  3153. aspace->domain_attached = true;
  3154. /* Mapping splash memory block */
  3155. if ((i == MSM_SMMU_DOMAIN_UNSECURE) &&
  3156. sde_kms->splash_data.num_splash_regions) {
  3157. ret = _sde_kms_map_all_splash_regions(sde_kms);
  3158. if (ret) {
  3159. SDE_ERROR("failed to map ret:%d\n", ret);
  3160. goto fail;
  3161. }
  3162. }
  3163. /*
  3164. * disable early-map which would have been enabled during
  3165. * bootup by smmu through the device-tree hint for cont-spash
  3166. */
  3167. ret = mmu->funcs->set_attribute(mmu, DOMAIN_ATTR_EARLY_MAP,
  3168. &early_map);
  3169. if (ret) {
  3170. SDE_ERROR("failed to set_att ret:%d, early_map:%d\n",
  3171. ret, early_map);
  3172. goto early_map_fail;
  3173. }
  3174. }
  3175. sde_kms->base.aspace = sde_kms->aspace[0];
  3176. return 0;
  3177. early_map_fail:
  3178. _sde_kms_unmap_all_splash_regions(sde_kms);
  3179. fail:
  3180. _sde_kms_mmu_destroy(sde_kms);
  3181. return ret;
  3182. }
  3183. static void sde_kms_init_rot_sid_hw(struct sde_kms *sde_kms)
  3184. {
  3185. if (!sde_kms || !sde_kms->hw_sid || sde_in_trusted_vm(sde_kms))
  3186. return;
  3187. sde_hw_set_rotator_sid(sde_kms->hw_sid);
  3188. }
  3189. static void sde_kms_init_shared_hw(struct sde_kms *sde_kms)
  3190. {
  3191. if (!sde_kms || !sde_kms->hw_mdp || !sde_kms->catalog)
  3192. return;
  3193. if (sde_kms->hw_mdp->ops.reset_ubwc)
  3194. sde_kms->hw_mdp->ops.reset_ubwc(sde_kms->hw_mdp,
  3195. sde_kms->catalog);
  3196. }
  3197. static void _sde_kms_set_lutdma_vbif_remap(struct sde_kms *sde_kms)
  3198. {
  3199. struct sde_vbif_set_qos_params qos_params;
  3200. struct sde_mdss_cfg *catalog;
  3201. if (!sde_kms->catalog)
  3202. return;
  3203. catalog = sde_kms->catalog;
  3204. memset(&qos_params, 0, sizeof(qos_params));
  3205. qos_params.vbif_idx = catalog->dma_cfg.vbif_idx;
  3206. qos_params.xin_id = catalog->dma_cfg.xin_id;
  3207. qos_params.clk_ctrl = catalog->dma_cfg.clk_ctrl;
  3208. qos_params.client_type = VBIF_LUTDMA_CLIENT;
  3209. sde_vbif_set_qos_remap(sde_kms, &qos_params);
  3210. }
  3211. static int _sde_kms_active_override(struct sde_kms *sde_kms, bool enable)
  3212. {
  3213. struct sde_hw_uidle *uidle;
  3214. if (!sde_kms) {
  3215. SDE_ERROR("invalid kms\n");
  3216. return -EINVAL;
  3217. }
  3218. uidle = sde_kms->hw_uidle;
  3219. if (uidle && uidle->ops.active_override_enable)
  3220. uidle->ops.active_override_enable(uidle, enable);
  3221. return 0;
  3222. }
  3223. static void _sde_kms_update_pm_qos_irq_request(struct sde_kms *sde_kms)
  3224. {
  3225. struct device *cpu_dev;
  3226. int cpu = 0;
  3227. u32 cpu_irq_latency = sde_kms->catalog->perf.cpu_irq_latency;
  3228. if (cpumask_empty(&sde_kms->irq_cpu_mask)) {
  3229. SDE_DEBUG("%s: irq_cpu_mask is empty\n", __func__);
  3230. return;
  3231. }
  3232. for_each_cpu(cpu, &sde_kms->irq_cpu_mask) {
  3233. cpu_dev = get_cpu_device(cpu);
  3234. if (!cpu_dev) {
  3235. SDE_DEBUG("%s: failed to get cpu%d device\n", __func__,
  3236. cpu);
  3237. continue;
  3238. }
  3239. if (dev_pm_qos_request_active(&sde_kms->pm_qos_irq_req[cpu]))
  3240. dev_pm_qos_update_request(&sde_kms->pm_qos_irq_req[cpu],
  3241. cpu_irq_latency);
  3242. else
  3243. dev_pm_qos_add_request(cpu_dev,
  3244. &sde_kms->pm_qos_irq_req[cpu],
  3245. DEV_PM_QOS_RESUME_LATENCY,
  3246. cpu_irq_latency);
  3247. }
  3248. }
  3249. static void _sde_kms_remove_pm_qos_irq_request(struct sde_kms *sde_kms)
  3250. {
  3251. struct device *cpu_dev;
  3252. int cpu = 0;
  3253. if (cpumask_empty(&sde_kms->irq_cpu_mask)) {
  3254. SDE_DEBUG("%s: irq_cpu_mask is empty\n", __func__);
  3255. return;
  3256. }
  3257. for_each_cpu(cpu, &sde_kms->irq_cpu_mask) {
  3258. cpu_dev = get_cpu_device(cpu);
  3259. if (!cpu_dev) {
  3260. SDE_DEBUG("%s: failed to get cpu%d device\n", __func__,
  3261. cpu);
  3262. continue;
  3263. }
  3264. if (dev_pm_qos_request_active(&sde_kms->pm_qos_irq_req[cpu]))
  3265. dev_pm_qos_remove_request(
  3266. &sde_kms->pm_qos_irq_req[cpu]);
  3267. }
  3268. }
  3269. void sde_kms_cpu_vote_for_irq(struct sde_kms *sde_kms, bool enable)
  3270. {
  3271. struct msm_drm_private *priv = sde_kms->dev->dev_private;
  3272. mutex_lock(&priv->phandle.phandle_lock);
  3273. if (enable && atomic_inc_return(&sde_kms->irq_vote_count) == 1)
  3274. _sde_kms_update_pm_qos_irq_request(sde_kms);
  3275. else if (!enable && atomic_dec_return(&sde_kms->irq_vote_count) == 0)
  3276. _sde_kms_remove_pm_qos_irq_request(sde_kms);
  3277. mutex_unlock(&priv->phandle.phandle_lock);
  3278. }
  3279. static void sde_kms_irq_affinity_notify(
  3280. struct irq_affinity_notify *affinity_notify,
  3281. const cpumask_t *mask)
  3282. {
  3283. struct msm_drm_private *priv;
  3284. struct sde_kms *sde_kms = container_of(affinity_notify,
  3285. struct sde_kms, affinity_notify);
  3286. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private)
  3287. return;
  3288. priv = sde_kms->dev->dev_private;
  3289. mutex_lock(&priv->phandle.phandle_lock);
  3290. _sde_kms_remove_pm_qos_irq_request(sde_kms);
  3291. // save irq cpu mask
  3292. sde_kms->irq_cpu_mask = *mask;
  3293. // request vote with updated irq cpu mask
  3294. if (atomic_read(&sde_kms->irq_vote_count))
  3295. _sde_kms_update_pm_qos_irq_request(sde_kms);
  3296. mutex_unlock(&priv->phandle.phandle_lock);
  3297. }
  3298. static void sde_kms_irq_affinity_release(struct kref *ref) {}
  3299. static void sde_kms_handle_power_event(u32 event_type, void *usr)
  3300. {
  3301. struct sde_kms *sde_kms = usr;
  3302. struct msm_kms *msm_kms;
  3303. msm_kms = &sde_kms->base;
  3304. if (!sde_kms)
  3305. return;
  3306. SDE_DEBUG("event_type:%d\n", event_type);
  3307. SDE_EVT32_VERBOSE(event_type);
  3308. if (event_type == SDE_POWER_EVENT_POST_ENABLE) {
  3309. sde_irq_update(msm_kms, true);
  3310. sde_kms->first_kickoff = true;
  3311. /**
  3312. * Rotator sid needs to be programmed since uefi doesn't
  3313. * configure it during continuous splash
  3314. */
  3315. sde_kms_init_rot_sid_hw(sde_kms);
  3316. if (sde_kms->splash_data.num_splash_displays ||
  3317. sde_in_trusted_vm(sde_kms))
  3318. return;
  3319. sde_vbif_init_memtypes(sde_kms);
  3320. sde_kms_init_shared_hw(sde_kms);
  3321. _sde_kms_set_lutdma_vbif_remap(sde_kms);
  3322. } else if (event_type == SDE_POWER_EVENT_PRE_DISABLE) {
  3323. sde_irq_update(msm_kms, false);
  3324. sde_kms->first_kickoff = false;
  3325. if (sde_in_trusted_vm(sde_kms))
  3326. return;
  3327. _sde_kms_active_override(sde_kms, true);
  3328. if (!is_sde_rsc_available(SDE_RSC_INDEX))
  3329. sde_vbif_axi_halt_request(sde_kms);
  3330. }
  3331. }
  3332. #define genpd_to_sde_kms(domain) container_of(domain, struct sde_kms, genpd)
  3333. static int sde_kms_pd_enable(struct generic_pm_domain *genpd)
  3334. {
  3335. struct sde_kms *sde_kms = genpd_to_sde_kms(genpd);
  3336. int rc = -EINVAL;
  3337. SDE_DEBUG("\n");
  3338. rc = pm_runtime_get_sync(sde_kms->dev->dev);
  3339. if (rc > 0)
  3340. rc = 0;
  3341. SDE_EVT32(rc, genpd->device_count);
  3342. return rc;
  3343. }
  3344. static int sde_kms_pd_disable(struct generic_pm_domain *genpd)
  3345. {
  3346. struct sde_kms *sde_kms = genpd_to_sde_kms(genpd);
  3347. SDE_DEBUG("\n");
  3348. pm_runtime_put_sync(sde_kms->dev->dev);
  3349. SDE_EVT32(genpd->device_count);
  3350. return 0;
  3351. }
  3352. static int _sde_kms_get_splash_data(struct sde_kms *sde_kms,
  3353. struct sde_splash_data *data)
  3354. {
  3355. int i = 0;
  3356. int ret = 0;
  3357. struct device_node *parent, *node, *node1;
  3358. struct resource r, r1;
  3359. const char *node_name = "splash_region";
  3360. struct sde_splash_mem *mem;
  3361. bool share_splash_mem = false;
  3362. int num_displays, num_regions;
  3363. struct sde_splash_display *splash_display;
  3364. if (!data)
  3365. return -EINVAL;
  3366. memset(data, 0, sizeof(*data));
  3367. parent = of_find_node_by_path("/reserved-memory");
  3368. if (!parent) {
  3369. SDE_ERROR("failed to find reserved-memory node\n");
  3370. return -EINVAL;
  3371. }
  3372. node = of_find_node_by_name(parent, node_name);
  3373. if (!node) {
  3374. SDE_DEBUG("failed to find node %s\n", node_name);
  3375. return -EINVAL;
  3376. }
  3377. node1 = of_find_node_by_name(NULL, "disp_rdump_region");
  3378. if (!node1)
  3379. SDE_DEBUG("failed to find disp ramdump memory reservation\n");
  3380. /**
  3381. * Support sharing a single splash memory for all the built in displays
  3382. * and also independent splash region per displays. Incase of
  3383. * independent splash region for each connected display, dtsi node of
  3384. * cont_splash_region should be collection of all memory regions
  3385. * Ex: <r1.start r1.end r2.start r2.end ... rn.start, rn.end>
  3386. */
  3387. num_displays = dsi_display_get_num_of_displays();
  3388. num_regions = of_property_count_u64_elems(node, "reg") / 2;
  3389. data->num_splash_displays = num_displays;
  3390. SDE_DEBUG("splash mem num_regions:%d\n", num_regions);
  3391. if (num_displays > num_regions) {
  3392. share_splash_mem = true;
  3393. pr_info(":%d displays share same splash buf\n", num_displays);
  3394. }
  3395. for (i = 0; i < num_displays; i++) {
  3396. splash_display = &data->splash_display[i];
  3397. if (!i || !share_splash_mem) {
  3398. if (of_address_to_resource(node, i, &r)) {
  3399. SDE_ERROR("invalid data for:%s\n", node_name);
  3400. return -EINVAL;
  3401. }
  3402. mem = &data->splash_mem[i];
  3403. if (!node1 || of_address_to_resource(node1, i, &r1)) {
  3404. SDE_DEBUG("failed to find ramdump memory\n");
  3405. mem->ramdump_base = 0;
  3406. mem->ramdump_size = 0;
  3407. } else {
  3408. mem->ramdump_base = (unsigned long)r1.start;
  3409. mem->ramdump_size = (r1.end - r1.start) + 1;
  3410. }
  3411. mem->splash_buf_base = (unsigned long)r.start;
  3412. mem->splash_buf_size = (r.end - r.start) + 1;
  3413. mem->ref_cnt = 0;
  3414. splash_display->splash = mem;
  3415. data->num_splash_regions++;
  3416. } else {
  3417. data->splash_display[i].splash = &data->splash_mem[0];
  3418. }
  3419. SDE_DEBUG("splash mem for disp:%d add:%lx size:%x\n", (i + 1),
  3420. splash_display->splash->splash_buf_base,
  3421. splash_display->splash->splash_buf_size);
  3422. }
  3423. sde_kms->splash_data.type = SDE_SPLASH_HANDOFF;
  3424. return ret;
  3425. }
  3426. static int _sde_kms_hw_init_ioremap(struct sde_kms *sde_kms,
  3427. struct platform_device *platformdev)
  3428. {
  3429. int rc = -EINVAL;
  3430. sde_kms->mmio = msm_ioremap(platformdev, "mdp_phys", "mdp_phys");
  3431. if (IS_ERR(sde_kms->mmio)) {
  3432. rc = PTR_ERR(sde_kms->mmio);
  3433. SDE_ERROR("mdp register memory map failed: %d\n", rc);
  3434. sde_kms->mmio = NULL;
  3435. goto error;
  3436. }
  3437. DRM_INFO("mapped mdp address space @%pK\n", sde_kms->mmio);
  3438. sde_kms->mmio_len = msm_iomap_size(platformdev, "mdp_phys");
  3439. rc = sde_dbg_reg_register_base(SDE_DBG_NAME, sde_kms->mmio,
  3440. sde_kms->mmio_len);
  3441. if (rc)
  3442. SDE_ERROR("dbg base register kms failed: %d\n", rc);
  3443. sde_kms->vbif[VBIF_RT] = msm_ioremap(platformdev, "vbif_phys",
  3444. "vbif_phys");
  3445. if (IS_ERR(sde_kms->vbif[VBIF_RT])) {
  3446. rc = PTR_ERR(sde_kms->vbif[VBIF_RT]);
  3447. SDE_ERROR("vbif register memory map failed: %d\n", rc);
  3448. sde_kms->vbif[VBIF_RT] = NULL;
  3449. goto error;
  3450. }
  3451. sde_kms->vbif_len[VBIF_RT] = msm_iomap_size(platformdev,
  3452. "vbif_phys");
  3453. rc = sde_dbg_reg_register_base("vbif_rt", sde_kms->vbif[VBIF_RT],
  3454. sde_kms->vbif_len[VBIF_RT]);
  3455. if (rc)
  3456. SDE_ERROR("dbg base register vbif_rt failed: %d\n", rc);
  3457. sde_kms->vbif[VBIF_NRT] = msm_ioremap(platformdev, "vbif_nrt_phys",
  3458. "vbif_nrt_phys");
  3459. if (IS_ERR(sde_kms->vbif[VBIF_NRT])) {
  3460. sde_kms->vbif[VBIF_NRT] = NULL;
  3461. SDE_DEBUG("VBIF NRT is not defined");
  3462. } else {
  3463. sde_kms->vbif_len[VBIF_NRT] = msm_iomap_size(platformdev,
  3464. "vbif_nrt_phys");
  3465. rc = sde_dbg_reg_register_base("vbif_nrt",
  3466. sde_kms->vbif[VBIF_NRT],
  3467. sde_kms->vbif_len[VBIF_NRT]);
  3468. if (rc)
  3469. SDE_ERROR("dbg base register vbif_nrt failed: %d\n",
  3470. rc);
  3471. }
  3472. sde_kms->reg_dma = msm_ioremap(platformdev, "regdma_phys",
  3473. "regdma_phys");
  3474. if (IS_ERR(sde_kms->reg_dma)) {
  3475. sde_kms->reg_dma = NULL;
  3476. SDE_DEBUG("REG_DMA is not defined");
  3477. } else {
  3478. sde_kms->reg_dma_len = msm_iomap_size(platformdev,
  3479. "regdma_phys");
  3480. rc = sde_dbg_reg_register_base("reg_dma",
  3481. sde_kms->reg_dma,
  3482. sde_kms->reg_dma_len);
  3483. if (rc)
  3484. SDE_ERROR("dbg base register reg_dma failed: %d\n",
  3485. rc);
  3486. }
  3487. sde_kms->sid = msm_ioremap(platformdev, "sid_phys",
  3488. "sid_phys");
  3489. if (IS_ERR(sde_kms->sid)) {
  3490. SDE_DEBUG("sid register is not defined: %d\n", rc);
  3491. sde_kms->sid = NULL;
  3492. } else {
  3493. sde_kms->sid_len = msm_iomap_size(platformdev, "sid_phys");
  3494. rc = sde_dbg_reg_register_base("sid", sde_kms->sid,
  3495. sde_kms->sid_len);
  3496. if (rc)
  3497. SDE_ERROR("dbg base register sid failed: %d\n", rc);
  3498. }
  3499. error:
  3500. return rc;
  3501. }
  3502. static int _sde_kms_hw_init_power_helper(struct drm_device *dev,
  3503. struct sde_kms *sde_kms)
  3504. {
  3505. int rc = 0;
  3506. if (of_find_property(dev->dev->of_node, "#power-domain-cells", NULL)) {
  3507. sde_kms->genpd.name = dev->unique;
  3508. sde_kms->genpd.power_off = sde_kms_pd_disable;
  3509. sde_kms->genpd.power_on = sde_kms_pd_enable;
  3510. rc = pm_genpd_init(&sde_kms->genpd, NULL, true);
  3511. if (rc < 0) {
  3512. SDE_ERROR("failed to init genpd provider %s: %d\n",
  3513. sde_kms->genpd.name, rc);
  3514. return rc;
  3515. }
  3516. rc = of_genpd_add_provider_simple(dev->dev->of_node,
  3517. &sde_kms->genpd);
  3518. if (rc < 0) {
  3519. SDE_ERROR("failed to add genpd provider %s: %d\n",
  3520. sde_kms->genpd.name, rc);
  3521. pm_genpd_remove(&sde_kms->genpd);
  3522. return rc;
  3523. }
  3524. sde_kms->genpd_init = true;
  3525. SDE_DEBUG("added genpd provider %s\n", sde_kms->genpd.name);
  3526. }
  3527. return rc;
  3528. }
  3529. static int _sde_kms_hw_init_blocks(struct sde_kms *sde_kms,
  3530. struct drm_device *dev,
  3531. struct msm_drm_private *priv)
  3532. {
  3533. struct sde_rm *rm = NULL;
  3534. int i, rc = -EINVAL;
  3535. sde_kms->catalog = sde_hw_catalog_init(dev);
  3536. if (IS_ERR_OR_NULL(sde_kms->catalog)) {
  3537. rc = PTR_ERR(sde_kms->catalog);
  3538. if (!sde_kms->catalog)
  3539. rc = -EINVAL;
  3540. SDE_ERROR("catalog init failed: %d\n", rc);
  3541. sde_kms->catalog = NULL;
  3542. goto power_error;
  3543. }
  3544. sde_kms->core_rev = sde_kms->catalog->hwversion;
  3545. pr_info("sde hardware revision:0x%x\n", sde_kms->core_rev);
  3546. /* initialize power domain if defined */
  3547. rc = _sde_kms_hw_init_power_helper(dev, sde_kms);
  3548. if (rc) {
  3549. SDE_ERROR("_sde_kms_hw_init_power_helper failed: %d\n", rc);
  3550. goto genpd_err;
  3551. }
  3552. rc = _sde_kms_mmu_init(sde_kms);
  3553. if (rc) {
  3554. SDE_ERROR("sde_kms_mmu_init failed: %d\n", rc);
  3555. goto power_error;
  3556. }
  3557. /* Initialize reg dma block which is a singleton */
  3558. rc = sde_reg_dma_init(sde_kms->reg_dma, sde_kms->catalog,
  3559. sde_kms->dev);
  3560. if (rc) {
  3561. SDE_ERROR("failed: reg dma init failed\n");
  3562. goto power_error;
  3563. }
  3564. sde_dbg_init_dbg_buses(sde_kms->core_rev);
  3565. rm = &sde_kms->rm;
  3566. rc = sde_rm_init(rm, sde_kms->catalog, sde_kms->mmio,
  3567. sde_kms->dev);
  3568. if (rc) {
  3569. SDE_ERROR("rm init failed: %d\n", rc);
  3570. goto power_error;
  3571. }
  3572. sde_kms->rm_init = true;
  3573. sde_kms->hw_intr = sde_hw_intr_init(sde_kms->mmio, sde_kms->catalog);
  3574. if (IS_ERR_OR_NULL(sde_kms->hw_intr)) {
  3575. rc = PTR_ERR(sde_kms->hw_intr);
  3576. SDE_ERROR("hw_intr init failed: %d\n", rc);
  3577. sde_kms->hw_intr = NULL;
  3578. goto hw_intr_init_err;
  3579. }
  3580. /*
  3581. * Attempt continuous splash handoff only if reserved
  3582. * splash memory is found & release resources on any error
  3583. * in finding display hw config in splash
  3584. */
  3585. if (sde_kms->splash_data.num_splash_regions) {
  3586. struct sde_splash_display *display;
  3587. int ret, display_count =
  3588. sde_kms->splash_data.num_splash_displays;
  3589. ret = sde_rm_cont_splash_res_init(priv, &sde_kms->rm,
  3590. &sde_kms->splash_data, sde_kms->catalog);
  3591. for (i = 0; i < display_count; i++) {
  3592. display = &sde_kms->splash_data.splash_display[i];
  3593. /*
  3594. * free splash region on resource init failure and
  3595. * cont-splash disabled case
  3596. */
  3597. if (!display->cont_splash_enabled || ret)
  3598. _sde_kms_free_splash_display_data(
  3599. sde_kms, display);
  3600. }
  3601. }
  3602. sde_kms->hw_mdp = sde_rm_get_mdp(&sde_kms->rm);
  3603. if (IS_ERR_OR_NULL(sde_kms->hw_mdp)) {
  3604. rc = PTR_ERR(sde_kms->hw_mdp);
  3605. if (!sde_kms->hw_mdp)
  3606. rc = -EINVAL;
  3607. SDE_ERROR("failed to get hw_mdp: %d\n", rc);
  3608. sde_kms->hw_mdp = NULL;
  3609. goto power_error;
  3610. }
  3611. for (i = 0; i < sde_kms->catalog->vbif_count; i++) {
  3612. u32 vbif_idx = sde_kms->catalog->vbif[i].id;
  3613. sde_kms->hw_vbif[i] = sde_hw_vbif_init(vbif_idx,
  3614. sde_kms->vbif[vbif_idx], sde_kms->catalog);
  3615. if (IS_ERR_OR_NULL(sde_kms->hw_vbif[vbif_idx])) {
  3616. rc = PTR_ERR(sde_kms->hw_vbif[vbif_idx]);
  3617. if (!sde_kms->hw_vbif[vbif_idx])
  3618. rc = -EINVAL;
  3619. SDE_ERROR("failed to init vbif %d: %d\n", vbif_idx, rc);
  3620. sde_kms->hw_vbif[vbif_idx] = NULL;
  3621. goto power_error;
  3622. }
  3623. }
  3624. if (sde_kms->catalog->uidle_cfg.uidle_rev) {
  3625. sde_kms->hw_uidle = sde_hw_uidle_init(UIDLE, sde_kms->mmio,
  3626. sde_kms->mmio_len, sde_kms->catalog);
  3627. if (IS_ERR_OR_NULL(sde_kms->hw_uidle)) {
  3628. rc = PTR_ERR(sde_kms->hw_uidle);
  3629. if (!sde_kms->hw_uidle)
  3630. rc = -EINVAL;
  3631. /* uidle is optional, so do not make it a fatal error */
  3632. SDE_ERROR("failed to init uidle rc:%d\n", rc);
  3633. sde_kms->hw_uidle = NULL;
  3634. rc = 0;
  3635. }
  3636. } else {
  3637. sde_kms->hw_uidle = NULL;
  3638. }
  3639. if (sde_kms->sid) {
  3640. sde_kms->hw_sid = sde_hw_sid_init(sde_kms->sid,
  3641. sde_kms->sid_len, sde_kms->catalog);
  3642. if (IS_ERR_OR_NULL(sde_kms->hw_sid)) {
  3643. rc = PTR_ERR(sde_kms->hw_sid);
  3644. SDE_ERROR("failed to init sid %ld\n", rc);
  3645. sde_kms->hw_sid = NULL;
  3646. goto power_error;
  3647. }
  3648. }
  3649. rc = sde_core_perf_init(&sde_kms->perf, dev, sde_kms->catalog,
  3650. &priv->phandle, "core_clk");
  3651. if (rc) {
  3652. SDE_ERROR("failed to init perf %d\n", rc);
  3653. goto perf_err;
  3654. }
  3655. /*
  3656. * _sde_kms_drm_obj_init should create the DRM related objects
  3657. * i.e. CRTCs, planes, encoders, connectors and so forth
  3658. */
  3659. rc = _sde_kms_drm_obj_init(sde_kms);
  3660. if (rc) {
  3661. SDE_ERROR("modeset init failed: %d\n", rc);
  3662. goto drm_obj_init_err;
  3663. }
  3664. return 0;
  3665. genpd_err:
  3666. drm_obj_init_err:
  3667. sde_core_perf_destroy(&sde_kms->perf);
  3668. hw_intr_init_err:
  3669. perf_err:
  3670. power_error:
  3671. return rc;
  3672. }
  3673. int sde_kms_get_io_resources(struct sde_kms *sde_kms, struct msm_io_res *io_res)
  3674. {
  3675. struct platform_device *pdev = to_platform_device(sde_kms->dev->dev);
  3676. int rc = 0;
  3677. rc = msm_dss_get_io_mem(pdev, &io_res->mem);
  3678. if (rc) {
  3679. SDE_ERROR("failed to get io mem for KMS, rc = %d\n", rc);
  3680. return rc;
  3681. }
  3682. rc = msm_dss_get_pmic_io_mem(pdev, &io_res->mem);
  3683. if (rc) {
  3684. SDE_ERROR("failed to get io mem for pmic, rc:%d\n", rc);
  3685. return rc;
  3686. }
  3687. rc = msm_dss_get_io_irq(pdev, &io_res->irq, HH_IRQ_LABEL_SDE);
  3688. if (rc) {
  3689. SDE_ERROR("failed to get io irq for KMS");
  3690. return rc;
  3691. }
  3692. return rc;
  3693. }
  3694. static int sde_kms_hw_init(struct msm_kms *kms)
  3695. {
  3696. struct sde_kms *sde_kms;
  3697. struct drm_device *dev;
  3698. struct msm_drm_private *priv;
  3699. struct platform_device *platformdev;
  3700. int i, irq_num, rc = -EINVAL;
  3701. if (!kms) {
  3702. SDE_ERROR("invalid kms\n");
  3703. goto end;
  3704. }
  3705. sde_kms = to_sde_kms(kms);
  3706. dev = sde_kms->dev;
  3707. if (!dev || !dev->dev) {
  3708. SDE_ERROR("invalid device\n");
  3709. goto end;
  3710. }
  3711. platformdev = to_platform_device(dev->dev);
  3712. priv = dev->dev_private;
  3713. if (!priv) {
  3714. SDE_ERROR("invalid private data\n");
  3715. goto end;
  3716. }
  3717. rc = _sde_kms_hw_init_ioremap(sde_kms, platformdev);
  3718. if (rc)
  3719. goto error;
  3720. rc = _sde_kms_get_splash_data(sde_kms, &sde_kms->splash_data);
  3721. if (rc)
  3722. SDE_DEBUG("sde splash data fetch failed: %d\n", rc);
  3723. rc = _sde_kms_hw_init_blocks(sde_kms, dev, priv);
  3724. if (rc)
  3725. goto error;
  3726. dev->mode_config.min_width = sde_kms->catalog->min_display_width;
  3727. dev->mode_config.min_height = sde_kms->catalog->min_display_height;
  3728. dev->mode_config.max_width = sde_kms->catalog->max_display_width;
  3729. dev->mode_config.max_height = sde_kms->catalog->max_display_height;
  3730. mutex_init(&sde_kms->secure_transition_lock);
  3731. atomic_set(&sde_kms->detach_sec_cb, 0);
  3732. atomic_set(&sde_kms->detach_all_cb, 0);
  3733. atomic_set(&sde_kms->irq_vote_count, 0);
  3734. /*
  3735. * Support format modifiers for compression etc.
  3736. */
  3737. dev->mode_config.allow_fb_modifiers = true;
  3738. /*
  3739. * Handle (re)initializations during power enable
  3740. */
  3741. sde_kms_handle_power_event(SDE_POWER_EVENT_POST_ENABLE, sde_kms);
  3742. sde_kms->power_event = sde_power_handle_register_event(&priv->phandle,
  3743. SDE_POWER_EVENT_POST_ENABLE |
  3744. SDE_POWER_EVENT_PRE_DISABLE,
  3745. sde_kms_handle_power_event, sde_kms, "kms");
  3746. if (sde_kms->splash_data.num_splash_displays) {
  3747. SDE_DEBUG("Skipping MDP Resources disable\n");
  3748. } else {
  3749. for (i = 0; i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++)
  3750. sde_power_data_bus_set_quota(&priv->phandle, i,
  3751. SDE_POWER_HANDLE_ENABLE_BUS_AB_QUOTA,
  3752. SDE_POWER_HANDLE_ENABLE_BUS_IB_QUOTA);
  3753. pm_runtime_put_sync(sde_kms->dev->dev);
  3754. }
  3755. sde_kms->affinity_notify.notify = sde_kms_irq_affinity_notify;
  3756. sde_kms->affinity_notify.release = sde_kms_irq_affinity_release;
  3757. irq_num = platform_get_irq(to_platform_device(sde_kms->dev->dev), 0);
  3758. SDE_DEBUG("Registering for notification of irq_num: %d\n", irq_num);
  3759. irq_set_affinity_notifier(irq_num, &sde_kms->affinity_notify);
  3760. if (sde_in_trusted_vm(sde_kms))
  3761. rc = sde_vm_trusted_init(sde_kms);
  3762. else
  3763. rc = sde_vm_primary_init(sde_kms);
  3764. if (rc) {
  3765. SDE_ERROR("failed to initialize VM ops, rc: %d\n", rc);
  3766. goto error;
  3767. }
  3768. return 0;
  3769. error:
  3770. _sde_kms_hw_destroy(sde_kms, platformdev);
  3771. end:
  3772. return rc;
  3773. }
  3774. struct msm_kms *sde_kms_init(struct drm_device *dev)
  3775. {
  3776. struct msm_drm_private *priv;
  3777. struct sde_kms *sde_kms;
  3778. if (!dev || !dev->dev_private) {
  3779. SDE_ERROR("drm device node invalid\n");
  3780. return ERR_PTR(-EINVAL);
  3781. }
  3782. priv = dev->dev_private;
  3783. sde_kms = kzalloc(sizeof(*sde_kms), GFP_KERNEL);
  3784. if (!sde_kms) {
  3785. SDE_ERROR("failed to allocate sde kms\n");
  3786. return ERR_PTR(-ENOMEM);
  3787. }
  3788. msm_kms_init(&sde_kms->base, &kms_funcs);
  3789. sde_kms->dev = dev;
  3790. return &sde_kms->base;
  3791. }
  3792. void sde_kms_vm_trusted_resource_deinit(struct sde_kms *sde_kms)
  3793. {
  3794. struct dsi_display *display;
  3795. struct sde_splash_display *handoff_display;
  3796. int i;
  3797. for (i = 0; i < sde_kms->dsi_display_count; i++) {
  3798. handoff_display = &sde_kms->splash_data.splash_display[i];
  3799. display = (struct dsi_display *)sde_kms->dsi_displays[i];
  3800. if (handoff_display->cont_splash_enabled)
  3801. _sde_kms_free_splash_display_data(sde_kms,
  3802. handoff_display);
  3803. dsi_display_set_active_state(display, false);
  3804. }
  3805. memset(&sde_kms->splash_data, 0, sizeof(struct sde_splash_data));
  3806. }
  3807. int sde_kms_vm_trusted_resource_init(struct sde_kms *sde_kms,
  3808. struct drm_atomic_state *state)
  3809. {
  3810. struct drm_device *dev;
  3811. struct msm_drm_private *priv;
  3812. struct sde_splash_display *handoff_display;
  3813. struct dsi_display *display;
  3814. int ret, i;
  3815. if (!sde_kms || !sde_kms->dev || !sde_kms->dev->dev_private) {
  3816. SDE_ERROR("invalid params\n");
  3817. return -EINVAL;
  3818. }
  3819. dev = sde_kms->dev;
  3820. priv = dev->dev_private;
  3821. sde_kms->splash_data.type = SDE_VM_HANDOFF;
  3822. sde_kms->splash_data.num_splash_displays = sde_kms->dsi_display_count;
  3823. ret = sde_rm_cont_splash_res_init(priv, &sde_kms->rm,
  3824. &sde_kms->splash_data, sde_kms->catalog);
  3825. if (ret) {
  3826. SDE_ERROR("invalid cont splash init, ret:%d\n", ret);
  3827. return -EINVAL;
  3828. }
  3829. for (i = 0; i < sde_kms->dsi_display_count; i++) {
  3830. handoff_display = &sde_kms->splash_data.splash_display[i];
  3831. display = (struct dsi_display *)sde_kms->dsi_displays[i];
  3832. if (!handoff_display->cont_splash_enabled || ret)
  3833. _sde_kms_free_splash_display_data(sde_kms,
  3834. handoff_display);
  3835. else
  3836. dsi_display_set_active_state(display, true);
  3837. }
  3838. if (sde_kms->splash_data.num_splash_displays != 1) {
  3839. SDE_ERROR("no. of displays not supported:%d\n",
  3840. sde_kms->splash_data.num_splash_displays);
  3841. goto error;
  3842. }
  3843. ret = sde_kms_cont_splash_config(&sde_kms->base, state);
  3844. if (ret) {
  3845. SDE_ERROR("error in setting handoff configs\n");
  3846. goto error;
  3847. }
  3848. /**
  3849. * fill-in vote for the continuous splash hanodff path, which will be
  3850. * removed on the successful first commit.
  3851. */
  3852. pm_runtime_get_sync(sde_kms->dev->dev);
  3853. return 0;
  3854. error:
  3855. return ret;
  3856. }
  3857. static int _sde_kms_register_events(struct msm_kms *kms,
  3858. struct drm_mode_object *obj, u32 event, bool en)
  3859. {
  3860. int ret = 0;
  3861. struct drm_crtc *crtc = NULL;
  3862. struct drm_connector *conn = NULL;
  3863. struct sde_kms *sde_kms = NULL;
  3864. struct sde_vm_ops *vm_ops;
  3865. if (!kms || !obj) {
  3866. SDE_ERROR("invalid argument kms %pK obj %pK\n", kms, obj);
  3867. return -EINVAL;
  3868. }
  3869. sde_kms = to_sde_kms(kms);
  3870. /* check vm ownership, if event registration requires HW access */
  3871. switch (obj->type) {
  3872. case DRM_MODE_OBJECT_CRTC:
  3873. vm_ops = sde_vm_get_ops(sde_kms);
  3874. sde_vm_lock(sde_kms);
  3875. if (vm_ops && vm_ops->vm_owns_hw
  3876. && !vm_ops->vm_owns_hw(sde_kms)) {
  3877. sde_vm_unlock(sde_kms);
  3878. SDE_DEBUG("HW is owned by other VM\n");
  3879. return -EACCES;
  3880. }
  3881. crtc = obj_to_crtc(obj);
  3882. ret = sde_crtc_register_custom_event(sde_kms, crtc, event, en);
  3883. sde_vm_unlock(sde_kms);
  3884. break;
  3885. case DRM_MODE_OBJECT_CONNECTOR:
  3886. conn = obj_to_connector(obj);
  3887. ret = sde_connector_register_custom_event(sde_kms, conn, event,
  3888. en);
  3889. break;
  3890. }
  3891. return ret;
  3892. }
  3893. int sde_kms_handle_recovery(struct drm_encoder *encoder)
  3894. {
  3895. SDE_EVT32(DRMID(encoder), MSM_ENC_ACTIVE_REGION);
  3896. return sde_encoder_wait_for_event(encoder, MSM_ENC_ACTIVE_REGION);
  3897. }