sde_encoder.c 143 KB

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  1. /*
  2. * Copyright (c) 2014-2020, The Linux Foundation. All rights reserved.
  3. * Copyright (C) 2013 Red Hat
  4. * Author: Rob Clark <[email protected]>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  19. #include <linux/kthread.h>
  20. #include <linux/debugfs.h>
  21. #include <linux/input.h>
  22. #include <linux/seq_file.h>
  23. #include <linux/sde_rsc.h>
  24. #include "msm_drv.h"
  25. #include "sde_kms.h"
  26. #include <drm/drm_crtc.h>
  27. #include <drm/drm_probe_helper.h>
  28. #include "sde_hwio.h"
  29. #include "sde_hw_catalog.h"
  30. #include "sde_hw_intf.h"
  31. #include "sde_hw_ctl.h"
  32. #include "sde_formats.h"
  33. #include "sde_encoder.h"
  34. #include "sde_encoder_phys.h"
  35. #include "sde_hw_dsc.h"
  36. #include "sde_crtc.h"
  37. #include "sde_trace.h"
  38. #include "sde_core_irq.h"
  39. #include "sde_hw_top.h"
  40. #include "sde_hw_qdss.h"
  41. #include "sde_encoder_dce.h"
  42. #define SDE_DEBUG_ENC(e, fmt, ...) SDE_DEBUG("enc%d " fmt,\
  43. (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
  44. #define SDE_ERROR_ENC(e, fmt, ...) SDE_ERROR("enc%d " fmt,\
  45. (e) ? (e)->base.base.id : -1, ##__VA_ARGS__)
  46. #define SDE_DEBUG_PHYS(p, fmt, ...) SDE_DEBUG("enc%d intf%d pp%d " fmt,\
  47. (p) ? (p)->parent->base.id : -1, \
  48. (p) ? (p)->intf_idx - INTF_0 : -1, \
  49. (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \
  50. ##__VA_ARGS__)
  51. #define SDE_ERROR_PHYS(p, fmt, ...) SDE_ERROR("enc%d intf%d pp%d " fmt,\
  52. (p) ? (p)->parent->base.id : -1, \
  53. (p) ? (p)->intf_idx - INTF_0 : -1, \
  54. (p) ? ((p)->hw_pp ? (p)->hw_pp->idx - PINGPONG_0 : -1) : -1, \
  55. ##__VA_ARGS__)
  56. #define MISR_BUFF_SIZE 256
  57. #define IDLE_SHORT_TIMEOUT 1
  58. #define EVT_TIME_OUT_SPLIT 2
  59. /* Maximum number of VSYNC wait attempts for RSC state transition */
  60. #define MAX_RSC_WAIT 5
  61. #define TOPOLOGY_DUALPIPE_MERGE_MODE(x) \
  62. (((x) == SDE_RM_TOPOLOGY_DUALPIPE_DSCMERGE) || \
  63. ((x) == SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE) || \
  64. ((x) == SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE_VDC) || \
  65. ((x) == SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC))
  66. /**
  67. * enum sde_enc_rc_events - events for resource control state machine
  68. * @SDE_ENC_RC_EVENT_KICKOFF:
  69. * This event happens at NORMAL priority.
  70. * Event that signals the start of the transfer. When this event is
  71. * received, enable MDP/DSI core clocks and request RSC with CMD state.
  72. * Regardless of the previous state, the resource should be in ON state
  73. * at the end of this event. At the end of this event, a delayed work is
  74. * scheduled to go to IDLE_PC state after IDLE_POWERCOLLAPSE_DURATION
  75. * ktime.
  76. * @SDE_ENC_RC_EVENT_PRE_STOP:
  77. * This event happens at NORMAL priority.
  78. * This event, when received during the ON state, set RSC to IDLE, and
  79. * and leave the RC STATE in the PRE_OFF state.
  80. * It should be followed by the STOP event as part of encoder disable.
  81. * If received during IDLE or OFF states, it will do nothing.
  82. * @SDE_ENC_RC_EVENT_STOP:
  83. * This event happens at NORMAL priority.
  84. * When this event is received, disable all the MDP/DSI core clocks, and
  85. * disable IRQs. It should be called from the PRE_OFF or IDLE states.
  86. * IDLE is expected when IDLE_PC has run, and PRE_OFF did nothing.
  87. * PRE_OFF is expected when PRE_STOP was executed during the ON state.
  88. * Resource state should be in OFF at the end of the event.
  89. * @SDE_ENC_RC_EVENT_PRE_MODESET:
  90. * This event happens at NORMAL priority from a work item.
  91. * Event signals that there is a seamless mode switch is in prgoress. A
  92. * client needs to turn of only irq - leave clocks ON to reduce the mode
  93. * switch latency.
  94. * @SDE_ENC_RC_EVENT_POST_MODESET:
  95. * This event happens at NORMAL priority from a work item.
  96. * Event signals that seamless mode switch is complete and resources are
  97. * acquired. Clients wants to turn on the irq again and update the rsc
  98. * with new vtotal.
  99. * @SDE_ENC_RC_EVENT_ENTER_IDLE:
  100. * This event happens at NORMAL priority from a work item.
  101. * Event signals that there were no frame updates for
  102. * IDLE_POWERCOLLAPSE_DURATION time. This would disable MDP/DSI core clocks
  103. * and request RSC with IDLE state and change the resource state to IDLE.
  104. * @SDE_ENC_RC_EVENT_EARLY_WAKEUP:
  105. * This event is triggered from the input event thread when touch event is
  106. * received from the input device. On receiving this event,
  107. * - If the device is in SDE_ENC_RC_STATE_IDLE state, it turns ON the
  108. clocks and enable RSC.
  109. * - If the device is in SDE_ENC_RC_STATE_ON state, it resets the delayed
  110. * off work since a new commit is imminent.
  111. */
  112. enum sde_enc_rc_events {
  113. SDE_ENC_RC_EVENT_KICKOFF = 1,
  114. SDE_ENC_RC_EVENT_PRE_STOP,
  115. SDE_ENC_RC_EVENT_STOP,
  116. SDE_ENC_RC_EVENT_PRE_MODESET,
  117. SDE_ENC_RC_EVENT_POST_MODESET,
  118. SDE_ENC_RC_EVENT_ENTER_IDLE,
  119. SDE_ENC_RC_EVENT_EARLY_WAKEUP,
  120. };
  121. void sde_encoder_uidle_enable(struct drm_encoder *drm_enc, bool enable)
  122. {
  123. struct sde_encoder_virt *sde_enc;
  124. int i;
  125. sde_enc = to_sde_encoder_virt(drm_enc);
  126. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  127. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  128. if (phys && phys->hw_ctl && phys->hw_ctl->ops.uidle_enable) {
  129. SDE_EVT32(DRMID(drm_enc), enable);
  130. phys->hw_ctl->ops.uidle_enable(phys->hw_ctl, enable);
  131. }
  132. }
  133. }
  134. static void _sde_encoder_pm_qos_add_request(struct drm_encoder *drm_enc)
  135. {
  136. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  137. struct msm_drm_private *priv;
  138. struct sde_kms *sde_kms;
  139. struct device *cpu_dev;
  140. struct cpumask *cpu_mask = NULL;
  141. int cpu = 0;
  142. u32 cpu_dma_latency;
  143. priv = drm_enc->dev->dev_private;
  144. sde_kms = to_sde_kms(priv->kms);
  145. if (!sde_kms->catalog || !sde_kms->catalog->perf.cpu_mask)
  146. return;
  147. cpu_dma_latency = sde_kms->catalog->perf.cpu_dma_latency;
  148. cpumask_clear(&sde_enc->valid_cpu_mask);
  149. if (sde_enc->mode_info.frame_rate > FPS60)
  150. cpu_mask = to_cpumask(&sde_kms->catalog->perf.cpu_mask_perf);
  151. if (!cpu_mask &&
  152. sde_encoder_check_curr_mode(drm_enc,
  153. MSM_DISPLAY_CMD_MODE))
  154. cpu_mask = to_cpumask(&sde_kms->catalog->perf.cpu_mask);
  155. if (!cpu_mask)
  156. return;
  157. for_each_cpu(cpu, cpu_mask) {
  158. cpu_dev = get_cpu_device(cpu);
  159. if (!cpu_dev) {
  160. SDE_ERROR("%s: failed to get cpu%d device\n", __func__,
  161. cpu);
  162. return;
  163. }
  164. cpumask_set_cpu(cpu, &sde_enc->valid_cpu_mask);
  165. dev_pm_qos_add_request(cpu_dev,
  166. &sde_enc->pm_qos_cpu_req[cpu],
  167. DEV_PM_QOS_RESUME_LATENCY, cpu_dma_latency);
  168. SDE_EVT32_VERBOSE(DRMID(drm_enc), cpu_dma_latency, cpu);
  169. }
  170. }
  171. static void _sde_encoder_pm_qos_remove_request(struct drm_encoder *drm_enc)
  172. {
  173. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  174. struct device *cpu_dev;
  175. int cpu = 0;
  176. for_each_cpu(cpu, &sde_enc->valid_cpu_mask) {
  177. cpu_dev = get_cpu_device(cpu);
  178. if (!cpu_dev) {
  179. SDE_ERROR("%s: failed to get cpu%d device\n", __func__,
  180. cpu);
  181. continue;
  182. }
  183. dev_pm_qos_remove_request(&sde_enc->pm_qos_cpu_req[cpu]);
  184. SDE_EVT32_VERBOSE(DRMID(drm_enc), cpu);
  185. }
  186. cpumask_clear(&sde_enc->valid_cpu_mask);
  187. }
  188. static bool _sde_encoder_is_autorefresh_enabled(
  189. struct sde_encoder_virt *sde_enc)
  190. {
  191. struct drm_connector *drm_conn;
  192. if (!sde_enc->cur_master ||
  193. !(sde_enc->disp_info.capabilities & MSM_DISPLAY_CAP_CMD_MODE))
  194. return false;
  195. drm_conn = sde_enc->cur_master->connector;
  196. if (!drm_conn || !drm_conn->state)
  197. return false;
  198. return sde_connector_get_property(drm_conn->state,
  199. CONNECTOR_PROP_AUTOREFRESH) ? true : false;
  200. }
  201. static void sde_configure_qdss(struct sde_encoder_virt *sde_enc,
  202. struct sde_hw_qdss *hw_qdss,
  203. struct sde_encoder_phys *phys, bool enable)
  204. {
  205. if (sde_enc->qdss_status == enable)
  206. return;
  207. sde_enc->qdss_status = enable;
  208. phys->hw_mdptop->ops.set_mdp_hw_events(phys->hw_mdptop,
  209. sde_enc->qdss_status);
  210. hw_qdss->ops.enable_qdss_events(hw_qdss, sde_enc->qdss_status);
  211. }
  212. static int _sde_encoder_wait_timeout(int32_t drm_id, int32_t hw_id,
  213. s64 timeout_ms, struct sde_encoder_wait_info *info)
  214. {
  215. int rc = 0;
  216. s64 wait_time_jiffies = msecs_to_jiffies(timeout_ms);
  217. ktime_t cur_ktime;
  218. ktime_t exp_ktime = ktime_add_ms(ktime_get(), timeout_ms);
  219. do {
  220. rc = wait_event_timeout(*(info->wq),
  221. atomic_read(info->atomic_cnt) == info->count_check,
  222. wait_time_jiffies);
  223. cur_ktime = ktime_get();
  224. SDE_EVT32(drm_id, hw_id, rc, ktime_to_ms(cur_ktime),
  225. timeout_ms, atomic_read(info->atomic_cnt),
  226. info->count_check);
  227. /* If we timed out, counter is valid and time is less, wait again */
  228. } while ((atomic_read(info->atomic_cnt) != info->count_check) &&
  229. (rc == 0) &&
  230. (ktime_compare_safe(exp_ktime, cur_ktime) > 0));
  231. return rc;
  232. }
  233. bool sde_encoder_is_primary_display(struct drm_encoder *drm_enc)
  234. {
  235. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  236. return sde_enc &&
  237. (sde_enc->disp_info.display_type ==
  238. SDE_CONNECTOR_PRIMARY);
  239. }
  240. bool sde_encoder_is_dsi_display(struct drm_encoder *drm_enc)
  241. {
  242. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  243. return sde_enc &&
  244. (sde_enc->disp_info.intf_type == DRM_MODE_CONNECTOR_DSI);
  245. }
  246. int sde_encoder_in_cont_splash(struct drm_encoder *drm_enc)
  247. {
  248. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  249. return sde_enc && sde_enc->cur_master &&
  250. sde_enc->cur_master->cont_splash_enabled;
  251. }
  252. void sde_encoder_helper_report_irq_timeout(struct sde_encoder_phys *phys_enc,
  253. enum sde_intr_idx intr_idx)
  254. {
  255. SDE_EVT32(DRMID(phys_enc->parent),
  256. phys_enc->intf_idx - INTF_0,
  257. phys_enc->hw_pp->idx - PINGPONG_0,
  258. intr_idx);
  259. SDE_ERROR_PHYS(phys_enc, "irq %d timeout\n", intr_idx);
  260. if (phys_enc->parent_ops.handle_frame_done)
  261. phys_enc->parent_ops.handle_frame_done(
  262. phys_enc->parent, phys_enc,
  263. SDE_ENCODER_FRAME_EVENT_ERROR);
  264. }
  265. int sde_encoder_helper_wait_for_irq(struct sde_encoder_phys *phys_enc,
  266. enum sde_intr_idx intr_idx,
  267. struct sde_encoder_wait_info *wait_info)
  268. {
  269. struct sde_encoder_irq *irq;
  270. u32 irq_status;
  271. int ret, i;
  272. if (!phys_enc || !wait_info || intr_idx >= INTR_IDX_MAX) {
  273. SDE_ERROR("invalid params\n");
  274. return -EINVAL;
  275. }
  276. irq = &phys_enc->irq[intr_idx];
  277. /* note: do master / slave checking outside */
  278. /* return EWOULDBLOCK since we know the wait isn't necessary */
  279. if (phys_enc->enable_state == SDE_ENC_DISABLED) {
  280. SDE_ERROR_PHYS(phys_enc, "encoder is disabled\n");
  281. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  282. irq->irq_idx, intr_idx, SDE_EVTLOG_ERROR);
  283. return -EWOULDBLOCK;
  284. }
  285. if (irq->irq_idx < 0) {
  286. SDE_DEBUG_PHYS(phys_enc, "irq %s hw %d disabled, skip wait\n",
  287. irq->name, irq->hw_idx);
  288. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  289. irq->irq_idx);
  290. return 0;
  291. }
  292. SDE_DEBUG_PHYS(phys_enc, "pending_cnt %d\n",
  293. atomic_read(wait_info->atomic_cnt));
  294. SDE_EVT32_VERBOSE(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  295. irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0,
  296. atomic_read(wait_info->atomic_cnt), SDE_EVTLOG_FUNC_ENTRY);
  297. /*
  298. * Some module X may disable interrupt for longer duration
  299. * and it may trigger all interrupts including timer interrupt
  300. * when module X again enable the interrupt.
  301. * That may cause interrupt wait timeout API in this API.
  302. * It is handled by split the wait timer in two halves.
  303. */
  304. for (i = 0; i < EVT_TIME_OUT_SPLIT; i++) {
  305. ret = _sde_encoder_wait_timeout(DRMID(phys_enc->parent),
  306. irq->hw_idx,
  307. (wait_info->timeout_ms/EVT_TIME_OUT_SPLIT),
  308. wait_info);
  309. if (ret)
  310. break;
  311. }
  312. if (ret <= 0) {
  313. irq_status = sde_core_irq_read(phys_enc->sde_kms,
  314. irq->irq_idx, true);
  315. if (irq_status) {
  316. unsigned long flags;
  317. SDE_EVT32(DRMID(phys_enc->parent), intr_idx,
  318. irq->hw_idx, irq->irq_idx,
  319. phys_enc->hw_pp->idx - PINGPONG_0,
  320. atomic_read(wait_info->atomic_cnt));
  321. SDE_DEBUG_PHYS(phys_enc,
  322. "done but irq %d not triggered\n",
  323. irq->irq_idx);
  324. local_irq_save(flags);
  325. irq->cb.func(phys_enc, irq->irq_idx);
  326. local_irq_restore(flags);
  327. ret = 0;
  328. } else {
  329. ret = -ETIMEDOUT;
  330. SDE_EVT32(DRMID(phys_enc->parent), intr_idx,
  331. irq->hw_idx, irq->irq_idx,
  332. phys_enc->hw_pp->idx - PINGPONG_0,
  333. atomic_read(wait_info->atomic_cnt), irq_status,
  334. SDE_EVTLOG_ERROR);
  335. }
  336. } else {
  337. ret = 0;
  338. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  339. irq->irq_idx, phys_enc->hw_pp->idx - PINGPONG_0,
  340. atomic_read(wait_info->atomic_cnt));
  341. }
  342. SDE_EVT32_VERBOSE(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  343. irq->irq_idx, ret, phys_enc->hw_pp->idx - PINGPONG_0,
  344. atomic_read(wait_info->atomic_cnt), SDE_EVTLOG_FUNC_EXIT);
  345. return ret;
  346. }
  347. int sde_encoder_helper_register_irq(struct sde_encoder_phys *phys_enc,
  348. enum sde_intr_idx intr_idx)
  349. {
  350. struct sde_encoder_irq *irq;
  351. int ret = 0;
  352. if (!phys_enc || intr_idx >= INTR_IDX_MAX) {
  353. SDE_ERROR("invalid params\n");
  354. return -EINVAL;
  355. }
  356. irq = &phys_enc->irq[intr_idx];
  357. if (irq->irq_idx >= 0) {
  358. SDE_DEBUG_PHYS(phys_enc,
  359. "skipping already registered irq %s type %d\n",
  360. irq->name, irq->intr_type);
  361. return 0;
  362. }
  363. irq->irq_idx = sde_core_irq_idx_lookup(phys_enc->sde_kms,
  364. irq->intr_type, irq->hw_idx);
  365. if (irq->irq_idx < 0) {
  366. SDE_ERROR_PHYS(phys_enc,
  367. "failed to lookup IRQ index for %s type:%d\n",
  368. irq->name, irq->intr_type);
  369. return -EINVAL;
  370. }
  371. ret = sde_core_irq_register_callback(phys_enc->sde_kms, irq->irq_idx,
  372. &irq->cb);
  373. if (ret) {
  374. SDE_ERROR_PHYS(phys_enc,
  375. "failed to register IRQ callback for %s\n",
  376. irq->name);
  377. irq->irq_idx = -EINVAL;
  378. return ret;
  379. }
  380. ret = sde_core_irq_enable(phys_enc->sde_kms, &irq->irq_idx, 1);
  381. if (ret) {
  382. SDE_ERROR_PHYS(phys_enc,
  383. "enable IRQ for intr:%s failed, irq_idx %d\n",
  384. irq->name, irq->irq_idx);
  385. sde_core_irq_unregister_callback(phys_enc->sde_kms,
  386. irq->irq_idx, &irq->cb);
  387. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  388. irq->irq_idx, SDE_EVTLOG_ERROR);
  389. irq->irq_idx = -EINVAL;
  390. return ret;
  391. }
  392. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx, irq->irq_idx);
  393. SDE_DEBUG_PHYS(phys_enc, "registered irq %s idx: %d\n",
  394. irq->name, irq->irq_idx);
  395. return ret;
  396. }
  397. int sde_encoder_helper_unregister_irq(struct sde_encoder_phys *phys_enc,
  398. enum sde_intr_idx intr_idx)
  399. {
  400. struct sde_encoder_irq *irq;
  401. int ret;
  402. if (!phys_enc) {
  403. SDE_ERROR("invalid encoder\n");
  404. return -EINVAL;
  405. }
  406. irq = &phys_enc->irq[intr_idx];
  407. /* silently skip irqs that weren't registered */
  408. if (irq->irq_idx < 0) {
  409. SDE_ERROR(
  410. "extra unregister irq, enc%d intr_idx:0x%x hw_idx:0x%x irq_idx:0x%x\n",
  411. DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  412. irq->irq_idx);
  413. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  414. irq->irq_idx, SDE_EVTLOG_ERROR);
  415. return 0;
  416. }
  417. ret = sde_core_irq_disable(phys_enc->sde_kms, &irq->irq_idx, 1);
  418. if (ret)
  419. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  420. irq->irq_idx, ret, SDE_EVTLOG_ERROR);
  421. ret = sde_core_irq_unregister_callback(phys_enc->sde_kms, irq->irq_idx,
  422. &irq->cb);
  423. if (ret)
  424. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx,
  425. irq->irq_idx, ret, SDE_EVTLOG_ERROR);
  426. SDE_EVT32(DRMID(phys_enc->parent), intr_idx, irq->hw_idx, irq->irq_idx);
  427. SDE_DEBUG_PHYS(phys_enc, "unregistered %d\n", irq->irq_idx);
  428. irq->irq_idx = -EINVAL;
  429. return 0;
  430. }
  431. void sde_encoder_get_hw_resources(struct drm_encoder *drm_enc,
  432. struct sde_encoder_hw_resources *hw_res,
  433. struct drm_connector_state *conn_state)
  434. {
  435. struct sde_encoder_virt *sde_enc = NULL;
  436. struct msm_mode_info mode_info;
  437. int i = 0;
  438. if (!hw_res || !drm_enc || !conn_state) {
  439. SDE_ERROR("invalid argument(s), drm_enc %d, res %d, state %d\n",
  440. !drm_enc, !hw_res, !conn_state);
  441. return;
  442. }
  443. sde_enc = to_sde_encoder_virt(drm_enc);
  444. SDE_DEBUG_ENC(sde_enc, "\n");
  445. /* Query resources used by phys encs, expected to be without overlap */
  446. memset(hw_res, 0, sizeof(*hw_res));
  447. hw_res->display_num_of_h_tiles = sde_enc->display_num_of_h_tiles;
  448. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  449. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  450. if (phys && phys->ops.get_hw_resources)
  451. phys->ops.get_hw_resources(phys, hw_res, conn_state);
  452. }
  453. /*
  454. * NOTE: Do not use sde_encoder_get_mode_info here as this function is
  455. * called from atomic_check phase. Use the below API to get mode
  456. * information of the temporary conn_state passed
  457. */
  458. sde_connector_state_get_mode_info(conn_state, &mode_info);
  459. hw_res->topology = mode_info.topology;
  460. hw_res->comp_info = &sde_enc->mode_info.comp_info;
  461. hw_res->display_type = sde_enc->disp_info.display_type;
  462. }
  463. void sde_encoder_destroy(struct drm_encoder *drm_enc)
  464. {
  465. struct sde_encoder_virt *sde_enc = NULL;
  466. int i = 0;
  467. if (!drm_enc) {
  468. SDE_ERROR("invalid encoder\n");
  469. return;
  470. }
  471. sde_enc = to_sde_encoder_virt(drm_enc);
  472. SDE_DEBUG_ENC(sde_enc, "\n");
  473. mutex_lock(&sde_enc->enc_lock);
  474. sde_rsc_client_destroy(sde_enc->rsc_client);
  475. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  476. struct sde_encoder_phys *phys;
  477. phys = sde_enc->phys_vid_encs[i];
  478. if (phys && phys->ops.destroy) {
  479. phys->ops.destroy(phys);
  480. --sde_enc->num_phys_encs;
  481. sde_enc->phys_encs[i] = NULL;
  482. }
  483. phys = sde_enc->phys_cmd_encs[i];
  484. if (phys && phys->ops.destroy) {
  485. phys->ops.destroy(phys);
  486. --sde_enc->num_phys_encs;
  487. sde_enc->phys_encs[i] = NULL;
  488. }
  489. }
  490. if (sde_enc->num_phys_encs)
  491. SDE_ERROR_ENC(sde_enc, "expected 0 num_phys_encs not %d\n",
  492. sde_enc->num_phys_encs);
  493. sde_enc->num_phys_encs = 0;
  494. mutex_unlock(&sde_enc->enc_lock);
  495. drm_encoder_cleanup(drm_enc);
  496. mutex_destroy(&sde_enc->enc_lock);
  497. kfree(sde_enc->input_handler);
  498. sde_enc->input_handler = NULL;
  499. kfree(sde_enc);
  500. }
  501. void sde_encoder_helper_update_intf_cfg(
  502. struct sde_encoder_phys *phys_enc)
  503. {
  504. struct sde_encoder_virt *sde_enc;
  505. struct sde_hw_intf_cfg_v1 *intf_cfg;
  506. enum sde_3d_blend_mode mode_3d;
  507. if (!phys_enc || !phys_enc->hw_pp) {
  508. SDE_ERROR("invalid args, encoder %d\n", !phys_enc);
  509. return;
  510. }
  511. sde_enc = to_sde_encoder_virt(phys_enc->parent);
  512. intf_cfg = &sde_enc->cur_master->intf_cfg_v1;
  513. SDE_DEBUG_ENC(sde_enc,
  514. "intf_cfg updated for %d at idx %d\n",
  515. phys_enc->intf_idx,
  516. intf_cfg->intf_count);
  517. /* setup interface configuration */
  518. if (intf_cfg->intf_count >= MAX_INTF_PER_CTL_V1) {
  519. pr_err("invalid inf_count %d\n", intf_cfg->intf_count);
  520. return;
  521. }
  522. intf_cfg->intf[intf_cfg->intf_count++] = phys_enc->intf_idx;
  523. if (phys_enc == sde_enc->cur_master) {
  524. if (sde_enc->cur_master->intf_mode == INTF_MODE_CMD)
  525. intf_cfg->intf_mode_sel = SDE_CTL_MODE_SEL_CMD;
  526. else
  527. intf_cfg->intf_mode_sel = SDE_CTL_MODE_SEL_VID;
  528. }
  529. /* configure this interface as master for split display */
  530. if (phys_enc->split_role == ENC_ROLE_MASTER)
  531. intf_cfg->intf_master = phys_enc->hw_intf->idx;
  532. /* setup which pp blk will connect to this intf */
  533. if (phys_enc->hw_intf->ops.bind_pingpong_blk)
  534. phys_enc->hw_intf->ops.bind_pingpong_blk(
  535. phys_enc->hw_intf,
  536. true,
  537. phys_enc->hw_pp->idx);
  538. /*setup merge_3d configuration */
  539. mode_3d = sde_encoder_helper_get_3d_blend_mode(phys_enc);
  540. if (mode_3d && phys_enc->hw_pp->merge_3d &&
  541. intf_cfg->merge_3d_count < MAX_MERGE_3D_PER_CTL_V1)
  542. intf_cfg->merge_3d[intf_cfg->merge_3d_count++] =
  543. phys_enc->hw_pp->merge_3d->idx;
  544. if (phys_enc->hw_pp->ops.setup_3d_mode)
  545. phys_enc->hw_pp->ops.setup_3d_mode(phys_enc->hw_pp,
  546. mode_3d);
  547. }
  548. void sde_encoder_helper_split_config(
  549. struct sde_encoder_phys *phys_enc,
  550. enum sde_intf interface)
  551. {
  552. struct sde_encoder_virt *sde_enc;
  553. struct split_pipe_cfg *cfg;
  554. struct sde_hw_mdp *hw_mdptop;
  555. enum sde_rm_topology_name topology;
  556. struct msm_display_info *disp_info;
  557. if (!phys_enc || !phys_enc->hw_mdptop || !phys_enc->parent) {
  558. SDE_ERROR("invalid arg(s), encoder %d\n", !phys_enc);
  559. return;
  560. }
  561. sde_enc = to_sde_encoder_virt(phys_enc->parent);
  562. hw_mdptop = phys_enc->hw_mdptop;
  563. disp_info = &sde_enc->disp_info;
  564. cfg = &phys_enc->hw_intf->cfg;
  565. memset(cfg, 0, sizeof(*cfg));
  566. if (disp_info->intf_type != DRM_MODE_CONNECTOR_DSI)
  567. return;
  568. if (disp_info->capabilities & MSM_DISPLAY_SPLIT_LINK)
  569. cfg->split_link_en = true;
  570. /**
  571. * disable split modes since encoder will be operating in as the only
  572. * encoder, either for the entire use case in the case of, for example,
  573. * single DSI, or for this frame in the case of left/right only partial
  574. * update.
  575. */
  576. if (phys_enc->split_role == ENC_ROLE_SOLO) {
  577. if (hw_mdptop->ops.setup_split_pipe)
  578. hw_mdptop->ops.setup_split_pipe(hw_mdptop, cfg);
  579. if (hw_mdptop->ops.setup_pp_split)
  580. hw_mdptop->ops.setup_pp_split(hw_mdptop, cfg);
  581. return;
  582. }
  583. cfg->en = true;
  584. cfg->mode = phys_enc->intf_mode;
  585. cfg->intf = interface;
  586. if (cfg->en && phys_enc->ops.needs_single_flush &&
  587. phys_enc->ops.needs_single_flush(phys_enc))
  588. cfg->split_flush_en = true;
  589. topology = sde_connector_get_topology_name(phys_enc->connector);
  590. if (topology == SDE_RM_TOPOLOGY_PPSPLIT)
  591. cfg->pp_split_slave = cfg->intf;
  592. else
  593. cfg->pp_split_slave = INTF_MAX;
  594. if (phys_enc->split_role == ENC_ROLE_MASTER) {
  595. SDE_DEBUG_ENC(sde_enc, "enable %d\n", cfg->en);
  596. if (hw_mdptop->ops.setup_split_pipe)
  597. hw_mdptop->ops.setup_split_pipe(hw_mdptop, cfg);
  598. } else if (sde_enc->hw_pp[0]) {
  599. /*
  600. * slave encoder
  601. * - determine split index from master index,
  602. * assume master is first pp
  603. */
  604. cfg->pp_split_index = sde_enc->hw_pp[0]->idx - PINGPONG_0;
  605. SDE_DEBUG_ENC(sde_enc, "master using pp%d\n",
  606. cfg->pp_split_index);
  607. if (hw_mdptop->ops.setup_pp_split)
  608. hw_mdptop->ops.setup_pp_split(hw_mdptop, cfg);
  609. }
  610. }
  611. bool sde_encoder_in_clone_mode(struct drm_encoder *drm_enc)
  612. {
  613. struct sde_encoder_virt *sde_enc;
  614. int i = 0;
  615. if (!drm_enc)
  616. return false;
  617. sde_enc = to_sde_encoder_virt(drm_enc);
  618. if (!sde_enc)
  619. return false;
  620. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  621. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  622. if (phys && phys->in_clone_mode)
  623. return true;
  624. }
  625. return false;
  626. }
  627. static int _sde_encoder_atomic_check_phys_enc(struct sde_encoder_virt *sde_enc,
  628. struct drm_crtc_state *crtc_state,
  629. struct drm_connector_state *conn_state)
  630. {
  631. const struct drm_display_mode *mode;
  632. struct drm_display_mode *adj_mode;
  633. int i = 0;
  634. int ret = 0;
  635. mode = &crtc_state->mode;
  636. adj_mode = &crtc_state->adjusted_mode;
  637. /* perform atomic check on the first physical encoder (master) */
  638. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  639. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  640. if (phys && phys->ops.atomic_check)
  641. ret = phys->ops.atomic_check(phys, crtc_state,
  642. conn_state);
  643. else if (phys && phys->ops.mode_fixup)
  644. if (!phys->ops.mode_fixup(phys, mode, adj_mode))
  645. ret = -EINVAL;
  646. if (ret) {
  647. SDE_ERROR_ENC(sde_enc,
  648. "mode unsupported, phys idx %d\n", i);
  649. break;
  650. }
  651. }
  652. return ret;
  653. }
  654. static int _sde_encoder_atomic_check_pu_roi(struct sde_encoder_virt *sde_enc,
  655. struct drm_crtc_state *crtc_state,
  656. struct drm_connector_state *conn_state,
  657. struct sde_connector_state *sde_conn_state,
  658. struct sde_crtc_state *sde_crtc_state)
  659. {
  660. int ret = 0;
  661. if (crtc_state->mode_changed || crtc_state->active_changed) {
  662. struct sde_rect mode_roi, roi;
  663. mode_roi.x = 0;
  664. mode_roi.y = 0;
  665. mode_roi.w = crtc_state->adjusted_mode.hdisplay;
  666. mode_roi.h = crtc_state->adjusted_mode.vdisplay;
  667. if (sde_conn_state->rois.num_rects) {
  668. sde_kms_rect_merge_rectangles(
  669. &sde_conn_state->rois, &roi);
  670. if (!sde_kms_rect_is_equal(&mode_roi, &roi)) {
  671. SDE_ERROR_ENC(sde_enc,
  672. "roi (%d,%d,%d,%d) on connector invalid during modeset\n",
  673. roi.x, roi.y, roi.w, roi.h);
  674. ret = -EINVAL;
  675. }
  676. }
  677. if (sde_crtc_state->user_roi_list.num_rects) {
  678. sde_kms_rect_merge_rectangles(
  679. &sde_crtc_state->user_roi_list, &roi);
  680. if (!sde_kms_rect_is_equal(&mode_roi, &roi)) {
  681. SDE_ERROR_ENC(sde_enc,
  682. "roi (%d,%d,%d,%d) on crtc invalid during modeset\n",
  683. roi.x, roi.y, roi.w, roi.h);
  684. ret = -EINVAL;
  685. }
  686. }
  687. }
  688. return ret;
  689. }
  690. static int _sde_encoder_atomic_check_reserve(struct drm_encoder *drm_enc,
  691. struct drm_crtc_state *crtc_state,
  692. struct drm_connector_state *conn_state,
  693. struct sde_encoder_virt *sde_enc, struct sde_kms *sde_kms,
  694. struct sde_connector *sde_conn,
  695. struct sde_connector_state *sde_conn_state)
  696. {
  697. int ret = 0;
  698. struct drm_display_mode *adj_mode = &crtc_state->adjusted_mode;
  699. if (sde_conn && drm_atomic_crtc_needs_modeset(crtc_state)) {
  700. struct msm_display_topology *topology = NULL;
  701. ret = sde_connector_get_mode_info(&sde_conn->base,
  702. adj_mode, &sde_conn_state->mode_info);
  703. if (ret) {
  704. SDE_ERROR_ENC(sde_enc,
  705. "failed to get mode info, rc = %d\n", ret);
  706. return ret;
  707. }
  708. if (sde_conn_state->mode_info.comp_info.comp_type &&
  709. sde_conn_state->mode_info.comp_info.comp_ratio >=
  710. MSM_DISPLAY_COMPRESSION_RATIO_MAX) {
  711. SDE_ERROR_ENC(sde_enc,
  712. "invalid compression ratio: %d\n",
  713. sde_conn_state->mode_info.comp_info.comp_ratio);
  714. ret = -EINVAL;
  715. return ret;
  716. }
  717. /* Reserve dynamic resources, indicating atomic_check phase */
  718. ret = sde_rm_reserve(&sde_kms->rm, drm_enc, crtc_state,
  719. conn_state, true);
  720. if (ret) {
  721. SDE_ERROR_ENC(sde_enc,
  722. "RM failed to reserve resources, rc = %d\n",
  723. ret);
  724. return ret;
  725. }
  726. /**
  727. * Update connector state with the topology selected for the
  728. * resource set validated. Reset the topology if we are
  729. * de-activating crtc.
  730. */
  731. if (crtc_state->active)
  732. topology = &sde_conn_state->mode_info.topology;
  733. ret = sde_rm_update_topology(conn_state, topology);
  734. if (ret) {
  735. SDE_ERROR_ENC(sde_enc,
  736. "RM failed to update topology, rc: %d\n", ret);
  737. return ret;
  738. }
  739. ret = sde_connector_set_blob_data(conn_state->connector,
  740. conn_state,
  741. CONNECTOR_PROP_SDE_INFO);
  742. if (ret) {
  743. SDE_ERROR_ENC(sde_enc,
  744. "connector failed to update info, rc: %d\n",
  745. ret);
  746. return ret;
  747. }
  748. }
  749. return ret;
  750. }
  751. static int sde_encoder_virt_atomic_check(
  752. struct drm_encoder *drm_enc, struct drm_crtc_state *crtc_state,
  753. struct drm_connector_state *conn_state)
  754. {
  755. struct sde_encoder_virt *sde_enc;
  756. struct sde_kms *sde_kms;
  757. const struct drm_display_mode *mode;
  758. struct drm_display_mode *adj_mode;
  759. struct sde_connector *sde_conn = NULL;
  760. struct sde_connector_state *sde_conn_state = NULL;
  761. struct sde_crtc_state *sde_crtc_state = NULL;
  762. enum sde_rm_topology_name old_top;
  763. int ret = 0;
  764. if (!drm_enc || !crtc_state || !conn_state) {
  765. SDE_ERROR("invalid arg(s), drm_enc %d, crtc/conn state %d/%d\n",
  766. !drm_enc, !crtc_state, !conn_state);
  767. return -EINVAL;
  768. }
  769. sde_enc = to_sde_encoder_virt(drm_enc);
  770. SDE_DEBUG_ENC(sde_enc, "\n");
  771. sde_kms = sde_encoder_get_kms(drm_enc);
  772. if (!sde_kms)
  773. return -EINVAL;
  774. mode = &crtc_state->mode;
  775. adj_mode = &crtc_state->adjusted_mode;
  776. sde_conn = to_sde_connector(conn_state->connector);
  777. sde_conn_state = to_sde_connector_state(conn_state);
  778. sde_crtc_state = to_sde_crtc_state(crtc_state);
  779. SDE_EVT32(DRMID(drm_enc), crtc_state->mode_changed,
  780. crtc_state->active_changed, crtc_state->connectors_changed);
  781. ret = _sde_encoder_atomic_check_phys_enc(sde_enc, crtc_state,
  782. conn_state);
  783. if (ret)
  784. return ret;
  785. ret = _sde_encoder_atomic_check_pu_roi(sde_enc, crtc_state,
  786. conn_state, sde_conn_state, sde_crtc_state);
  787. if (ret)
  788. return ret;
  789. /**
  790. * record topology in previous atomic state to be able to handle
  791. * topology transitions correctly.
  792. */
  793. old_top = sde_connector_get_property(conn_state,
  794. CONNECTOR_PROP_TOPOLOGY_NAME);
  795. ret = sde_connector_set_old_topology_name(conn_state, old_top);
  796. if (ret)
  797. return ret;
  798. ret = _sde_encoder_atomic_check_reserve(drm_enc, crtc_state,
  799. conn_state, sde_enc, sde_kms, sde_conn, sde_conn_state);
  800. if (ret)
  801. return ret;
  802. ret = sde_connector_roi_v1_check_roi(conn_state);
  803. if (ret) {
  804. SDE_ERROR_ENC(sde_enc, "connector roi check failed, rc: %d",
  805. ret);
  806. return ret;
  807. }
  808. drm_mode_set_crtcinfo(adj_mode, 0);
  809. SDE_EVT32(DRMID(drm_enc), adj_mode->flags, adj_mode->private_flags);
  810. return ret;
  811. }
  812. static void _sde_encoder_get_connector_roi(
  813. struct sde_encoder_virt *sde_enc,
  814. struct sde_rect *merged_conn_roi)
  815. {
  816. struct drm_connector *drm_conn;
  817. struct sde_connector_state *c_state;
  818. if (!sde_enc || !merged_conn_roi)
  819. return;
  820. drm_conn = sde_enc->phys_encs[0]->connector;
  821. if (!drm_conn || !drm_conn->state)
  822. return;
  823. c_state = to_sde_connector_state(drm_conn->state);
  824. sde_kms_rect_merge_rectangles(&c_state->rois, merged_conn_roi);
  825. }
  826. static int _sde_encoder_update_roi(struct drm_encoder *drm_enc)
  827. {
  828. struct sde_encoder_virt *sde_enc;
  829. struct drm_connector *drm_conn;
  830. struct drm_display_mode *adj_mode;
  831. struct sde_rect roi;
  832. if (!drm_enc) {
  833. SDE_ERROR("invalid encoder parameter\n");
  834. return -EINVAL;
  835. }
  836. sde_enc = to_sde_encoder_virt(drm_enc);
  837. if (!sde_enc->crtc || !sde_enc->crtc->state) {
  838. SDE_ERROR("invalid crtc parameter\n");
  839. return -EINVAL;
  840. }
  841. if (!sde_enc->cur_master) {
  842. SDE_ERROR("invalid cur_master parameter\n");
  843. return -EINVAL;
  844. }
  845. adj_mode = &sde_enc->cur_master->cached_mode;
  846. drm_conn = sde_enc->cur_master->connector;
  847. _sde_encoder_get_connector_roi(sde_enc, &roi);
  848. if (sde_kms_rect_is_null(&roi)) {
  849. roi.w = adj_mode->hdisplay;
  850. roi.h = adj_mode->vdisplay;
  851. }
  852. memcpy(&sde_enc->prv_conn_roi, &sde_enc->cur_conn_roi,
  853. sizeof(sde_enc->prv_conn_roi));
  854. memcpy(&sde_enc->cur_conn_roi, &roi, sizeof(sde_enc->cur_conn_roi));
  855. return 0;
  856. }
  857. void sde_encoder_helper_vsync_config(struct sde_encoder_phys *phys_enc,
  858. u32 vsync_source, bool is_dummy)
  859. {
  860. struct sde_vsync_source_cfg vsync_cfg = { 0 };
  861. struct sde_kms *sde_kms;
  862. struct sde_hw_mdp *hw_mdptop;
  863. struct sde_encoder_virt *sde_enc;
  864. int i;
  865. sde_enc = to_sde_encoder_virt(phys_enc->parent);
  866. if (!sde_enc) {
  867. SDE_ERROR("invalid param sde_enc:%d\n", sde_enc != NULL);
  868. return;
  869. } else if (sde_enc->num_phys_encs > ARRAY_SIZE(sde_enc->hw_pp)) {
  870. SDE_ERROR("invalid num phys enc %d/%d\n",
  871. sde_enc->num_phys_encs,
  872. (int) ARRAY_SIZE(sde_enc->hw_pp));
  873. return;
  874. }
  875. sde_kms = sde_encoder_get_kms(&sde_enc->base);
  876. if (!sde_kms) {
  877. SDE_ERROR("invalid sde_kms\n");
  878. return;
  879. }
  880. hw_mdptop = sde_kms->hw_mdp;
  881. if (!hw_mdptop) {
  882. SDE_ERROR("invalid mdptop\n");
  883. return;
  884. }
  885. if (hw_mdptop->ops.setup_vsync_source) {
  886. for (i = 0; i < sde_enc->num_phys_encs; i++)
  887. vsync_cfg.ppnumber[i] = sde_enc->hw_pp[i]->idx;
  888. vsync_cfg.pp_count = sde_enc->num_phys_encs;
  889. vsync_cfg.frame_rate = sde_enc->mode_info.frame_rate;
  890. vsync_cfg.vsync_source = vsync_source;
  891. vsync_cfg.is_dummy = is_dummy;
  892. hw_mdptop->ops.setup_vsync_source(hw_mdptop, &vsync_cfg);
  893. }
  894. }
  895. static void _sde_encoder_update_vsync_source(struct sde_encoder_virt *sde_enc,
  896. struct msm_display_info *disp_info, bool is_dummy)
  897. {
  898. struct sde_encoder_phys *phys;
  899. int i;
  900. u32 vsync_source;
  901. if (!sde_enc || !disp_info) {
  902. SDE_ERROR("invalid param sde_enc:%d or disp_info:%d\n",
  903. sde_enc != NULL, disp_info != NULL);
  904. return;
  905. } else if (sde_enc->num_phys_encs > ARRAY_SIZE(sde_enc->hw_pp)) {
  906. SDE_ERROR("invalid num phys enc %d/%d\n",
  907. sde_enc->num_phys_encs,
  908. (int) ARRAY_SIZE(sde_enc->hw_pp));
  909. return;
  910. }
  911. if (sde_encoder_check_curr_mode(&sde_enc->base, MSM_DISPLAY_CMD_MODE)) {
  912. if (is_dummy)
  913. vsync_source = SDE_VSYNC_SOURCE_WD_TIMER_0 -
  914. sde_enc->te_source;
  915. else if (disp_info->is_te_using_watchdog_timer)
  916. vsync_source = SDE_VSYNC_SOURCE_WD_TIMER_4;
  917. else
  918. vsync_source = sde_enc->te_source;
  919. SDE_EVT32(DRMID(&sde_enc->base), vsync_source, is_dummy,
  920. disp_info->is_te_using_watchdog_timer);
  921. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  922. phys = sde_enc->phys_encs[i];
  923. if (phys && phys->ops.setup_vsync_source)
  924. phys->ops.setup_vsync_source(phys,
  925. vsync_source, is_dummy);
  926. }
  927. }
  928. }
  929. int sde_encoder_helper_switch_vsync(struct drm_encoder *drm_enc,
  930. bool watchdog_te)
  931. {
  932. struct sde_encoder_virt *sde_enc;
  933. struct msm_display_info disp_info;
  934. if (!drm_enc) {
  935. pr_err("invalid drm encoder\n");
  936. return -EINVAL;
  937. }
  938. sde_enc = to_sde_encoder_virt(drm_enc);
  939. sde_encoder_control_te(drm_enc, false);
  940. memcpy(&disp_info, &sde_enc->disp_info, sizeof(disp_info));
  941. disp_info.is_te_using_watchdog_timer = watchdog_te;
  942. _sde_encoder_update_vsync_source(sde_enc, &disp_info, false);
  943. sde_encoder_control_te(drm_enc, true);
  944. return 0;
  945. }
  946. static int _sde_encoder_rsc_client_update_vsync_wait(
  947. struct drm_encoder *drm_enc, struct sde_encoder_virt *sde_enc,
  948. int wait_vblank_crtc_id)
  949. {
  950. int wait_refcount = 0, ret = 0;
  951. int pipe = -1;
  952. int wait_count = 0;
  953. struct drm_crtc *primary_crtc;
  954. struct drm_crtc *crtc;
  955. crtc = sde_enc->crtc;
  956. if (wait_vblank_crtc_id)
  957. wait_refcount =
  958. sde_rsc_client_get_vsync_refcount(sde_enc->rsc_client);
  959. SDE_EVT32_VERBOSE(DRMID(drm_enc), wait_vblank_crtc_id, wait_refcount,
  960. SDE_EVTLOG_FUNC_ENTRY);
  961. if (crtc->base.id != wait_vblank_crtc_id) {
  962. primary_crtc = drm_crtc_find(drm_enc->dev,
  963. NULL, wait_vblank_crtc_id);
  964. if (!primary_crtc) {
  965. SDE_ERROR_ENC(sde_enc,
  966. "failed to find primary crtc id %d\n",
  967. wait_vblank_crtc_id);
  968. return -EINVAL;
  969. }
  970. pipe = drm_crtc_index(primary_crtc);
  971. }
  972. /**
  973. * note: VBLANK is expected to be enabled at this point in
  974. * resource control state machine if on primary CRTC
  975. */
  976. for (wait_count = 0; wait_count < MAX_RSC_WAIT; wait_count++) {
  977. if (sde_rsc_client_is_state_update_complete(
  978. sde_enc->rsc_client))
  979. break;
  980. if (crtc->base.id == wait_vblank_crtc_id)
  981. ret = sde_encoder_wait_for_event(drm_enc,
  982. MSM_ENC_VBLANK);
  983. else
  984. drm_wait_one_vblank(drm_enc->dev, pipe);
  985. if (ret) {
  986. SDE_ERROR_ENC(sde_enc,
  987. "wait for vblank failed ret:%d\n", ret);
  988. /**
  989. * rsc hardware may hang without vsync. avoid rsc hang
  990. * by generating the vsync from watchdog timer.
  991. */
  992. if (crtc->base.id == wait_vblank_crtc_id)
  993. sde_encoder_helper_switch_vsync(drm_enc, true);
  994. }
  995. }
  996. if (wait_count >= MAX_RSC_WAIT)
  997. SDE_EVT32(DRMID(drm_enc), wait_vblank_crtc_id, wait_count,
  998. SDE_EVTLOG_ERROR);
  999. if (wait_refcount)
  1000. sde_rsc_client_reset_vsync_refcount(sde_enc->rsc_client);
  1001. SDE_EVT32_VERBOSE(DRMID(drm_enc), wait_vblank_crtc_id, wait_refcount,
  1002. SDE_EVTLOG_FUNC_EXIT);
  1003. return ret;
  1004. }
  1005. static int _sde_encoder_update_rsc_client(
  1006. struct drm_encoder *drm_enc, bool enable)
  1007. {
  1008. struct sde_encoder_virt *sde_enc;
  1009. struct drm_crtc *crtc;
  1010. enum sde_rsc_state rsc_state = SDE_RSC_IDLE_STATE;
  1011. struct sde_rsc_cmd_config *rsc_config;
  1012. int ret;
  1013. struct msm_display_info *disp_info;
  1014. struct msm_mode_info *mode_info;
  1015. int wait_vblank_crtc_id = SDE_RSC_INVALID_CRTC_ID;
  1016. u32 qsync_mode = 0, v_front_porch;
  1017. struct drm_display_mode *mode;
  1018. bool is_vid_mode;
  1019. struct drm_encoder *enc;
  1020. if (!drm_enc || !drm_enc->dev) {
  1021. SDE_ERROR("invalid encoder arguments\n");
  1022. return -EINVAL;
  1023. }
  1024. sde_enc = to_sde_encoder_virt(drm_enc);
  1025. mode_info = &sde_enc->mode_info;
  1026. crtc = sde_enc->crtc;
  1027. if (!sde_enc->crtc) {
  1028. SDE_ERROR("invalid crtc parameter\n");
  1029. return -EINVAL;
  1030. }
  1031. disp_info = &sde_enc->disp_info;
  1032. rsc_config = &sde_enc->rsc_config;
  1033. if (!sde_enc->rsc_client) {
  1034. SDE_DEBUG_ENC(sde_enc, "rsc client not created\n");
  1035. return 0;
  1036. }
  1037. /**
  1038. * only primary command mode panel without Qsync can request CMD state.
  1039. * all other panels/displays can request for VID state including
  1040. * secondary command mode panel.
  1041. * Clone mode encoder can request CLK STATE only.
  1042. */
  1043. if (sde_enc->cur_master)
  1044. qsync_mode = sde_connector_get_qsync_mode(
  1045. sde_enc->cur_master->connector);
  1046. if (sde_encoder_in_clone_mode(drm_enc) ||
  1047. (disp_info->display_type != SDE_CONNECTOR_PRIMARY) ||
  1048. (disp_info->display_type && qsync_mode))
  1049. rsc_state = enable ? SDE_RSC_CLK_STATE : SDE_RSC_IDLE_STATE;
  1050. else if (sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE))
  1051. rsc_state = enable ? SDE_RSC_CMD_STATE : SDE_RSC_IDLE_STATE;
  1052. else if (sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_VIDEO_MODE))
  1053. rsc_state = enable ? SDE_RSC_VID_STATE : SDE_RSC_IDLE_STATE;
  1054. drm_for_each_encoder(enc, drm_enc->dev) {
  1055. if (enc->base.id != drm_enc->base.id &&
  1056. sde_encoder_in_cont_splash(enc))
  1057. rsc_state = SDE_RSC_CLK_STATE;
  1058. }
  1059. SDE_EVT32(rsc_state, qsync_mode);
  1060. is_vid_mode = sde_encoder_check_curr_mode(&sde_enc->base,
  1061. MSM_DISPLAY_VIDEO_MODE);
  1062. mode = &sde_enc->crtc->state->mode;
  1063. v_front_porch = mode->vsync_start - mode->vdisplay;
  1064. /* compare specific items and reconfigure the rsc */
  1065. if ((rsc_config->fps != mode_info->frame_rate) ||
  1066. (rsc_config->vtotal != mode_info->vtotal) ||
  1067. (rsc_config->prefill_lines != mode_info->prefill_lines) ||
  1068. (rsc_config->jitter_numer != mode_info->jitter_numer) ||
  1069. (rsc_config->jitter_denom != mode_info->jitter_denom)) {
  1070. rsc_config->fps = mode_info->frame_rate;
  1071. rsc_config->vtotal = mode_info->vtotal;
  1072. /*
  1073. * for video mode, prefill lines should not go beyond vertical
  1074. * front porch for RSCC configuration. This will ensure bw
  1075. * downvotes are not sent within the active region. Additional
  1076. * -1 is to give one line time for rscc mode min_threshold.
  1077. */
  1078. if (is_vid_mode && (mode_info->prefill_lines >= v_front_porch))
  1079. rsc_config->prefill_lines = v_front_porch - 1;
  1080. else
  1081. rsc_config->prefill_lines = mode_info->prefill_lines;
  1082. rsc_config->jitter_numer = mode_info->jitter_numer;
  1083. rsc_config->jitter_denom = mode_info->jitter_denom;
  1084. sde_enc->rsc_state_init = false;
  1085. }
  1086. if (rsc_state != SDE_RSC_IDLE_STATE && !sde_enc->rsc_state_init
  1087. && (disp_info->display_type == SDE_CONNECTOR_PRIMARY)) {
  1088. /* update it only once */
  1089. sde_enc->rsc_state_init = true;
  1090. ret = sde_rsc_client_state_update(sde_enc->rsc_client,
  1091. rsc_state, rsc_config, crtc->base.id,
  1092. &wait_vblank_crtc_id);
  1093. } else {
  1094. ret = sde_rsc_client_state_update(sde_enc->rsc_client,
  1095. rsc_state, NULL, crtc->base.id,
  1096. &wait_vblank_crtc_id);
  1097. }
  1098. /**
  1099. * if RSC performed a state change that requires a VBLANK wait, it will
  1100. * set wait_vblank_crtc_id to the CRTC whose VBLANK we must wait on.
  1101. *
  1102. * if we are the primary display, we will need to enable and wait
  1103. * locally since we hold the commit thread
  1104. *
  1105. * if we are an external display, we must send a signal to the primary
  1106. * to enable its VBLANK and wait one, since the RSC hardware is driven
  1107. * by the primary panel's VBLANK signals
  1108. */
  1109. SDE_EVT32_VERBOSE(DRMID(drm_enc), wait_vblank_crtc_id);
  1110. if (ret) {
  1111. SDE_ERROR_ENC(sde_enc,
  1112. "sde rsc client update failed ret:%d\n", ret);
  1113. return ret;
  1114. } else if (wait_vblank_crtc_id == SDE_RSC_INVALID_CRTC_ID) {
  1115. return ret;
  1116. }
  1117. ret = _sde_encoder_rsc_client_update_vsync_wait(drm_enc,
  1118. sde_enc, wait_vblank_crtc_id);
  1119. return ret;
  1120. }
  1121. static void _sde_encoder_irq_control(struct drm_encoder *drm_enc, bool enable)
  1122. {
  1123. struct sde_encoder_virt *sde_enc;
  1124. int i;
  1125. if (!drm_enc) {
  1126. SDE_ERROR("invalid encoder\n");
  1127. return;
  1128. }
  1129. sde_enc = to_sde_encoder_virt(drm_enc);
  1130. SDE_DEBUG_ENC(sde_enc, "enable:%d\n", enable);
  1131. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1132. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  1133. if (phys && phys->ops.irq_control)
  1134. phys->ops.irq_control(phys, enable);
  1135. }
  1136. }
  1137. /* keep track of the userspace vblank during modeset */
  1138. static void _sde_encoder_modeset_helper_locked(struct drm_encoder *drm_enc,
  1139. u32 sw_event)
  1140. {
  1141. struct sde_encoder_virt *sde_enc;
  1142. bool enable;
  1143. int i;
  1144. if (!drm_enc) {
  1145. SDE_ERROR("invalid encoder\n");
  1146. return;
  1147. }
  1148. sde_enc = to_sde_encoder_virt(drm_enc);
  1149. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, vblank_enabled:%d\n",
  1150. sw_event, sde_enc->vblank_enabled);
  1151. /* nothing to do if vblank not enabled by userspace */
  1152. if (!sde_enc->vblank_enabled)
  1153. return;
  1154. /* disable vblank on pre_modeset */
  1155. if (sw_event == SDE_ENC_RC_EVENT_PRE_MODESET)
  1156. enable = false;
  1157. /* enable vblank on post_modeset */
  1158. else if (sw_event == SDE_ENC_RC_EVENT_POST_MODESET)
  1159. enable = true;
  1160. else
  1161. return;
  1162. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1163. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  1164. if (phys && phys->ops.control_vblank_irq)
  1165. phys->ops.control_vblank_irq(phys, enable);
  1166. }
  1167. }
  1168. struct sde_rsc_client *sde_encoder_get_rsc_client(struct drm_encoder *drm_enc)
  1169. {
  1170. struct sde_encoder_virt *sde_enc;
  1171. if (!drm_enc)
  1172. return NULL;
  1173. sde_enc = to_sde_encoder_virt(drm_enc);
  1174. return sde_enc->rsc_client;
  1175. }
  1176. static int _sde_encoder_resource_control_helper(struct drm_encoder *drm_enc,
  1177. bool enable)
  1178. {
  1179. struct sde_kms *sde_kms;
  1180. struct sde_encoder_virt *sde_enc;
  1181. int rc;
  1182. sde_enc = to_sde_encoder_virt(drm_enc);
  1183. sde_kms = sde_encoder_get_kms(drm_enc);
  1184. if (!sde_kms)
  1185. return -EINVAL;
  1186. SDE_DEBUG_ENC(sde_enc, "enable:%d\n", enable);
  1187. SDE_EVT32(DRMID(drm_enc), enable);
  1188. if (!sde_enc->cur_master) {
  1189. SDE_ERROR("encoder master not set\n");
  1190. return -EINVAL;
  1191. }
  1192. if (enable) {
  1193. /* enable SDE core clks */
  1194. rc = pm_runtime_get_sync(drm_enc->dev->dev);
  1195. if (rc < 0) {
  1196. SDE_ERROR("failed to enable power resource %d\n", rc);
  1197. SDE_EVT32(rc, SDE_EVTLOG_ERROR);
  1198. return rc;
  1199. }
  1200. sde_enc->elevated_ahb_vote = true;
  1201. /* enable DSI clks */
  1202. rc = sde_connector_clk_ctrl(sde_enc->cur_master->connector,
  1203. true);
  1204. if (rc) {
  1205. SDE_ERROR("failed to enable clk control %d\n", rc);
  1206. pm_runtime_put_sync(drm_enc->dev->dev);
  1207. return rc;
  1208. }
  1209. /* enable all the irq */
  1210. _sde_encoder_irq_control(drm_enc, true);
  1211. _sde_encoder_pm_qos_add_request(drm_enc);
  1212. } else {
  1213. _sde_encoder_pm_qos_remove_request(drm_enc);
  1214. /* disable all the irq */
  1215. _sde_encoder_irq_control(drm_enc, false);
  1216. /* disable DSI clks */
  1217. sde_connector_clk_ctrl(sde_enc->cur_master->connector, false);
  1218. /* disable SDE core clks */
  1219. pm_runtime_put_sync(drm_enc->dev->dev);
  1220. }
  1221. return 0;
  1222. }
  1223. static void sde_encoder_misr_configure(struct drm_encoder *drm_enc,
  1224. bool enable, u32 frame_count)
  1225. {
  1226. struct sde_encoder_virt *sde_enc;
  1227. int i;
  1228. if (!drm_enc) {
  1229. SDE_ERROR("invalid encoder\n");
  1230. return;
  1231. }
  1232. sde_enc = to_sde_encoder_virt(drm_enc);
  1233. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1234. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  1235. if (!phys || !phys->ops.setup_misr)
  1236. continue;
  1237. phys->ops.setup_misr(phys, enable, frame_count);
  1238. }
  1239. }
  1240. static void sde_encoder_input_event_handler(struct input_handle *handle,
  1241. unsigned int type, unsigned int code, int value)
  1242. {
  1243. struct drm_encoder *drm_enc = NULL;
  1244. struct sde_encoder_virt *sde_enc = NULL;
  1245. struct msm_drm_thread *disp_thread = NULL;
  1246. struct msm_drm_private *priv = NULL;
  1247. if (!handle || !handle->handler || !handle->handler->private) {
  1248. SDE_ERROR("invalid encoder for the input event\n");
  1249. return;
  1250. }
  1251. drm_enc = (struct drm_encoder *)handle->handler->private;
  1252. if (!drm_enc->dev || !drm_enc->dev->dev_private) {
  1253. SDE_ERROR("invalid parameters\n");
  1254. return;
  1255. }
  1256. priv = drm_enc->dev->dev_private;
  1257. sde_enc = to_sde_encoder_virt(drm_enc);
  1258. if (!sde_enc->crtc || (sde_enc->crtc->index
  1259. >= ARRAY_SIZE(priv->disp_thread))) {
  1260. SDE_DEBUG_ENC(sde_enc,
  1261. "invalid cached CRTC: %d or crtc index: %d\n",
  1262. sde_enc->crtc == NULL,
  1263. sde_enc->crtc ? sde_enc->crtc->index : -EINVAL);
  1264. return;
  1265. }
  1266. SDE_EVT32_VERBOSE(DRMID(drm_enc));
  1267. disp_thread = &priv->disp_thread[sde_enc->crtc->index];
  1268. kthread_queue_work(&disp_thread->worker,
  1269. &sde_enc->input_event_work);
  1270. }
  1271. void sde_encoder_control_idle_pc(struct drm_encoder *drm_enc, bool enable)
  1272. {
  1273. struct sde_encoder_virt *sde_enc;
  1274. if (!drm_enc) {
  1275. SDE_ERROR("invalid encoder\n");
  1276. return;
  1277. }
  1278. sde_enc = to_sde_encoder_virt(drm_enc);
  1279. /* return early if there is no state change */
  1280. if (sde_enc->idle_pc_enabled == enable)
  1281. return;
  1282. sde_enc->idle_pc_enabled = enable;
  1283. SDE_DEBUG("idle-pc state:%d\n", sde_enc->idle_pc_enabled);
  1284. SDE_EVT32(sde_enc->idle_pc_enabled);
  1285. }
  1286. static void _sde_encoder_rc_restart_delayed(struct sde_encoder_virt *sde_enc,
  1287. u32 sw_event)
  1288. {
  1289. struct drm_encoder *drm_enc = &sde_enc->base;
  1290. struct msm_drm_private *priv;
  1291. unsigned int lp, idle_pc_duration;
  1292. struct msm_drm_thread *disp_thread;
  1293. /* set idle timeout based on master connector's lp value */
  1294. if (sde_enc->cur_master)
  1295. lp = sde_connector_get_lp(
  1296. sde_enc->cur_master->connector);
  1297. else
  1298. lp = SDE_MODE_DPMS_ON;
  1299. if (lp == SDE_MODE_DPMS_LP2)
  1300. idle_pc_duration = IDLE_SHORT_TIMEOUT;
  1301. else
  1302. idle_pc_duration = IDLE_POWERCOLLAPSE_DURATION;
  1303. priv = drm_enc->dev->dev_private;
  1304. disp_thread = &priv->disp_thread[sde_enc->crtc->index];
  1305. kthread_mod_delayed_work(
  1306. &disp_thread->worker,
  1307. &sde_enc->delayed_off_work,
  1308. msecs_to_jiffies(idle_pc_duration));
  1309. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1310. idle_pc_duration, SDE_EVTLOG_FUNC_CASE2);
  1311. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, work scheduled\n",
  1312. sw_event);
  1313. }
  1314. static void _sde_encoder_rc_cancel_delayed(struct sde_encoder_virt *sde_enc,
  1315. u32 sw_event)
  1316. {
  1317. if (kthread_cancel_delayed_work_sync(
  1318. &sde_enc->delayed_off_work))
  1319. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, work cancelled\n",
  1320. sw_event);
  1321. }
  1322. static void _sde_encoder_rc_kickoff_delayed(struct sde_encoder_virt *sde_enc,
  1323. u32 sw_event)
  1324. {
  1325. if (_sde_encoder_is_autorefresh_enabled(sde_enc))
  1326. _sde_encoder_rc_cancel_delayed(sde_enc, sw_event);
  1327. else
  1328. _sde_encoder_rc_restart_delayed(sde_enc, sw_event);
  1329. }
  1330. static int _sde_encoder_rc_kickoff(struct drm_encoder *drm_enc,
  1331. u32 sw_event, struct sde_encoder_virt *sde_enc, bool is_vid_mode)
  1332. {
  1333. int ret = 0;
  1334. mutex_lock(&sde_enc->rc_lock);
  1335. /* return if the resource control is already in ON state */
  1336. if (sde_enc->rc_state == SDE_ENC_RC_STATE_ON) {
  1337. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc in ON state\n",
  1338. sw_event);
  1339. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1340. SDE_EVTLOG_FUNC_CASE1);
  1341. goto end;
  1342. } else if (sde_enc->rc_state != SDE_ENC_RC_STATE_OFF &&
  1343. sde_enc->rc_state != SDE_ENC_RC_STATE_IDLE) {
  1344. SDE_ERROR_ENC(sde_enc, "sw_event:%d, rc in state %d\n",
  1345. sw_event, sde_enc->rc_state);
  1346. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1347. SDE_EVTLOG_ERROR);
  1348. goto end;
  1349. }
  1350. if (is_vid_mode && sde_enc->rc_state == SDE_ENC_RC_STATE_IDLE) {
  1351. _sde_encoder_irq_control(drm_enc, true);
  1352. } else {
  1353. /* enable all the clks and resources */
  1354. ret = _sde_encoder_resource_control_helper(drm_enc,
  1355. true);
  1356. if (ret) {
  1357. SDE_ERROR_ENC(sde_enc,
  1358. "sw_event:%d, rc in state %d\n",
  1359. sw_event, sde_enc->rc_state);
  1360. SDE_EVT32(DRMID(drm_enc), sw_event,
  1361. sde_enc->rc_state,
  1362. SDE_EVTLOG_ERROR);
  1363. goto end;
  1364. }
  1365. _sde_encoder_update_rsc_client(drm_enc, true);
  1366. }
  1367. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1368. SDE_ENC_RC_STATE_ON, SDE_EVTLOG_FUNC_CASE1);
  1369. sde_enc->rc_state = SDE_ENC_RC_STATE_ON;
  1370. end:
  1371. _sde_encoder_rc_kickoff_delayed(sde_enc, sw_event);
  1372. mutex_unlock(&sde_enc->rc_lock);
  1373. return ret;
  1374. }
  1375. static int _sde_encoder_rc_pre_stop(struct drm_encoder *drm_enc,
  1376. u32 sw_event, struct sde_encoder_virt *sde_enc, bool is_vid_mode)
  1377. {
  1378. /* cancel delayed off work, if any */
  1379. _sde_encoder_rc_cancel_delayed(sde_enc, sw_event);
  1380. mutex_lock(&sde_enc->rc_lock);
  1381. if (is_vid_mode &&
  1382. sde_enc->rc_state == SDE_ENC_RC_STATE_IDLE) {
  1383. _sde_encoder_irq_control(drm_enc, true);
  1384. }
  1385. /* skip if is already OFF or IDLE, resources are off already */
  1386. else if (sde_enc->rc_state == SDE_ENC_RC_STATE_OFF ||
  1387. sde_enc->rc_state == SDE_ENC_RC_STATE_IDLE) {
  1388. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc in %d state\n",
  1389. sw_event, sde_enc->rc_state);
  1390. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1391. SDE_EVTLOG_FUNC_CASE3);
  1392. goto end;
  1393. }
  1394. /**
  1395. * IRQs are still enabled currently, which allows wait for
  1396. * VBLANK which RSC may require to correctly transition to OFF
  1397. */
  1398. _sde_encoder_update_rsc_client(drm_enc, false);
  1399. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1400. SDE_ENC_RC_STATE_PRE_OFF,
  1401. SDE_EVTLOG_FUNC_CASE3);
  1402. sde_enc->rc_state = SDE_ENC_RC_STATE_PRE_OFF;
  1403. end:
  1404. mutex_unlock(&sde_enc->rc_lock);
  1405. return 0;
  1406. }
  1407. static int _sde_encoder_rc_stop(struct drm_encoder *drm_enc,
  1408. u32 sw_event, struct sde_encoder_virt *sde_enc)
  1409. {
  1410. int ret = 0;
  1411. /* cancel vsync event work and timer */
  1412. kthread_cancel_work_sync(&sde_enc->vsync_event_work);
  1413. if (sde_enc->disp_info.intf_type == DRM_MODE_CONNECTOR_DSI)
  1414. del_timer_sync(&sde_enc->vsync_event_timer);
  1415. mutex_lock(&sde_enc->rc_lock);
  1416. /* return if the resource control is already in OFF state */
  1417. if (sde_enc->rc_state == SDE_ENC_RC_STATE_OFF) {
  1418. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc in OFF state\n",
  1419. sw_event);
  1420. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1421. SDE_EVTLOG_FUNC_CASE4);
  1422. goto end;
  1423. } else if (sde_enc->rc_state == SDE_ENC_RC_STATE_ON ||
  1424. sde_enc->rc_state == SDE_ENC_RC_STATE_MODESET) {
  1425. SDE_ERROR_ENC(sde_enc, "sw_event:%d, rc in state %d\n",
  1426. sw_event, sde_enc->rc_state);
  1427. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1428. SDE_EVTLOG_ERROR);
  1429. ret = -EINVAL;
  1430. goto end;
  1431. }
  1432. /**
  1433. * expect to arrive here only if in either idle state or pre-off
  1434. * and in IDLE state the resources are already disabled
  1435. */
  1436. if (sde_enc->rc_state == SDE_ENC_RC_STATE_PRE_OFF)
  1437. _sde_encoder_resource_control_helper(drm_enc, false);
  1438. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1439. SDE_ENC_RC_STATE_OFF, SDE_EVTLOG_FUNC_CASE4);
  1440. sde_enc->rc_state = SDE_ENC_RC_STATE_OFF;
  1441. end:
  1442. mutex_unlock(&sde_enc->rc_lock);
  1443. return ret;
  1444. }
  1445. static int _sde_encoder_rc_pre_modeset(struct drm_encoder *drm_enc,
  1446. u32 sw_event, struct sde_encoder_virt *sde_enc)
  1447. {
  1448. int ret = 0;
  1449. /* cancel delayed off work, if any */
  1450. _sde_encoder_rc_cancel_delayed(sde_enc, sw_event);
  1451. mutex_lock(&sde_enc->rc_lock);
  1452. if (sde_enc->rc_state == SDE_ENC_RC_STATE_OFF) {
  1453. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc in OFF state\n",
  1454. sw_event);
  1455. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1456. SDE_EVTLOG_FUNC_CASE5);
  1457. goto end;
  1458. } else if (sde_enc->rc_state != SDE_ENC_RC_STATE_ON) {
  1459. /* enable all the clks and resources */
  1460. ret = _sde_encoder_resource_control_helper(drm_enc,
  1461. true);
  1462. if (ret) {
  1463. SDE_ERROR_ENC(sde_enc,
  1464. "sw_event:%d, rc in state %d\n",
  1465. sw_event, sde_enc->rc_state);
  1466. SDE_EVT32(DRMID(drm_enc), sw_event,
  1467. sde_enc->rc_state,
  1468. SDE_EVTLOG_ERROR);
  1469. goto end;
  1470. }
  1471. _sde_encoder_update_rsc_client(drm_enc, true);
  1472. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1473. SDE_ENC_RC_STATE_ON, SDE_EVTLOG_FUNC_CASE5);
  1474. sde_enc->rc_state = SDE_ENC_RC_STATE_ON;
  1475. }
  1476. ret = sde_encoder_wait_for_event(drm_enc, MSM_ENC_TX_COMPLETE);
  1477. if (ret && ret != -EWOULDBLOCK) {
  1478. SDE_ERROR_ENC(sde_enc,
  1479. "wait for commit done returned %d\n",
  1480. ret);
  1481. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1482. ret, SDE_EVTLOG_ERROR);
  1483. ret = -EINVAL;
  1484. goto end;
  1485. }
  1486. _sde_encoder_irq_control(drm_enc, false);
  1487. _sde_encoder_modeset_helper_locked(drm_enc, sw_event);
  1488. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1489. SDE_ENC_RC_STATE_MODESET, SDE_EVTLOG_FUNC_CASE5);
  1490. sde_enc->rc_state = SDE_ENC_RC_STATE_MODESET;
  1491. _sde_encoder_pm_qos_remove_request(drm_enc);
  1492. end:
  1493. mutex_unlock(&sde_enc->rc_lock);
  1494. return ret;
  1495. }
  1496. static int _sde_encoder_rc_post_modeset(struct drm_encoder *drm_enc,
  1497. u32 sw_event, struct sde_encoder_virt *sde_enc)
  1498. {
  1499. int ret = 0;
  1500. mutex_lock(&sde_enc->rc_lock);
  1501. if (sde_enc->rc_state == SDE_ENC_RC_STATE_OFF) {
  1502. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc in OFF state\n",
  1503. sw_event);
  1504. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1505. SDE_EVTLOG_FUNC_CASE5);
  1506. goto end;
  1507. } else if (sde_enc->rc_state != SDE_ENC_RC_STATE_MODESET) {
  1508. SDE_ERROR_ENC(sde_enc,
  1509. "sw_event:%d, rc:%d !MODESET state\n",
  1510. sw_event, sde_enc->rc_state);
  1511. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1512. SDE_EVTLOG_ERROR);
  1513. ret = -EINVAL;
  1514. goto end;
  1515. }
  1516. _sde_encoder_modeset_helper_locked(drm_enc, sw_event);
  1517. _sde_encoder_irq_control(drm_enc, true);
  1518. _sde_encoder_update_rsc_client(drm_enc, true);
  1519. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1520. SDE_ENC_RC_STATE_ON, SDE_EVTLOG_FUNC_CASE6);
  1521. sde_enc->rc_state = SDE_ENC_RC_STATE_ON;
  1522. _sde_encoder_pm_qos_add_request(drm_enc);
  1523. end:
  1524. mutex_unlock(&sde_enc->rc_lock);
  1525. return ret;
  1526. }
  1527. static int _sde_encoder_rc_idle(struct drm_encoder *drm_enc,
  1528. u32 sw_event, struct sde_encoder_virt *sde_enc, bool is_vid_mode)
  1529. {
  1530. struct msm_drm_private *priv;
  1531. struct sde_kms *sde_kms;
  1532. struct drm_crtc *crtc = drm_enc->crtc;
  1533. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  1534. priv = drm_enc->dev->dev_private;
  1535. sde_kms = to_sde_kms(priv->kms);
  1536. mutex_lock(&sde_enc->rc_lock);
  1537. if (sde_enc->rc_state != SDE_ENC_RC_STATE_ON) {
  1538. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, rc:%d !ON state\n",
  1539. sw_event, sde_enc->rc_state);
  1540. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1541. SDE_EVTLOG_ERROR);
  1542. goto end;
  1543. } else if (sde_crtc_frame_pending(sde_enc->crtc)) {
  1544. SDE_DEBUG_ENC(sde_enc, "skip idle entry");
  1545. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1546. sde_crtc_frame_pending(sde_enc->crtc),
  1547. SDE_EVTLOG_ERROR);
  1548. _sde_encoder_rc_kickoff_delayed(sde_enc, sw_event);
  1549. goto end;
  1550. }
  1551. if (is_vid_mode) {
  1552. _sde_encoder_irq_control(drm_enc, false);
  1553. } else {
  1554. /* disable all the clks and resources */
  1555. _sde_encoder_update_rsc_client(drm_enc, false);
  1556. _sde_encoder_resource_control_helper(drm_enc, false);
  1557. if (!sde_kms->perf.bw_vote_mode)
  1558. memset(&sde_crtc->cur_perf, 0,
  1559. sizeof(struct sde_core_perf_params));
  1560. }
  1561. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1562. SDE_ENC_RC_STATE_IDLE, SDE_EVTLOG_FUNC_CASE7);
  1563. sde_enc->rc_state = SDE_ENC_RC_STATE_IDLE;
  1564. end:
  1565. mutex_unlock(&sde_enc->rc_lock);
  1566. return 0;
  1567. }
  1568. static int _sde_encoder_rc_early_wakeup(struct drm_encoder *drm_enc,
  1569. u32 sw_event, struct sde_encoder_virt *sde_enc,
  1570. struct msm_drm_private *priv, bool is_vid_mode)
  1571. {
  1572. bool autorefresh_enabled = false;
  1573. struct msm_drm_thread *disp_thread;
  1574. int ret = 0;
  1575. if (!sde_enc->crtc ||
  1576. sde_enc->crtc->index >= ARRAY_SIZE(priv->disp_thread)) {
  1577. SDE_DEBUG_ENC(sde_enc,
  1578. "invalid crtc:%d or crtc index:%d , sw_event:%u\n",
  1579. sde_enc->crtc == NULL,
  1580. sde_enc->crtc ? sde_enc->crtc->index : -EINVAL,
  1581. sw_event);
  1582. return -EINVAL;
  1583. }
  1584. disp_thread = &priv->disp_thread[sde_enc->crtc->index];
  1585. mutex_lock(&sde_enc->rc_lock);
  1586. if (sde_enc->rc_state == SDE_ENC_RC_STATE_ON) {
  1587. if (sde_enc->cur_master &&
  1588. sde_enc->cur_master->ops.is_autorefresh_enabled)
  1589. autorefresh_enabled =
  1590. sde_enc->cur_master->ops.is_autorefresh_enabled(
  1591. sde_enc->cur_master);
  1592. if (autorefresh_enabled) {
  1593. SDE_DEBUG_ENC(sde_enc,
  1594. "not handling early wakeup since auto refresh is enabled\n");
  1595. goto end;
  1596. }
  1597. if (!sde_crtc_frame_pending(sde_enc->crtc))
  1598. kthread_mod_delayed_work(&disp_thread->worker,
  1599. &sde_enc->delayed_off_work,
  1600. msecs_to_jiffies(
  1601. IDLE_POWERCOLLAPSE_DURATION));
  1602. } else if (sde_enc->rc_state == SDE_ENC_RC_STATE_IDLE) {
  1603. /* enable all the clks and resources */
  1604. ret = _sde_encoder_resource_control_helper(drm_enc,
  1605. true);
  1606. if (ret) {
  1607. SDE_ERROR_ENC(sde_enc,
  1608. "sw_event:%d, rc in state %d\n",
  1609. sw_event, sde_enc->rc_state);
  1610. SDE_EVT32(DRMID(drm_enc), sw_event,
  1611. sde_enc->rc_state,
  1612. SDE_EVTLOG_ERROR);
  1613. goto end;
  1614. }
  1615. _sde_encoder_update_rsc_client(drm_enc, true);
  1616. /*
  1617. * In some cases, commit comes with slight delay
  1618. * (> 80 ms)after early wake up, prevent clock switch
  1619. * off to avoid jank in next update. So, increase the
  1620. * command mode idle timeout sufficiently to prevent
  1621. * such case.
  1622. */
  1623. kthread_mod_delayed_work(&disp_thread->worker,
  1624. &sde_enc->delayed_off_work,
  1625. msecs_to_jiffies(
  1626. IDLE_POWERCOLLAPSE_IN_EARLY_WAKEUP));
  1627. sde_enc->rc_state = SDE_ENC_RC_STATE_ON;
  1628. }
  1629. SDE_EVT32(DRMID(drm_enc), sw_event, sde_enc->rc_state,
  1630. SDE_ENC_RC_STATE_ON, SDE_EVTLOG_FUNC_CASE8);
  1631. end:
  1632. mutex_unlock(&sde_enc->rc_lock);
  1633. return ret;
  1634. }
  1635. static int sde_encoder_resource_control(struct drm_encoder *drm_enc,
  1636. u32 sw_event)
  1637. {
  1638. struct sde_encoder_virt *sde_enc;
  1639. struct msm_drm_private *priv;
  1640. int ret = 0;
  1641. bool is_vid_mode = false;
  1642. if (!drm_enc || !drm_enc->dev || !drm_enc->dev->dev_private) {
  1643. SDE_ERROR("invalid encoder parameters, sw_event:%u\n",
  1644. sw_event);
  1645. return -EINVAL;
  1646. }
  1647. sde_enc = to_sde_encoder_virt(drm_enc);
  1648. priv = drm_enc->dev->dev_private;
  1649. if (sde_encoder_check_curr_mode(&sde_enc->base, MSM_DISPLAY_VIDEO_MODE))
  1650. is_vid_mode = true;
  1651. /*
  1652. * when idle_pc is not supported, process only KICKOFF, STOP and MODESET
  1653. * events and return early for other events (ie wb display).
  1654. */
  1655. if (!sde_enc->idle_pc_enabled &&
  1656. (sw_event != SDE_ENC_RC_EVENT_KICKOFF &&
  1657. sw_event != SDE_ENC_RC_EVENT_PRE_MODESET &&
  1658. sw_event != SDE_ENC_RC_EVENT_POST_MODESET &&
  1659. sw_event != SDE_ENC_RC_EVENT_STOP &&
  1660. sw_event != SDE_ENC_RC_EVENT_PRE_STOP))
  1661. return 0;
  1662. SDE_DEBUG_ENC(sde_enc, "sw_event:%d, idle_pc:%d\n",
  1663. sw_event, sde_enc->idle_pc_enabled);
  1664. SDE_EVT32_VERBOSE(DRMID(drm_enc), sw_event, sde_enc->idle_pc_enabled,
  1665. sde_enc->rc_state, SDE_EVTLOG_FUNC_ENTRY);
  1666. switch (sw_event) {
  1667. case SDE_ENC_RC_EVENT_KICKOFF:
  1668. ret = _sde_encoder_rc_kickoff(drm_enc, sw_event, sde_enc,
  1669. is_vid_mode);
  1670. break;
  1671. case SDE_ENC_RC_EVENT_PRE_STOP:
  1672. ret = _sde_encoder_rc_pre_stop(drm_enc, sw_event, sde_enc,
  1673. is_vid_mode);
  1674. break;
  1675. case SDE_ENC_RC_EVENT_STOP:
  1676. ret = _sde_encoder_rc_stop(drm_enc, sw_event, sde_enc);
  1677. break;
  1678. case SDE_ENC_RC_EVENT_PRE_MODESET:
  1679. ret = _sde_encoder_rc_pre_modeset(drm_enc, sw_event, sde_enc);
  1680. break;
  1681. case SDE_ENC_RC_EVENT_POST_MODESET:
  1682. ret = _sde_encoder_rc_post_modeset(drm_enc, sw_event, sde_enc);
  1683. break;
  1684. case SDE_ENC_RC_EVENT_ENTER_IDLE:
  1685. ret = _sde_encoder_rc_idle(drm_enc, sw_event, sde_enc,
  1686. is_vid_mode);
  1687. break;
  1688. case SDE_ENC_RC_EVENT_EARLY_WAKEUP:
  1689. ret = _sde_encoder_rc_early_wakeup(drm_enc, sw_event, sde_enc,
  1690. priv, is_vid_mode);
  1691. break;
  1692. default:
  1693. SDE_EVT32(DRMID(drm_enc), sw_event, SDE_EVTLOG_ERROR);
  1694. SDE_ERROR("unexpected sw_event: %d\n", sw_event);
  1695. break;
  1696. }
  1697. SDE_EVT32_VERBOSE(DRMID(drm_enc), sw_event, sde_enc->idle_pc_enabled,
  1698. sde_enc->rc_state, SDE_EVTLOG_FUNC_EXIT);
  1699. return ret;
  1700. }
  1701. static void sde_encoder_virt_mode_switch(struct drm_encoder *drm_enc,
  1702. enum sde_intf_mode intf_mode, struct drm_display_mode *adj_mode)
  1703. {
  1704. int i = 0;
  1705. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  1706. if (intf_mode == INTF_MODE_CMD)
  1707. sde_enc->disp_info.curr_panel_mode = MSM_DISPLAY_VIDEO_MODE;
  1708. else if (intf_mode == INTF_MODE_VIDEO)
  1709. sde_enc->disp_info.curr_panel_mode = MSM_DISPLAY_CMD_MODE;
  1710. _sde_encoder_update_rsc_client(drm_enc, true);
  1711. if (intf_mode == INTF_MODE_CMD) {
  1712. for (i = 0; i < sde_enc->num_phys_encs; i++)
  1713. sde_enc->phys_encs[i] = sde_enc->phys_vid_encs[i];
  1714. SDE_DEBUG_ENC(sde_enc, "switch to video physical encoder\n");
  1715. SDE_EVT32(DRMID(&sde_enc->base), intf_mode,
  1716. msm_is_mode_seamless_poms(adj_mode),
  1717. SDE_EVTLOG_FUNC_CASE1);
  1718. } else if (intf_mode == INTF_MODE_VIDEO) {
  1719. for (i = 0; i < sde_enc->num_phys_encs; i++)
  1720. sde_enc->phys_encs[i] = sde_enc->phys_cmd_encs[i];
  1721. SDE_EVT32(DRMID(&sde_enc->base), intf_mode,
  1722. msm_is_mode_seamless_poms(adj_mode),
  1723. SDE_EVTLOG_FUNC_CASE2);
  1724. SDE_DEBUG_ENC(sde_enc, "switch to command physical encoder\n");
  1725. }
  1726. }
  1727. static struct drm_connector *_sde_encoder_get_connector(
  1728. struct drm_device *dev, struct drm_encoder *drm_enc)
  1729. {
  1730. struct drm_connector_list_iter conn_iter;
  1731. struct drm_connector *conn = NULL, *conn_search;
  1732. drm_connector_list_iter_begin(dev, &conn_iter);
  1733. drm_for_each_connector_iter(conn_search, &conn_iter) {
  1734. if (conn_search->encoder == drm_enc) {
  1735. conn = conn_search;
  1736. break;
  1737. }
  1738. }
  1739. drm_connector_list_iter_end(&conn_iter);
  1740. return conn;
  1741. }
  1742. static void _sde_encoder_virt_populate_hw_res(struct drm_encoder *drm_enc)
  1743. {
  1744. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  1745. struct sde_kms *sde_kms = sde_encoder_get_kms(drm_enc);
  1746. struct sde_rm_hw_iter pp_iter, qdss_iter;
  1747. struct sde_rm_hw_iter dsc_iter, vdc_iter;
  1748. struct sde_rm_hw_request request_hw;
  1749. int i;
  1750. sde_rm_init_hw_iter(&pp_iter, drm_enc->base.id, SDE_HW_BLK_PINGPONG);
  1751. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  1752. sde_enc->hw_pp[i] = NULL;
  1753. if (!sde_rm_get_hw(&sde_kms->rm, &pp_iter))
  1754. break;
  1755. sde_enc->hw_pp[i] = (struct sde_hw_pingpong *) pp_iter.hw;
  1756. }
  1757. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1758. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  1759. if (phys) {
  1760. sde_rm_init_hw_iter(&qdss_iter, drm_enc->base.id,
  1761. SDE_HW_BLK_QDSS);
  1762. for (i = 0; i < QDSS_MAX; i++) {
  1763. if (sde_rm_get_hw(&sde_kms->rm, &qdss_iter)) {
  1764. phys->hw_qdss =
  1765. (struct sde_hw_qdss *)qdss_iter.hw;
  1766. break;
  1767. }
  1768. }
  1769. }
  1770. }
  1771. sde_rm_init_hw_iter(&dsc_iter, drm_enc->base.id, SDE_HW_BLK_DSC);
  1772. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  1773. sde_enc->hw_dsc[i] = NULL;
  1774. if (!sde_rm_get_hw(&sde_kms->rm, &dsc_iter))
  1775. break;
  1776. sde_enc->hw_dsc[i] = (struct sde_hw_dsc *) dsc_iter.hw;
  1777. }
  1778. sde_rm_init_hw_iter(&vdc_iter, drm_enc->base.id, SDE_HW_BLK_VDC);
  1779. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  1780. sde_enc->hw_vdc[i] = NULL;
  1781. if (!sde_rm_get_hw(&sde_kms->rm, &vdc_iter))
  1782. break;
  1783. sde_enc->hw_vdc[i] = (struct sde_hw_vdc *) vdc_iter.hw;
  1784. }
  1785. /* Get PP for DSC configuration */
  1786. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  1787. struct sde_hw_pingpong *pp = NULL;
  1788. unsigned long features = 0;
  1789. if (!sde_enc->hw_dsc[i])
  1790. continue;
  1791. request_hw.id = sde_enc->hw_dsc[i]->base.id;
  1792. request_hw.type = SDE_HW_BLK_PINGPONG;
  1793. if (!sde_rm_request_hw_blk(&sde_kms->rm, &request_hw))
  1794. break;
  1795. pp = (struct sde_hw_pingpong *) request_hw.hw;
  1796. features = pp->ops.get_hw_caps(pp);
  1797. if (test_bit(SDE_PINGPONG_DSC, &features))
  1798. sde_enc->hw_dsc_pp[i] = pp;
  1799. else
  1800. sde_enc->hw_dsc_pp[i] = NULL;
  1801. }
  1802. }
  1803. static int sde_encoder_virt_modeset_rc(struct drm_encoder *drm_enc,
  1804. struct drm_display_mode *adj_mode, bool pre_modeset)
  1805. {
  1806. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  1807. enum sde_intf_mode intf_mode;
  1808. int ret;
  1809. bool is_cmd_mode;
  1810. if (sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE))
  1811. is_cmd_mode = true;
  1812. if (pre_modeset) {
  1813. intf_mode = sde_encoder_get_intf_mode(drm_enc);
  1814. if (msm_is_mode_seamless_dms(adj_mode) ||
  1815. (msm_is_mode_seamless_dyn_clk(adj_mode) &&
  1816. is_cmd_mode)) {
  1817. /* restore resource state before releasing them */
  1818. ret = sde_encoder_resource_control(drm_enc,
  1819. SDE_ENC_RC_EVENT_PRE_MODESET);
  1820. if (ret) {
  1821. SDE_ERROR_ENC(sde_enc,
  1822. "sde resource control failed: %d\n",
  1823. ret);
  1824. return ret;
  1825. }
  1826. /*
  1827. * Disable dce before switching the mode and after pre-
  1828. * modeset to guarantee previous kickoff has finished.
  1829. */
  1830. sde_encoder_dce_disable(sde_enc);
  1831. } else if (msm_is_mode_seamless_poms(adj_mode)) {
  1832. _sde_encoder_modeset_helper_locked(drm_enc,
  1833. SDE_ENC_RC_EVENT_PRE_MODESET);
  1834. sde_encoder_virt_mode_switch(drm_enc, intf_mode,
  1835. adj_mode);
  1836. }
  1837. } else {
  1838. if (msm_is_mode_seamless_dms(adj_mode) ||
  1839. (msm_is_mode_seamless_dyn_clk(adj_mode) &&
  1840. is_cmd_mode))
  1841. sde_encoder_resource_control(&sde_enc->base,
  1842. SDE_ENC_RC_EVENT_POST_MODESET);
  1843. else if (msm_is_mode_seamless_poms(adj_mode))
  1844. _sde_encoder_modeset_helper_locked(drm_enc,
  1845. SDE_ENC_RC_EVENT_POST_MODESET);
  1846. }
  1847. return 0;
  1848. }
  1849. static void sde_encoder_virt_mode_set(struct drm_encoder *drm_enc,
  1850. struct drm_display_mode *mode,
  1851. struct drm_display_mode *adj_mode)
  1852. {
  1853. struct sde_encoder_virt *sde_enc;
  1854. struct sde_kms *sde_kms;
  1855. struct drm_connector *conn;
  1856. int i = 0, ret;
  1857. if (!drm_enc) {
  1858. SDE_ERROR("invalid encoder\n");
  1859. return;
  1860. }
  1861. if (!sde_kms_power_resource_is_enabled(drm_enc->dev)) {
  1862. SDE_ERROR("power resource is not enabled\n");
  1863. return;
  1864. }
  1865. sde_kms = sde_encoder_get_kms(drm_enc);
  1866. if (!sde_kms)
  1867. return;
  1868. sde_enc = to_sde_encoder_virt(drm_enc);
  1869. SDE_DEBUG_ENC(sde_enc, "\n");
  1870. SDE_EVT32(DRMID(drm_enc));
  1871. /*
  1872. * cache the crtc in sde_enc on enable for duration of use case
  1873. * for correctly servicing asynchronous irq events and timers
  1874. */
  1875. if (!drm_enc->crtc) {
  1876. SDE_ERROR("invalid crtc\n");
  1877. return;
  1878. }
  1879. sde_enc->crtc = drm_enc->crtc;
  1880. sde_crtc_set_qos_dirty(drm_enc->crtc);
  1881. /* get and store the mode_info */
  1882. conn = _sde_encoder_get_connector(sde_kms->dev, drm_enc);
  1883. if (!conn) {
  1884. SDE_ERROR_ENC(sde_enc, "failed to find attached connector\n");
  1885. return;
  1886. } else if (!conn->state) {
  1887. SDE_ERROR_ENC(sde_enc, "invalid connector state\n");
  1888. return;
  1889. }
  1890. sde_connector_state_get_mode_info(conn->state, &sde_enc->mode_info);
  1891. sde_encoder_dce_set_bpp(sde_enc->mode_info, sde_enc->crtc);
  1892. /* release resources before seamless mode change */
  1893. ret = sde_encoder_virt_modeset_rc(drm_enc, adj_mode, true);
  1894. if (ret)
  1895. return;
  1896. /* reserve dynamic resources now, indicating non test-only */
  1897. ret = sde_rm_reserve(&sde_kms->rm, drm_enc, drm_enc->crtc->state,
  1898. conn->state, false);
  1899. if (ret) {
  1900. SDE_ERROR_ENC(sde_enc,
  1901. "failed to reserve hw resources, %d\n", ret);
  1902. return;
  1903. }
  1904. /* assign the reserved HW blocks to this encoder */
  1905. _sde_encoder_virt_populate_hw_res(drm_enc);
  1906. /* perform mode_set on phys_encs */
  1907. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1908. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  1909. if (phys) {
  1910. if (!sde_enc->hw_pp[i] && sde_enc->topology.num_intf) {
  1911. SDE_ERROR_ENC(sde_enc,
  1912. "invalid pingpong block for the encoder\n");
  1913. return;
  1914. }
  1915. phys->hw_pp = sde_enc->hw_pp[i];
  1916. phys->connector = conn->state->connector;
  1917. if (phys->ops.mode_set)
  1918. phys->ops.mode_set(phys, mode, adj_mode);
  1919. }
  1920. }
  1921. /* update resources after seamless mode change */
  1922. sde_encoder_virt_modeset_rc(drm_enc, adj_mode, false);
  1923. }
  1924. void sde_encoder_control_te(struct drm_encoder *drm_enc, bool enable)
  1925. {
  1926. struct sde_encoder_virt *sde_enc;
  1927. struct sde_encoder_phys *phys;
  1928. int i;
  1929. if (!drm_enc) {
  1930. SDE_ERROR("invalid parameters\n");
  1931. return;
  1932. }
  1933. sde_enc = to_sde_encoder_virt(drm_enc);
  1934. if (!sde_enc) {
  1935. SDE_ERROR("invalid sde encoder\n");
  1936. return;
  1937. }
  1938. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  1939. phys = sde_enc->phys_encs[i];
  1940. if (phys && phys->ops.control_te)
  1941. phys->ops.control_te(phys, enable);
  1942. }
  1943. }
  1944. static int _sde_encoder_input_connect(struct input_handler *handler,
  1945. struct input_dev *dev, const struct input_device_id *id)
  1946. {
  1947. struct input_handle *handle;
  1948. int rc = 0;
  1949. handle = kzalloc(sizeof(*handle), GFP_KERNEL);
  1950. if (!handle)
  1951. return -ENOMEM;
  1952. handle->dev = dev;
  1953. handle->handler = handler;
  1954. handle->name = handler->name;
  1955. rc = input_register_handle(handle);
  1956. if (rc) {
  1957. pr_err("failed to register input handle\n");
  1958. goto error;
  1959. }
  1960. rc = input_open_device(handle);
  1961. if (rc) {
  1962. pr_err("failed to open input device\n");
  1963. goto error_unregister;
  1964. }
  1965. return 0;
  1966. error_unregister:
  1967. input_unregister_handle(handle);
  1968. error:
  1969. kfree(handle);
  1970. return rc;
  1971. }
  1972. static void _sde_encoder_input_disconnect(struct input_handle *handle)
  1973. {
  1974. input_close_device(handle);
  1975. input_unregister_handle(handle);
  1976. kfree(handle);
  1977. }
  1978. /**
  1979. * Structure for specifying event parameters on which to receive callbacks.
  1980. * This structure will trigger a callback in case of a touch event (specified by
  1981. * EV_ABS) where there is a change in X and Y coordinates,
  1982. */
  1983. static const struct input_device_id sde_input_ids[] = {
  1984. {
  1985. .flags = INPUT_DEVICE_ID_MATCH_EVBIT,
  1986. .evbit = { BIT_MASK(EV_ABS) },
  1987. .absbit = { [BIT_WORD(ABS_MT_POSITION_X)] =
  1988. BIT_MASK(ABS_MT_POSITION_X) |
  1989. BIT_MASK(ABS_MT_POSITION_Y) },
  1990. },
  1991. { },
  1992. };
  1993. static void _sde_encoder_input_handler_register(
  1994. struct drm_encoder *drm_enc)
  1995. {
  1996. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  1997. int rc;
  1998. if (!sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE))
  1999. return;
  2000. if (sde_enc->input_handler && !sde_enc->input_handler->private) {
  2001. sde_enc->input_handler->private = sde_enc;
  2002. /* register input handler if not already registered */
  2003. rc = input_register_handler(sde_enc->input_handler);
  2004. if (rc) {
  2005. SDE_ERROR("input_handler_register failed, rc= %d\n",
  2006. rc);
  2007. kfree(sde_enc->input_handler);
  2008. }
  2009. }
  2010. }
  2011. static void _sde_encoder_input_handler_unregister(
  2012. struct drm_encoder *drm_enc)
  2013. {
  2014. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  2015. if (!sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE))
  2016. return;
  2017. if (sde_enc->input_handler && sde_enc->input_handler->private) {
  2018. input_unregister_handler(sde_enc->input_handler);
  2019. sde_enc->input_handler->private = NULL;
  2020. }
  2021. }
  2022. static int _sde_encoder_input_handler(
  2023. struct sde_encoder_virt *sde_enc)
  2024. {
  2025. struct input_handler *input_handler = NULL;
  2026. int rc = 0;
  2027. if (sde_enc->input_handler) {
  2028. SDE_ERROR_ENC(sde_enc,
  2029. "input_handle is active. unexpected\n");
  2030. return -EINVAL;
  2031. }
  2032. input_handler = kzalloc(sizeof(*sde_enc->input_handler), GFP_KERNEL);
  2033. if (!input_handler)
  2034. return -ENOMEM;
  2035. input_handler->event = sde_encoder_input_event_handler;
  2036. input_handler->connect = _sde_encoder_input_connect;
  2037. input_handler->disconnect = _sde_encoder_input_disconnect;
  2038. input_handler->name = "sde";
  2039. input_handler->id_table = sde_input_ids;
  2040. sde_enc->input_handler = input_handler;
  2041. return rc;
  2042. }
  2043. static void _sde_encoder_virt_enable_helper(struct drm_encoder *drm_enc)
  2044. {
  2045. struct sde_encoder_virt *sde_enc = NULL;
  2046. struct sde_kms *sde_kms;
  2047. if (!drm_enc || !drm_enc->dev || !drm_enc->dev->dev_private) {
  2048. SDE_ERROR("invalid parameters\n");
  2049. return;
  2050. }
  2051. sde_kms = sde_encoder_get_kms(drm_enc);
  2052. if (!sde_kms)
  2053. return;
  2054. sde_enc = to_sde_encoder_virt(drm_enc);
  2055. if (!sde_enc || !sde_enc->cur_master) {
  2056. SDE_DEBUG("invalid sde encoder/master\n");
  2057. return;
  2058. }
  2059. if (sde_enc->disp_info.intf_type == DRM_MODE_CONNECTOR_DisplayPort &&
  2060. sde_enc->cur_master->hw_mdptop &&
  2061. sde_enc->cur_master->hw_mdptop->ops.intf_audio_select)
  2062. sde_enc->cur_master->hw_mdptop->ops.intf_audio_select(
  2063. sde_enc->cur_master->hw_mdptop);
  2064. if (sde_enc->cur_master->hw_mdptop &&
  2065. sde_enc->cur_master->hw_mdptop->ops.reset_ubwc)
  2066. sde_enc->cur_master->hw_mdptop->ops.reset_ubwc(
  2067. sde_enc->cur_master->hw_mdptop,
  2068. sde_kms->catalog);
  2069. if (sde_enc->cur_master->hw_ctl &&
  2070. sde_enc->cur_master->hw_ctl->ops.setup_intf_cfg_v1 &&
  2071. !sde_enc->cur_master->cont_splash_enabled)
  2072. sde_enc->cur_master->hw_ctl->ops.setup_intf_cfg_v1(
  2073. sde_enc->cur_master->hw_ctl,
  2074. &sde_enc->cur_master->intf_cfg_v1);
  2075. _sde_encoder_update_vsync_source(sde_enc, &sde_enc->disp_info, false);
  2076. sde_encoder_control_te(drm_enc, true);
  2077. memset(&sde_enc->prv_conn_roi, 0, sizeof(sde_enc->prv_conn_roi));
  2078. memset(&sde_enc->cur_conn_roi, 0, sizeof(sde_enc->cur_conn_roi));
  2079. }
  2080. static void _sde_encoder_setup_dither(struct sde_encoder_phys *phys)
  2081. {
  2082. void *dither_cfg = NULL;
  2083. int ret = 0, i = 0;
  2084. size_t len = 0;
  2085. enum sde_rm_topology_name topology;
  2086. struct drm_encoder *drm_enc;
  2087. struct msm_display_dsc_info *dsc = NULL;
  2088. struct sde_encoder_virt *sde_enc;
  2089. struct sde_hw_pingpong *hw_pp;
  2090. u32 bpp, bpc;
  2091. if (!phys || !phys->connector || !phys->hw_pp ||
  2092. !phys->hw_pp->ops.setup_dither || !phys->parent)
  2093. return;
  2094. topology = sde_connector_get_topology_name(phys->connector);
  2095. if ((topology == SDE_RM_TOPOLOGY_PPSPLIT) &&
  2096. (phys->split_role == ENC_ROLE_SLAVE))
  2097. return;
  2098. drm_enc = phys->parent;
  2099. sde_enc = to_sde_encoder_virt(drm_enc);
  2100. dsc = &sde_enc->mode_info.comp_info.dsc_info;
  2101. bpc = dsc->config.bits_per_component;
  2102. bpp = dsc->config.bits_per_pixel;
  2103. /* disable dither for 10 bpp or 10bpc dsc config */
  2104. if (bpp == 10 || bpc == 10) {
  2105. phys->hw_pp->ops.setup_dither(phys->hw_pp, NULL, 0);
  2106. return;
  2107. }
  2108. ret = sde_connector_get_dither_cfg(phys->connector,
  2109. phys->connector->state, &dither_cfg,
  2110. &len, sde_enc->idle_pc_restore);
  2111. /* skip reg writes when return values are invalid or no data */
  2112. if (ret && ret == -ENODATA)
  2113. return;
  2114. if (TOPOLOGY_DUALPIPE_MERGE_MODE(topology)) {
  2115. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  2116. hw_pp = sde_enc->hw_pp[i];
  2117. phys->hw_pp->ops.setup_dither(hw_pp,
  2118. dither_cfg, len);
  2119. }
  2120. } else {
  2121. phys->hw_pp->ops.setup_dither(phys->hw_pp,
  2122. dither_cfg, len);
  2123. }
  2124. }
  2125. void sde_encoder_virt_restore(struct drm_encoder *drm_enc)
  2126. {
  2127. struct sde_encoder_virt *sde_enc = NULL;
  2128. int i;
  2129. if (!drm_enc) {
  2130. SDE_ERROR("invalid encoder\n");
  2131. return;
  2132. }
  2133. sde_enc = to_sde_encoder_virt(drm_enc);
  2134. if (!sde_enc->cur_master) {
  2135. SDE_DEBUG("virt encoder has no master\n");
  2136. return;
  2137. }
  2138. memset(&sde_enc->cur_master->intf_cfg_v1, 0,
  2139. sizeof(sde_enc->cur_master->intf_cfg_v1));
  2140. sde_enc->idle_pc_restore = true;
  2141. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2142. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2143. if (!phys)
  2144. continue;
  2145. if (phys->hw_ctl && phys->hw_ctl->ops.clear_pending_flush)
  2146. phys->hw_ctl->ops.clear_pending_flush(phys->hw_ctl);
  2147. if ((phys != sde_enc->cur_master) && phys->ops.restore)
  2148. phys->ops.restore(phys);
  2149. _sde_encoder_setup_dither(phys);
  2150. }
  2151. if (sde_enc->cur_master->ops.restore)
  2152. sde_enc->cur_master->ops.restore(sde_enc->cur_master);
  2153. _sde_encoder_virt_enable_helper(drm_enc);
  2154. }
  2155. static void sde_encoder_off_work(struct kthread_work *work)
  2156. {
  2157. struct sde_encoder_virt *sde_enc = container_of(work,
  2158. struct sde_encoder_virt, delayed_off_work.work);
  2159. struct drm_encoder *drm_enc;
  2160. if (!sde_enc) {
  2161. SDE_ERROR("invalid sde encoder\n");
  2162. return;
  2163. }
  2164. drm_enc = &sde_enc->base;
  2165. SDE_ATRACE_BEGIN("sde_encoder_off_work");
  2166. sde_encoder_idle_request(drm_enc);
  2167. SDE_ATRACE_END("sde_encoder_off_work");
  2168. }
  2169. static void sde_encoder_virt_enable(struct drm_encoder *drm_enc)
  2170. {
  2171. struct sde_encoder_virt *sde_enc = NULL;
  2172. int i, ret = 0;
  2173. struct msm_compression_info *comp_info = NULL;
  2174. struct drm_display_mode *cur_mode = NULL;
  2175. struct msm_display_info *disp_info;
  2176. if (!drm_enc) {
  2177. SDE_ERROR("invalid encoder\n");
  2178. return;
  2179. }
  2180. sde_enc = to_sde_encoder_virt(drm_enc);
  2181. disp_info = &sde_enc->disp_info;
  2182. if (!sde_kms_power_resource_is_enabled(drm_enc->dev)) {
  2183. SDE_ERROR("power resource is not enabled\n");
  2184. return;
  2185. }
  2186. if (drm_enc->crtc && !sde_enc->crtc)
  2187. sde_enc->crtc = drm_enc->crtc;
  2188. comp_info = &sde_enc->mode_info.comp_info;
  2189. cur_mode = &sde_enc->base.crtc->state->adjusted_mode;
  2190. SDE_DEBUG_ENC(sde_enc, "\n");
  2191. SDE_EVT32(DRMID(drm_enc), cur_mode->hdisplay, cur_mode->vdisplay);
  2192. sde_enc->cur_master = NULL;
  2193. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2194. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2195. if (phys && phys->ops.is_master && phys->ops.is_master(phys)) {
  2196. SDE_DEBUG_ENC(sde_enc, "master is now idx %d\n", i);
  2197. sde_enc->cur_master = phys;
  2198. break;
  2199. }
  2200. }
  2201. if (!sde_enc->cur_master) {
  2202. SDE_ERROR("virt encoder has no master! num_phys %d\n", i);
  2203. return;
  2204. }
  2205. _sde_encoder_input_handler_register(drm_enc);
  2206. if (!(msm_is_mode_seamless_vrr(cur_mode)
  2207. || msm_is_mode_seamless_dms(cur_mode)
  2208. || msm_is_mode_seamless_dyn_clk(cur_mode)))
  2209. kthread_init_delayed_work(&sde_enc->delayed_off_work,
  2210. sde_encoder_off_work);
  2211. ret = sde_encoder_resource_control(drm_enc, SDE_ENC_RC_EVENT_KICKOFF);
  2212. if (ret) {
  2213. SDE_ERROR_ENC(sde_enc, "sde resource control failed: %d\n",
  2214. ret);
  2215. return;
  2216. }
  2217. memset(&sde_enc->cur_master->intf_cfg_v1, 0,
  2218. sizeof(sde_enc->cur_master->intf_cfg_v1));
  2219. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2220. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2221. if (!phys)
  2222. continue;
  2223. phys->comp_type = comp_info->comp_type;
  2224. phys->comp_ratio = comp_info->comp_ratio;
  2225. phys->frame_trigger_mode = sde_enc->frame_trigger_mode;
  2226. phys->poms_align_vsync = disp_info->poms_align_vsync;
  2227. if (phys->comp_type == MSM_DISPLAY_COMPRESSION_DSC) {
  2228. phys->dsc_extra_pclk_cycle_cnt =
  2229. comp_info->dsc_info.pclk_per_line;
  2230. phys->dsc_extra_disp_width =
  2231. comp_info->dsc_info.extra_width;
  2232. phys->dce_bytes_per_line =
  2233. comp_info->dsc_info.bytes_per_pkt *
  2234. comp_info->dsc_info.pkt_per_line;
  2235. } else if (phys->comp_type == MSM_DISPLAY_COMPRESSION_VDC) {
  2236. phys->dce_bytes_per_line =
  2237. comp_info->vdc_info.bytes_per_pkt *
  2238. comp_info->vdc_info.pkt_per_line;
  2239. }
  2240. if (phys != sde_enc->cur_master) {
  2241. /**
  2242. * on DMS request, the encoder will be enabled
  2243. * already. Invoke restore to reconfigure the
  2244. * new mode.
  2245. */
  2246. if ((msm_is_mode_seamless_dms(cur_mode) ||
  2247. msm_is_mode_seamless_dyn_clk(cur_mode)) &&
  2248. phys->ops.restore)
  2249. phys->ops.restore(phys);
  2250. else if (phys->ops.enable)
  2251. phys->ops.enable(phys);
  2252. }
  2253. if (sde_enc->misr_enable && phys->ops.setup_misr &&
  2254. (sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_VIDEO_MODE)))
  2255. phys->ops.setup_misr(phys, true,
  2256. sde_enc->misr_frame_count);
  2257. }
  2258. if ((msm_is_mode_seamless_dms(cur_mode) ||
  2259. msm_is_mode_seamless_dyn_clk(cur_mode)) &&
  2260. sde_enc->cur_master->ops.restore)
  2261. sde_enc->cur_master->ops.restore(sde_enc->cur_master);
  2262. else if (sde_enc->cur_master->ops.enable)
  2263. sde_enc->cur_master->ops.enable(sde_enc->cur_master);
  2264. _sde_encoder_virt_enable_helper(drm_enc);
  2265. }
  2266. static void sde_encoder_virt_disable(struct drm_encoder *drm_enc)
  2267. {
  2268. struct sde_encoder_virt *sde_enc = NULL;
  2269. struct sde_kms *sde_kms;
  2270. enum sde_intf_mode intf_mode;
  2271. int i = 0;
  2272. if (!drm_enc) {
  2273. SDE_ERROR("invalid encoder\n");
  2274. return;
  2275. } else if (!drm_enc->dev) {
  2276. SDE_ERROR("invalid dev\n");
  2277. return;
  2278. } else if (!drm_enc->dev->dev_private) {
  2279. SDE_ERROR("invalid dev_private\n");
  2280. return;
  2281. }
  2282. if (!sde_kms_power_resource_is_enabled(drm_enc->dev)) {
  2283. SDE_ERROR("power resource is not enabled\n");
  2284. return;
  2285. }
  2286. sde_enc = to_sde_encoder_virt(drm_enc);
  2287. SDE_DEBUG_ENC(sde_enc, "\n");
  2288. sde_kms = sde_encoder_get_kms(&sde_enc->base);
  2289. if (!sde_kms)
  2290. return;
  2291. intf_mode = sde_encoder_get_intf_mode(drm_enc);
  2292. SDE_EVT32(DRMID(drm_enc));
  2293. /* wait for idle */
  2294. sde_encoder_wait_for_event(drm_enc, MSM_ENC_TX_COMPLETE);
  2295. _sde_encoder_input_handler_unregister(drm_enc);
  2296. /*
  2297. * For primary command mode and video mode encoders, execute the
  2298. * resource control pre-stop operations before the physical encoders
  2299. * are disabled, to allow the rsc to transition its states properly.
  2300. *
  2301. * For other encoder types, rsc should not be enabled until after
  2302. * they have been fully disabled, so delay the pre-stop operations
  2303. * until after the physical disable calls have returned.
  2304. */
  2305. if (sde_enc->disp_info.display_type == SDE_CONNECTOR_PRIMARY &&
  2306. (intf_mode == INTF_MODE_CMD || intf_mode == INTF_MODE_VIDEO)) {
  2307. sde_encoder_resource_control(drm_enc,
  2308. SDE_ENC_RC_EVENT_PRE_STOP);
  2309. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2310. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2311. if (phys && phys->ops.disable)
  2312. phys->ops.disable(phys);
  2313. }
  2314. } else {
  2315. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2316. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2317. if (phys && phys->ops.disable)
  2318. phys->ops.disable(phys);
  2319. }
  2320. sde_encoder_resource_control(drm_enc,
  2321. SDE_ENC_RC_EVENT_PRE_STOP);
  2322. }
  2323. /*
  2324. * disable dce after the transfer is complete (for command mode)
  2325. * and after physical encoder is disabled, to make sure timing
  2326. * engine is already disabled (for video mode).
  2327. */
  2328. sde_encoder_dce_disable(sde_enc);
  2329. sde_encoder_resource_control(drm_enc, SDE_ENC_RC_EVENT_STOP);
  2330. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2331. if (sde_enc->phys_encs[i]) {
  2332. sde_enc->phys_encs[i]->cont_splash_enabled = false;
  2333. sde_enc->phys_encs[i]->connector = NULL;
  2334. }
  2335. atomic_set(&sde_enc->frame_done_cnt[i], 0);
  2336. }
  2337. sde_enc->cur_master = NULL;
  2338. /*
  2339. * clear the cached crtc in sde_enc on use case finish, after all the
  2340. * outstanding events and timers have been completed
  2341. */
  2342. sde_enc->crtc = NULL;
  2343. memset(&sde_enc->mode_info, 0, sizeof(sde_enc->mode_info));
  2344. SDE_DEBUG_ENC(sde_enc, "encoder disabled\n");
  2345. sde_rm_release(&sde_kms->rm, drm_enc, false);
  2346. }
  2347. void sde_encoder_helper_phys_disable(struct sde_encoder_phys *phys_enc,
  2348. struct sde_encoder_phys_wb *wb_enc)
  2349. {
  2350. struct sde_encoder_virt *sde_enc;
  2351. phys_enc->hw_ctl->ops.reset(phys_enc->hw_ctl);
  2352. sde_encoder_helper_reset_mixers(phys_enc, NULL);
  2353. if (wb_enc) {
  2354. if (wb_enc->hw_wb->ops.bind_pingpong_blk) {
  2355. wb_enc->hw_wb->ops.bind_pingpong_blk(wb_enc->hw_wb,
  2356. false, phys_enc->hw_pp->idx);
  2357. if (phys_enc->hw_ctl->ops.update_bitmask)
  2358. phys_enc->hw_ctl->ops.update_bitmask(
  2359. phys_enc->hw_ctl,
  2360. SDE_HW_FLUSH_WB,
  2361. wb_enc->hw_wb->idx, true);
  2362. }
  2363. } else {
  2364. if (phys_enc->hw_intf->ops.bind_pingpong_blk) {
  2365. phys_enc->hw_intf->ops.bind_pingpong_blk(
  2366. phys_enc->hw_intf, false,
  2367. phys_enc->hw_pp->idx);
  2368. if (phys_enc->hw_ctl->ops.update_bitmask)
  2369. phys_enc->hw_ctl->ops.update_bitmask(
  2370. phys_enc->hw_ctl,
  2371. SDE_HW_FLUSH_INTF,
  2372. phys_enc->hw_intf->idx, true);
  2373. }
  2374. }
  2375. if (phys_enc->hw_pp && phys_enc->hw_pp->ops.reset_3d_mode) {
  2376. phys_enc->hw_pp->ops.reset_3d_mode(phys_enc->hw_pp);
  2377. if (phys_enc->hw_ctl->ops.update_bitmask &&
  2378. phys_enc->hw_pp->merge_3d)
  2379. phys_enc->hw_ctl->ops.update_bitmask(
  2380. phys_enc->hw_ctl, SDE_HW_FLUSH_MERGE_3D,
  2381. phys_enc->hw_pp->merge_3d->idx, true);
  2382. }
  2383. if (phys_enc->hw_cdm && phys_enc->hw_cdm->ops.bind_pingpong_blk &&
  2384. phys_enc->hw_pp) {
  2385. phys_enc->hw_cdm->ops.bind_pingpong_blk(phys_enc->hw_cdm,
  2386. false, phys_enc->hw_pp->idx);
  2387. if (phys_enc->hw_ctl->ops.update_bitmask)
  2388. phys_enc->hw_ctl->ops.update_bitmask(
  2389. phys_enc->hw_ctl, SDE_HW_FLUSH_CDM,
  2390. phys_enc->hw_cdm->idx, true);
  2391. }
  2392. sde_enc = to_sde_encoder_virt(phys_enc->parent);
  2393. if (phys_enc == sde_enc->cur_master && phys_enc->hw_pp &&
  2394. phys_enc->hw_ctl->ops.reset_post_disable)
  2395. phys_enc->hw_ctl->ops.reset_post_disable(
  2396. phys_enc->hw_ctl, &phys_enc->intf_cfg_v1,
  2397. phys_enc->hw_pp->merge_3d ?
  2398. phys_enc->hw_pp->merge_3d->idx : 0);
  2399. phys_enc->hw_ctl->ops.trigger_flush(phys_enc->hw_ctl);
  2400. phys_enc->hw_ctl->ops.trigger_start(phys_enc->hw_ctl);
  2401. }
  2402. static enum sde_intf sde_encoder_get_intf(struct sde_mdss_cfg *catalog,
  2403. enum sde_intf_type type, u32 controller_id)
  2404. {
  2405. int i = 0;
  2406. for (i = 0; i < catalog->intf_count; i++) {
  2407. if (catalog->intf[i].type == type
  2408. && catalog->intf[i].controller_id == controller_id) {
  2409. return catalog->intf[i].id;
  2410. }
  2411. }
  2412. return INTF_MAX;
  2413. }
  2414. static enum sde_wb sde_encoder_get_wb(struct sde_mdss_cfg *catalog,
  2415. enum sde_intf_type type, u32 controller_id)
  2416. {
  2417. if (controller_id < catalog->wb_count)
  2418. return catalog->wb[controller_id].id;
  2419. return WB_MAX;
  2420. }
  2421. void sde_encoder_perf_uidle_status(struct sde_kms *sde_kms,
  2422. struct drm_crtc *crtc)
  2423. {
  2424. struct sde_hw_uidle *uidle;
  2425. struct sde_uidle_cntr cntr;
  2426. struct sde_uidle_status status;
  2427. if (!sde_kms || !crtc || !sde_kms->hw_uidle) {
  2428. pr_err("invalid params %d %d\n",
  2429. !sde_kms, !crtc);
  2430. return;
  2431. }
  2432. /* check if perf counters are enabled and setup */
  2433. if (!sde_kms->catalog->uidle_cfg.perf_cntr_en)
  2434. return;
  2435. uidle = sde_kms->hw_uidle;
  2436. if ((sde_kms->catalog->uidle_cfg.debugfs_perf & SDE_PERF_UIDLE_STATUS)
  2437. && uidle->ops.uidle_get_status) {
  2438. uidle->ops.uidle_get_status(uidle, &status);
  2439. trace_sde_perf_uidle_status(
  2440. crtc->base.id,
  2441. status.uidle_danger_status_0,
  2442. status.uidle_danger_status_1,
  2443. status.uidle_safe_status_0,
  2444. status.uidle_safe_status_1,
  2445. status.uidle_idle_status_0,
  2446. status.uidle_idle_status_1,
  2447. status.uidle_fal_status_0,
  2448. status.uidle_fal_status_1,
  2449. status.uidle_status,
  2450. status.uidle_en_fal10);
  2451. }
  2452. if ((sde_kms->catalog->uidle_cfg.debugfs_perf & SDE_PERF_UIDLE_CNT)
  2453. && uidle->ops.uidle_get_cntr) {
  2454. uidle->ops.uidle_get_cntr(uidle, &cntr);
  2455. trace_sde_perf_uidle_cntr(
  2456. crtc->base.id,
  2457. cntr.fal1_gate_cntr,
  2458. cntr.fal10_gate_cntr,
  2459. cntr.fal_wait_gate_cntr,
  2460. cntr.fal1_num_transitions_cntr,
  2461. cntr.fal10_num_transitions_cntr,
  2462. cntr.min_gate_cntr,
  2463. cntr.max_gate_cntr);
  2464. }
  2465. }
  2466. static void sde_encoder_vblank_callback(struct drm_encoder *drm_enc,
  2467. struct sde_encoder_phys *phy_enc)
  2468. {
  2469. struct sde_encoder_virt *sde_enc = NULL;
  2470. unsigned long lock_flags;
  2471. if (!drm_enc || !phy_enc)
  2472. return;
  2473. SDE_ATRACE_BEGIN("encoder_vblank_callback");
  2474. sde_enc = to_sde_encoder_virt(drm_enc);
  2475. spin_lock_irqsave(&sde_enc->enc_spinlock, lock_flags);
  2476. if (sde_enc->crtc_vblank_cb)
  2477. sde_enc->crtc_vblank_cb(sde_enc->crtc_vblank_cb_data);
  2478. spin_unlock_irqrestore(&sde_enc->enc_spinlock, lock_flags);
  2479. if (phy_enc->sde_kms &&
  2480. phy_enc->sde_kms->catalog->uidle_cfg.debugfs_perf)
  2481. sde_encoder_perf_uidle_status(phy_enc->sde_kms, sde_enc->crtc);
  2482. atomic_inc(&phy_enc->vsync_cnt);
  2483. SDE_ATRACE_END("encoder_vblank_callback");
  2484. }
  2485. static void sde_encoder_underrun_callback(struct drm_encoder *drm_enc,
  2486. struct sde_encoder_phys *phy_enc)
  2487. {
  2488. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  2489. if (!phy_enc)
  2490. return;
  2491. SDE_ATRACE_BEGIN("encoder_underrun_callback");
  2492. atomic_inc(&phy_enc->underrun_cnt);
  2493. SDE_EVT32(DRMID(drm_enc), atomic_read(&phy_enc->underrun_cnt));
  2494. if (sde_enc->cur_master->ops.get_underrun_line_count)
  2495. sde_enc->cur_master->ops.get_underrun_line_count(
  2496. sde_enc->cur_master);
  2497. trace_sde_encoder_underrun(DRMID(drm_enc),
  2498. atomic_read(&phy_enc->underrun_cnt));
  2499. SDE_DBG_CTRL("stop_ftrace");
  2500. SDE_DBG_CTRL("panic_underrun");
  2501. SDE_ATRACE_END("encoder_underrun_callback");
  2502. }
  2503. void sde_encoder_register_vblank_callback(struct drm_encoder *drm_enc,
  2504. void (*vbl_cb)(void *), void *vbl_data)
  2505. {
  2506. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  2507. unsigned long lock_flags;
  2508. bool enable;
  2509. int i;
  2510. enable = vbl_cb ? true : false;
  2511. if (!drm_enc) {
  2512. SDE_ERROR("invalid encoder\n");
  2513. return;
  2514. }
  2515. SDE_DEBUG_ENC(sde_enc, "\n");
  2516. SDE_EVT32(DRMID(drm_enc), enable);
  2517. spin_lock_irqsave(&sde_enc->enc_spinlock, lock_flags);
  2518. sde_enc->crtc_vblank_cb = vbl_cb;
  2519. sde_enc->crtc_vblank_cb_data = vbl_data;
  2520. spin_unlock_irqrestore(&sde_enc->enc_spinlock, lock_flags);
  2521. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2522. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2523. if (phys && phys->ops.control_vblank_irq)
  2524. phys->ops.control_vblank_irq(phys, enable);
  2525. }
  2526. sde_enc->vblank_enabled = enable;
  2527. }
  2528. void sde_encoder_register_frame_event_callback(struct drm_encoder *drm_enc,
  2529. void (*frame_event_cb)(void *, u32 event),
  2530. struct drm_crtc *crtc)
  2531. {
  2532. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  2533. unsigned long lock_flags;
  2534. bool enable;
  2535. enable = frame_event_cb ? true : false;
  2536. if (!drm_enc) {
  2537. SDE_ERROR("invalid encoder\n");
  2538. return;
  2539. }
  2540. SDE_DEBUG_ENC(sde_enc, "\n");
  2541. SDE_EVT32(DRMID(drm_enc), enable, 0);
  2542. spin_lock_irqsave(&sde_enc->enc_spinlock, lock_flags);
  2543. sde_enc->crtc_frame_event_cb = frame_event_cb;
  2544. sde_enc->crtc_frame_event_cb_data.crtc = crtc;
  2545. spin_unlock_irqrestore(&sde_enc->enc_spinlock, lock_flags);
  2546. }
  2547. static void sde_encoder_frame_done_callback(
  2548. struct drm_encoder *drm_enc,
  2549. struct sde_encoder_phys *ready_phys, u32 event)
  2550. {
  2551. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  2552. unsigned int i;
  2553. bool trigger = true;
  2554. bool is_cmd_mode = false;
  2555. enum sde_rm_topology_name topology = SDE_RM_TOPOLOGY_NONE;
  2556. if (!drm_enc || !sde_enc->cur_master) {
  2557. SDE_ERROR("invalid param: drm_enc %pK, cur_master %pK\n",
  2558. drm_enc, drm_enc ? sde_enc->cur_master : 0);
  2559. return;
  2560. }
  2561. sde_enc->crtc_frame_event_cb_data.connector =
  2562. sde_enc->cur_master->connector;
  2563. if (sde_encoder_check_curr_mode(drm_enc, MSM_DISPLAY_CMD_MODE))
  2564. is_cmd_mode = true;
  2565. if (event & (SDE_ENCODER_FRAME_EVENT_DONE
  2566. | SDE_ENCODER_FRAME_EVENT_ERROR
  2567. | SDE_ENCODER_FRAME_EVENT_PANEL_DEAD) && is_cmd_mode) {
  2568. if (ready_phys->connector)
  2569. topology = sde_connector_get_topology_name(
  2570. ready_phys->connector);
  2571. /* One of the physical encoders has become idle */
  2572. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2573. if (sde_enc->phys_encs[i] == ready_phys) {
  2574. SDE_EVT32_VERBOSE(DRMID(drm_enc), i,
  2575. atomic_read(&sde_enc->frame_done_cnt[i]));
  2576. if (!atomic_add_unless(
  2577. &sde_enc->frame_done_cnt[i], 1, 1)) {
  2578. SDE_EVT32(DRMID(drm_enc), event,
  2579. ready_phys->intf_idx,
  2580. SDE_EVTLOG_ERROR);
  2581. SDE_ERROR_ENC(sde_enc,
  2582. "intf idx:%d, event:%d\n",
  2583. ready_phys->intf_idx, event);
  2584. return;
  2585. }
  2586. }
  2587. if (topology != SDE_RM_TOPOLOGY_PPSPLIT &&
  2588. atomic_read(&sde_enc->frame_done_cnt[i]) != 1)
  2589. trigger = false;
  2590. }
  2591. if (trigger) {
  2592. if (sde_enc->crtc_frame_event_cb)
  2593. sde_enc->crtc_frame_event_cb(
  2594. &sde_enc->crtc_frame_event_cb_data,
  2595. event);
  2596. for (i = 0; i < sde_enc->num_phys_encs; i++)
  2597. atomic_set(&sde_enc->frame_done_cnt[i], 0);
  2598. }
  2599. } else if (sde_enc->crtc_frame_event_cb) {
  2600. sde_enc->crtc_frame_event_cb(
  2601. &sde_enc->crtc_frame_event_cb_data, event);
  2602. }
  2603. }
  2604. static void sde_encoder_get_qsync_fps_callback(
  2605. struct drm_encoder *drm_enc,
  2606. u32 *qsync_fps)
  2607. {
  2608. struct msm_display_info *disp_info;
  2609. struct sde_encoder_virt *sde_enc;
  2610. if (!qsync_fps)
  2611. return;
  2612. *qsync_fps = 0;
  2613. if (!drm_enc) {
  2614. SDE_ERROR("invalid drm encoder\n");
  2615. return;
  2616. }
  2617. sde_enc = to_sde_encoder_virt(drm_enc);
  2618. disp_info = &sde_enc->disp_info;
  2619. *qsync_fps = disp_info->qsync_min_fps;
  2620. }
  2621. int sde_encoder_idle_request(struct drm_encoder *drm_enc)
  2622. {
  2623. struct sde_encoder_virt *sde_enc;
  2624. if (!drm_enc) {
  2625. SDE_ERROR("invalid drm encoder\n");
  2626. return -EINVAL;
  2627. }
  2628. sde_enc = to_sde_encoder_virt(drm_enc);
  2629. sde_encoder_resource_control(&sde_enc->base,
  2630. SDE_ENC_RC_EVENT_ENTER_IDLE);
  2631. return 0;
  2632. }
  2633. /**
  2634. * _sde_encoder_trigger_flush - trigger flush for a physical encoder
  2635. * drm_enc: Pointer to drm encoder structure
  2636. * phys: Pointer to physical encoder structure
  2637. * extra_flush: Additional bit mask to include in flush trigger
  2638. */
  2639. static inline void _sde_encoder_trigger_flush(struct drm_encoder *drm_enc,
  2640. struct sde_encoder_phys *phys,
  2641. struct sde_ctl_flush_cfg *extra_flush)
  2642. {
  2643. struct sde_hw_ctl *ctl;
  2644. unsigned long lock_flags;
  2645. struct sde_encoder_virt *sde_enc;
  2646. int pend_ret_fence_cnt;
  2647. struct sde_connector *c_conn;
  2648. if (!drm_enc || !phys) {
  2649. SDE_ERROR("invalid argument(s), drm_enc %d, phys_enc %d\n",
  2650. !drm_enc, !phys);
  2651. return;
  2652. }
  2653. sde_enc = to_sde_encoder_virt(drm_enc);
  2654. c_conn = to_sde_connector(phys->connector);
  2655. if (!phys->hw_pp) {
  2656. SDE_ERROR("invalid pingpong hw\n");
  2657. return;
  2658. }
  2659. ctl = phys->hw_ctl;
  2660. if (!ctl || !phys->ops.trigger_flush) {
  2661. SDE_ERROR("missing ctl/trigger cb\n");
  2662. return;
  2663. }
  2664. if (phys->split_role == ENC_ROLE_SKIP) {
  2665. SDE_DEBUG_ENC(to_sde_encoder_virt(phys->parent),
  2666. "skip flush pp%d ctl%d\n",
  2667. phys->hw_pp->idx - PINGPONG_0,
  2668. ctl->idx - CTL_0);
  2669. return;
  2670. }
  2671. /* update pending counts and trigger kickoff ctl flush atomically */
  2672. spin_lock_irqsave(&sde_enc->enc_spinlock, lock_flags);
  2673. if (phys->ops.is_master && phys->ops.is_master(phys))
  2674. atomic_inc(&phys->pending_retire_fence_cnt);
  2675. pend_ret_fence_cnt = atomic_read(&phys->pending_retire_fence_cnt);
  2676. if (phys->hw_intf && phys->hw_intf->cap->type == INTF_DP &&
  2677. ctl->ops.update_bitmask) {
  2678. /* perform peripheral flush on every frame update for dp dsc */
  2679. if (phys->comp_type == MSM_DISPLAY_COMPRESSION_DSC &&
  2680. phys->comp_ratio && c_conn->ops.update_pps) {
  2681. c_conn->ops.update_pps(phys->connector, NULL,
  2682. c_conn->display);
  2683. ctl->ops.update_bitmask(ctl, SDE_HW_FLUSH_PERIPH,
  2684. phys->hw_intf->idx, 1);
  2685. }
  2686. if (sde_enc->dynamic_hdr_updated)
  2687. ctl->ops.update_bitmask(ctl, SDE_HW_FLUSH_PERIPH,
  2688. phys->hw_intf->idx, 1);
  2689. }
  2690. if ((extra_flush && extra_flush->pending_flush_mask)
  2691. && ctl->ops.update_pending_flush)
  2692. ctl->ops.update_pending_flush(ctl, extra_flush);
  2693. phys->ops.trigger_flush(phys);
  2694. spin_unlock_irqrestore(&sde_enc->enc_spinlock, lock_flags);
  2695. if (ctl->ops.get_pending_flush) {
  2696. struct sde_ctl_flush_cfg pending_flush = {0,};
  2697. ctl->ops.get_pending_flush(ctl, &pending_flush);
  2698. SDE_EVT32(DRMID(drm_enc), phys->intf_idx - INTF_0,
  2699. ctl->idx - CTL_0,
  2700. pending_flush.pending_flush_mask,
  2701. pend_ret_fence_cnt);
  2702. } else {
  2703. SDE_EVT32(DRMID(drm_enc), phys->intf_idx - INTF_0,
  2704. ctl->idx - CTL_0,
  2705. pend_ret_fence_cnt);
  2706. }
  2707. }
  2708. /**
  2709. * _sde_encoder_trigger_start - trigger start for a physical encoder
  2710. * phys: Pointer to physical encoder structure
  2711. */
  2712. static inline void _sde_encoder_trigger_start(struct sde_encoder_phys *phys)
  2713. {
  2714. struct sde_hw_ctl *ctl;
  2715. struct sde_encoder_virt *sde_enc;
  2716. if (!phys) {
  2717. SDE_ERROR("invalid argument(s)\n");
  2718. return;
  2719. }
  2720. if (!phys->hw_pp) {
  2721. SDE_ERROR("invalid pingpong hw\n");
  2722. return;
  2723. }
  2724. if (!phys->parent) {
  2725. SDE_ERROR("invalid parent\n");
  2726. return;
  2727. }
  2728. /* avoid ctrl start for encoder in clone mode */
  2729. if (phys->in_clone_mode)
  2730. return;
  2731. ctl = phys->hw_ctl;
  2732. sde_enc = to_sde_encoder_virt(phys->parent);
  2733. if (phys->split_role == ENC_ROLE_SKIP) {
  2734. SDE_DEBUG_ENC(sde_enc,
  2735. "skip start pp%d ctl%d\n",
  2736. phys->hw_pp->idx - PINGPONG_0,
  2737. ctl->idx - CTL_0);
  2738. return;
  2739. }
  2740. if (phys->ops.trigger_start && phys->enable_state != SDE_ENC_DISABLED)
  2741. phys->ops.trigger_start(phys);
  2742. }
  2743. void sde_encoder_helper_trigger_flush(struct sde_encoder_phys *phys_enc)
  2744. {
  2745. struct sde_hw_ctl *ctl;
  2746. if (!phys_enc) {
  2747. SDE_ERROR("invalid encoder\n");
  2748. return;
  2749. }
  2750. ctl = phys_enc->hw_ctl;
  2751. if (ctl && ctl->ops.trigger_flush)
  2752. ctl->ops.trigger_flush(ctl);
  2753. }
  2754. void sde_encoder_helper_trigger_start(struct sde_encoder_phys *phys_enc)
  2755. {
  2756. struct sde_hw_ctl *ctl;
  2757. if (!phys_enc) {
  2758. SDE_ERROR("invalid encoder\n");
  2759. return;
  2760. }
  2761. ctl = phys_enc->hw_ctl;
  2762. if (ctl && ctl->ops.trigger_start) {
  2763. ctl->ops.trigger_start(ctl);
  2764. SDE_EVT32(DRMID(phys_enc->parent), ctl->idx - CTL_0);
  2765. }
  2766. }
  2767. void sde_encoder_helper_hw_reset(struct sde_encoder_phys *phys_enc)
  2768. {
  2769. struct sde_encoder_virt *sde_enc;
  2770. struct sde_connector *sde_con;
  2771. void *sde_con_disp;
  2772. struct sde_hw_ctl *ctl;
  2773. int rc;
  2774. if (!phys_enc) {
  2775. SDE_ERROR("invalid encoder\n");
  2776. return;
  2777. }
  2778. sde_enc = to_sde_encoder_virt(phys_enc->parent);
  2779. ctl = phys_enc->hw_ctl;
  2780. if (!ctl || !ctl->ops.reset)
  2781. return;
  2782. SDE_DEBUG_ENC(sde_enc, "ctl %d reset\n", ctl->idx);
  2783. SDE_EVT32(DRMID(phys_enc->parent), ctl->idx);
  2784. if (phys_enc->ops.is_master && phys_enc->ops.is_master(phys_enc) &&
  2785. phys_enc->connector) {
  2786. sde_con = to_sde_connector(phys_enc->connector);
  2787. sde_con_disp = sde_connector_get_display(phys_enc->connector);
  2788. if (sde_con->ops.soft_reset) {
  2789. rc = sde_con->ops.soft_reset(sde_con_disp);
  2790. if (rc) {
  2791. SDE_ERROR_ENC(sde_enc,
  2792. "connector soft reset failure\n");
  2793. SDE_DBG_DUMP("all", "dbg_bus", "vbif_dbg_bus",
  2794. "panic");
  2795. }
  2796. }
  2797. }
  2798. phys_enc->enable_state = SDE_ENC_ENABLED;
  2799. }
  2800. /**
  2801. * _sde_encoder_kickoff_phys - handle physical encoder kickoff
  2802. * Iterate through the physical encoders and perform consolidated flush
  2803. * and/or control start triggering as needed. This is done in the virtual
  2804. * encoder rather than the individual physical ones in order to handle
  2805. * use cases that require visibility into multiple physical encoders at
  2806. * a time.
  2807. * sde_enc: Pointer to virtual encoder structure
  2808. */
  2809. static void _sde_encoder_kickoff_phys(struct sde_encoder_virt *sde_enc)
  2810. {
  2811. struct sde_hw_ctl *ctl;
  2812. uint32_t i;
  2813. struct sde_ctl_flush_cfg pending_flush = {0,};
  2814. u32 pending_kickoff_cnt;
  2815. struct msm_drm_private *priv = NULL;
  2816. struct sde_kms *sde_kms = NULL;
  2817. struct sde_crtc_misr_info crtc_misr_info = {false, 0};
  2818. bool is_regdma_blocking = false, is_vid_mode = false;
  2819. if (!sde_enc) {
  2820. SDE_ERROR("invalid encoder\n");
  2821. return;
  2822. }
  2823. if (sde_encoder_check_curr_mode(&sde_enc->base, MSM_DISPLAY_VIDEO_MODE))
  2824. is_vid_mode = true;
  2825. is_regdma_blocking = (is_vid_mode ||
  2826. _sde_encoder_is_autorefresh_enabled(sde_enc));
  2827. /* don't perform flush/start operations for slave encoders */
  2828. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2829. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2830. enum sde_rm_topology_name topology = SDE_RM_TOPOLOGY_NONE;
  2831. if (!phys || phys->enable_state == SDE_ENC_DISABLED)
  2832. continue;
  2833. ctl = phys->hw_ctl;
  2834. if (!ctl)
  2835. continue;
  2836. if (phys->connector)
  2837. topology = sde_connector_get_topology_name(
  2838. phys->connector);
  2839. if (!phys->ops.needs_single_flush ||
  2840. !phys->ops.needs_single_flush(phys)) {
  2841. if (ctl->ops.reg_dma_flush)
  2842. ctl->ops.reg_dma_flush(ctl, is_regdma_blocking);
  2843. _sde_encoder_trigger_flush(&sde_enc->base, phys, 0x0);
  2844. } else if (ctl->ops.get_pending_flush) {
  2845. ctl->ops.get_pending_flush(ctl, &pending_flush);
  2846. }
  2847. }
  2848. /* for split flush, combine pending flush masks and send to master */
  2849. if (pending_flush.pending_flush_mask && sde_enc->cur_master) {
  2850. ctl = sde_enc->cur_master->hw_ctl;
  2851. if (ctl->ops.reg_dma_flush)
  2852. ctl->ops.reg_dma_flush(ctl, is_regdma_blocking);
  2853. _sde_encoder_trigger_flush(&sde_enc->base, sde_enc->cur_master,
  2854. &pending_flush);
  2855. }
  2856. /* update pending_kickoff_cnt AFTER flush but before trigger start */
  2857. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2858. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  2859. if (!phys || phys->enable_state == SDE_ENC_DISABLED)
  2860. continue;
  2861. if (!phys->ops.needs_single_flush ||
  2862. !phys->ops.needs_single_flush(phys)) {
  2863. pending_kickoff_cnt =
  2864. sde_encoder_phys_inc_pending(phys);
  2865. SDE_EVT32(pending_kickoff_cnt, SDE_EVTLOG_FUNC_CASE1);
  2866. } else {
  2867. pending_kickoff_cnt =
  2868. sde_encoder_phys_inc_pending(phys);
  2869. SDE_EVT32(pending_kickoff_cnt,
  2870. pending_flush.pending_flush_mask,
  2871. SDE_EVTLOG_FUNC_CASE2);
  2872. }
  2873. }
  2874. if (sde_enc->misr_enable)
  2875. sde_encoder_misr_configure(&sde_enc->base, true,
  2876. sde_enc->misr_frame_count);
  2877. sde_crtc_get_misr_info(sde_enc->crtc, &crtc_misr_info);
  2878. if (crtc_misr_info.misr_enable)
  2879. sde_crtc_misr_setup(sde_enc->crtc, true,
  2880. crtc_misr_info.misr_frame_count);
  2881. _sde_encoder_trigger_start(sde_enc->cur_master);
  2882. if (sde_enc->elevated_ahb_vote) {
  2883. sde_kms = sde_encoder_get_kms(&sde_enc->base);
  2884. priv = sde_enc->base.dev->dev_private;
  2885. if (sde_kms != NULL) {
  2886. sde_power_scale_reg_bus(&priv->phandle,
  2887. VOTE_INDEX_LOW,
  2888. false);
  2889. }
  2890. sde_enc->elevated_ahb_vote = false;
  2891. }
  2892. }
  2893. static void _sde_encoder_ppsplit_swap_intf_for_right_only_update(
  2894. struct drm_encoder *drm_enc,
  2895. unsigned long *affected_displays,
  2896. int num_active_phys)
  2897. {
  2898. struct sde_encoder_virt *sde_enc;
  2899. struct sde_encoder_phys *master;
  2900. enum sde_rm_topology_name topology;
  2901. bool is_right_only;
  2902. if (!drm_enc || !affected_displays)
  2903. return;
  2904. sde_enc = to_sde_encoder_virt(drm_enc);
  2905. master = sde_enc->cur_master;
  2906. if (!master || !master->connector)
  2907. return;
  2908. topology = sde_connector_get_topology_name(master->connector);
  2909. if (topology != SDE_RM_TOPOLOGY_PPSPLIT)
  2910. return;
  2911. /*
  2912. * For pingpong split, the slave pingpong won't generate IRQs. For
  2913. * right-only updates, we can't swap pingpongs, or simply swap the
  2914. * master/slave assignment, we actually have to swap the interfaces
  2915. * so that the master physical encoder will use a pingpong/interface
  2916. * that generates irqs on which to wait.
  2917. */
  2918. is_right_only = !test_bit(0, affected_displays) &&
  2919. test_bit(1, affected_displays);
  2920. if (is_right_only && !sde_enc->intfs_swapped) {
  2921. /* right-only update swap interfaces */
  2922. swap(sde_enc->phys_encs[0]->intf_idx,
  2923. sde_enc->phys_encs[1]->intf_idx);
  2924. sde_enc->intfs_swapped = true;
  2925. } else if (!is_right_only && sde_enc->intfs_swapped) {
  2926. /* left-only or full update, swap back */
  2927. swap(sde_enc->phys_encs[0]->intf_idx,
  2928. sde_enc->phys_encs[1]->intf_idx);
  2929. sde_enc->intfs_swapped = false;
  2930. }
  2931. SDE_DEBUG_ENC(sde_enc,
  2932. "right_only %d swapped %d phys0->intf%d, phys1->intf%d\n",
  2933. is_right_only, sde_enc->intfs_swapped,
  2934. sde_enc->phys_encs[0]->intf_idx - INTF_0,
  2935. sde_enc->phys_encs[1]->intf_idx - INTF_0);
  2936. SDE_EVT32(DRMID(drm_enc), is_right_only, sde_enc->intfs_swapped,
  2937. sde_enc->phys_encs[0]->intf_idx - INTF_0,
  2938. sde_enc->phys_encs[1]->intf_idx - INTF_0,
  2939. *affected_displays);
  2940. /* ppsplit always uses master since ppslave invalid for irqs*/
  2941. if (num_active_phys == 1)
  2942. *affected_displays = BIT(0);
  2943. }
  2944. static void _sde_encoder_update_master(struct drm_encoder *drm_enc,
  2945. struct sde_encoder_kickoff_params *params)
  2946. {
  2947. struct sde_encoder_virt *sde_enc;
  2948. struct sde_encoder_phys *phys;
  2949. int i, num_active_phys;
  2950. bool master_assigned = false;
  2951. if (!drm_enc || !params)
  2952. return;
  2953. sde_enc = to_sde_encoder_virt(drm_enc);
  2954. if (sde_enc->num_phys_encs <= 1)
  2955. return;
  2956. /* count bits set */
  2957. num_active_phys = hweight_long(params->affected_displays);
  2958. SDE_DEBUG_ENC(sde_enc, "affected_displays 0x%lx num_active_phys %d\n",
  2959. params->affected_displays, num_active_phys);
  2960. SDE_EVT32_VERBOSE(DRMID(drm_enc), params->affected_displays,
  2961. num_active_phys);
  2962. /* for left/right only update, ppsplit master switches interface */
  2963. _sde_encoder_ppsplit_swap_intf_for_right_only_update(drm_enc,
  2964. &params->affected_displays, num_active_phys);
  2965. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  2966. enum sde_enc_split_role prv_role, new_role;
  2967. bool active = false;
  2968. phys = sde_enc->phys_encs[i];
  2969. if (!phys || !phys->ops.update_split_role || !phys->hw_pp)
  2970. continue;
  2971. active = test_bit(i, &params->affected_displays);
  2972. prv_role = phys->split_role;
  2973. if (active && num_active_phys == 1)
  2974. new_role = ENC_ROLE_SOLO;
  2975. else if (active && !master_assigned)
  2976. new_role = ENC_ROLE_MASTER;
  2977. else if (active)
  2978. new_role = ENC_ROLE_SLAVE;
  2979. else
  2980. new_role = ENC_ROLE_SKIP;
  2981. phys->ops.update_split_role(phys, new_role);
  2982. if (new_role == ENC_ROLE_SOLO || new_role == ENC_ROLE_MASTER) {
  2983. sde_enc->cur_master = phys;
  2984. master_assigned = true;
  2985. }
  2986. SDE_DEBUG_ENC(sde_enc, "pp %d role prv %d new %d active %d\n",
  2987. phys->hw_pp->idx - PINGPONG_0, prv_role,
  2988. phys->split_role, active);
  2989. SDE_EVT32(DRMID(drm_enc), params->affected_displays,
  2990. phys->hw_pp->idx - PINGPONG_0, prv_role,
  2991. phys->split_role, active, num_active_phys);
  2992. }
  2993. }
  2994. bool sde_encoder_check_curr_mode(struct drm_encoder *drm_enc, u32 mode)
  2995. {
  2996. struct sde_encoder_virt *sde_enc;
  2997. struct msm_display_info *disp_info;
  2998. if (!drm_enc) {
  2999. SDE_ERROR("invalid encoder\n");
  3000. return false;
  3001. }
  3002. sde_enc = to_sde_encoder_virt(drm_enc);
  3003. disp_info = &sde_enc->disp_info;
  3004. return (disp_info->curr_panel_mode == mode);
  3005. }
  3006. void sde_encoder_trigger_kickoff_pending(struct drm_encoder *drm_enc)
  3007. {
  3008. struct sde_encoder_virt *sde_enc;
  3009. struct sde_encoder_phys *phys;
  3010. unsigned int i;
  3011. struct sde_hw_ctl *ctl;
  3012. if (!drm_enc) {
  3013. SDE_ERROR("invalid encoder\n");
  3014. return;
  3015. }
  3016. sde_enc = to_sde_encoder_virt(drm_enc);
  3017. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3018. phys = sde_enc->phys_encs[i];
  3019. if (phys && phys->hw_ctl && (phys == sde_enc->cur_master) &&
  3020. sde_encoder_check_curr_mode(drm_enc,
  3021. MSM_DISPLAY_CMD_MODE)) {
  3022. ctl = phys->hw_ctl;
  3023. if (ctl->ops.trigger_pending)
  3024. /* update only for command mode primary ctl */
  3025. ctl->ops.trigger_pending(ctl);
  3026. }
  3027. }
  3028. sde_enc->idle_pc_restore = false;
  3029. }
  3030. static int _sde_encoder_wakeup_time(struct drm_encoder *drm_enc,
  3031. ktime_t *wakeup_time)
  3032. {
  3033. struct drm_display_mode *mode;
  3034. struct sde_encoder_virt *sde_enc;
  3035. u32 cur_line, lines_left;
  3036. u32 line_time, mdp_transfer_time_us;
  3037. u32 vtotal, time_to_vsync_us, threshold_time_us = 0;
  3038. ktime_t cur_time;
  3039. sde_enc = to_sde_encoder_virt(drm_enc);
  3040. if (!sde_enc || !sde_enc->cur_master) {
  3041. SDE_ERROR("invalid sde encoder/master\n");
  3042. return -EINVAL;
  3043. }
  3044. mode = &sde_enc->cur_master->cached_mode;
  3045. mdp_transfer_time_us = sde_enc->mode_info.mdp_transfer_time_us;
  3046. vtotal = mode->vtotal;
  3047. if (!mdp_transfer_time_us) {
  3048. /* mdp_transfer_time set to 0 for video mode */
  3049. line_time = (1000000 / sde_enc->mode_info.frame_rate) / vtotal;
  3050. } else {
  3051. line_time = mdp_transfer_time_us / vtotal;
  3052. threshold_time_us = ((1000000 / sde_enc->mode_info.frame_rate)
  3053. - mdp_transfer_time_us);
  3054. }
  3055. if (!sde_enc->cur_master->ops.get_line_count) {
  3056. SDE_DEBUG_ENC(sde_enc, "can't get master line count\n");
  3057. return -EINVAL;
  3058. }
  3059. cur_line = sde_enc->cur_master->ops.get_line_count(sde_enc->cur_master);
  3060. lines_left = (cur_line >= vtotal) ? vtotal : (vtotal - cur_line);
  3061. time_to_vsync_us = line_time * lines_left;
  3062. if (!time_to_vsync_us) {
  3063. SDE_ERROR("time to vsync should not be zero, vtotal=%d\n",
  3064. vtotal);
  3065. return -EINVAL;
  3066. }
  3067. cur_time = ktime_get();
  3068. *wakeup_time = ktime_add_us(cur_time, time_to_vsync_us);
  3069. if (threshold_time_us)
  3070. *wakeup_time = ktime_add_us(*wakeup_time, threshold_time_us);
  3071. SDE_DEBUG_ENC(sde_enc,
  3072. "cur_line=%u vtotal=%u time_to_vsync=%u, cur_time=%lld, wakeup_time=%lld\n",
  3073. cur_line, vtotal, time_to_vsync_us,
  3074. ktime_to_ms(cur_time),
  3075. ktime_to_ms(*wakeup_time));
  3076. return 0;
  3077. }
  3078. static void sde_encoder_vsync_event_handler(struct timer_list *t)
  3079. {
  3080. struct drm_encoder *drm_enc;
  3081. struct sde_encoder_virt *sde_enc =
  3082. from_timer(sde_enc, t, vsync_event_timer);
  3083. struct msm_drm_private *priv;
  3084. struct msm_drm_thread *event_thread;
  3085. if (!sde_enc || !sde_enc->crtc) {
  3086. SDE_ERROR("invalid encoder parameters %d\n", !sde_enc);
  3087. return;
  3088. }
  3089. drm_enc = &sde_enc->base;
  3090. if (!drm_enc || !drm_enc->dev || !drm_enc->dev->dev_private) {
  3091. SDE_ERROR("invalid encoder parameters\n");
  3092. return;
  3093. }
  3094. priv = drm_enc->dev->dev_private;
  3095. if (sde_enc->crtc->index >= ARRAY_SIZE(priv->event_thread)) {
  3096. SDE_ERROR("invalid crtc index:%u\n",
  3097. sde_enc->crtc->index);
  3098. return;
  3099. }
  3100. event_thread = &priv->event_thread[sde_enc->crtc->index];
  3101. if (!event_thread) {
  3102. SDE_ERROR("event_thread not found for crtc:%d\n",
  3103. sde_enc->crtc->index);
  3104. return;
  3105. }
  3106. kthread_queue_work(&event_thread->worker,
  3107. &sde_enc->vsync_event_work);
  3108. }
  3109. static void sde_encoder_esd_trigger_work_handler(struct kthread_work *work)
  3110. {
  3111. struct sde_encoder_virt *sde_enc = container_of(work,
  3112. struct sde_encoder_virt, esd_trigger_work);
  3113. if (!sde_enc) {
  3114. SDE_ERROR("invalid sde encoder\n");
  3115. return;
  3116. }
  3117. sde_encoder_resource_control(&sde_enc->base,
  3118. SDE_ENC_RC_EVENT_KICKOFF);
  3119. }
  3120. static void sde_encoder_input_event_work_handler(struct kthread_work *work)
  3121. {
  3122. struct sde_encoder_virt *sde_enc = container_of(work,
  3123. struct sde_encoder_virt, input_event_work);
  3124. if (!sde_enc) {
  3125. SDE_ERROR("invalid sde encoder\n");
  3126. return;
  3127. }
  3128. sde_encoder_resource_control(&sde_enc->base,
  3129. SDE_ENC_RC_EVENT_EARLY_WAKEUP);
  3130. }
  3131. static void sde_encoder_vsync_event_work_handler(struct kthread_work *work)
  3132. {
  3133. struct sde_encoder_virt *sde_enc = container_of(work,
  3134. struct sde_encoder_virt, vsync_event_work);
  3135. bool autorefresh_enabled = false;
  3136. int rc = 0;
  3137. ktime_t wakeup_time;
  3138. struct drm_encoder *drm_enc;
  3139. if (!sde_enc) {
  3140. SDE_ERROR("invalid sde encoder\n");
  3141. return;
  3142. }
  3143. drm_enc = &sde_enc->base;
  3144. rc = pm_runtime_get_sync(drm_enc->dev->dev);
  3145. if (rc < 0) {
  3146. SDE_ERROR_ENC(sde_enc, "sde enc power enabled failed:%d\n", rc);
  3147. return;
  3148. }
  3149. if (sde_enc->cur_master &&
  3150. sde_enc->cur_master->ops.is_autorefresh_enabled)
  3151. autorefresh_enabled =
  3152. sde_enc->cur_master->ops.is_autorefresh_enabled(
  3153. sde_enc->cur_master);
  3154. /* Update timer if autorefresh is enabled else return */
  3155. if (!autorefresh_enabled)
  3156. goto exit;
  3157. rc = _sde_encoder_wakeup_time(&sde_enc->base, &wakeup_time);
  3158. if (rc)
  3159. goto exit;
  3160. SDE_EVT32_VERBOSE(ktime_to_ms(wakeup_time));
  3161. mod_timer(&sde_enc->vsync_event_timer,
  3162. nsecs_to_jiffies(ktime_to_ns(wakeup_time)));
  3163. exit:
  3164. pm_runtime_put_sync(drm_enc->dev->dev);
  3165. }
  3166. int sde_encoder_poll_line_counts(struct drm_encoder *drm_enc)
  3167. {
  3168. static const uint64_t timeout_us = 50000;
  3169. static const uint64_t sleep_us = 20;
  3170. struct sde_encoder_virt *sde_enc;
  3171. ktime_t cur_ktime, exp_ktime;
  3172. uint32_t line_count, tmp, i;
  3173. if (!drm_enc) {
  3174. SDE_ERROR("invalid encoder\n");
  3175. return -EINVAL;
  3176. }
  3177. sde_enc = to_sde_encoder_virt(drm_enc);
  3178. if (!sde_enc->cur_master ||
  3179. !sde_enc->cur_master->ops.get_line_count) {
  3180. SDE_DEBUG_ENC(sde_enc, "can't get master line count\n");
  3181. SDE_EVT32(DRMID(drm_enc), SDE_EVTLOG_ERROR);
  3182. return -EINVAL;
  3183. }
  3184. exp_ktime = ktime_add_ms(ktime_get(), timeout_us / 1000);
  3185. line_count = sde_enc->cur_master->ops.get_line_count(
  3186. sde_enc->cur_master);
  3187. for (i = 0; i < (timeout_us * 2 / sleep_us); ++i) {
  3188. tmp = line_count;
  3189. line_count = sde_enc->cur_master->ops.get_line_count(
  3190. sde_enc->cur_master);
  3191. if (line_count < tmp) {
  3192. SDE_EVT32(DRMID(drm_enc), line_count);
  3193. return 0;
  3194. }
  3195. cur_ktime = ktime_get();
  3196. if (ktime_compare_safe(exp_ktime, cur_ktime) <= 0)
  3197. break;
  3198. usleep_range(sleep_us / 2, sleep_us);
  3199. }
  3200. SDE_EVT32(DRMID(drm_enc), line_count, SDE_EVTLOG_ERROR);
  3201. return -ETIMEDOUT;
  3202. }
  3203. static int _helper_flush_qsync(struct sde_encoder_phys *phys_enc)
  3204. {
  3205. struct drm_encoder *drm_enc;
  3206. struct sde_rm_hw_iter rm_iter;
  3207. bool lm_valid = false;
  3208. bool intf_valid = false;
  3209. if (!phys_enc || !phys_enc->parent) {
  3210. SDE_ERROR("invalid encoder\n");
  3211. return -EINVAL;
  3212. }
  3213. drm_enc = phys_enc->parent;
  3214. /* Flush the interfaces for AVR update or Qsync with INTF TE */
  3215. if (phys_enc->intf_mode == INTF_MODE_VIDEO ||
  3216. (phys_enc->intf_mode == INTF_MODE_CMD &&
  3217. phys_enc->has_intf_te)) {
  3218. sde_rm_init_hw_iter(&rm_iter, drm_enc->base.id,
  3219. SDE_HW_BLK_INTF);
  3220. while (sde_rm_get_hw(&phys_enc->sde_kms->rm, &rm_iter)) {
  3221. struct sde_hw_intf *hw_intf =
  3222. (struct sde_hw_intf *)rm_iter.hw;
  3223. if (!hw_intf)
  3224. continue;
  3225. if (phys_enc->hw_ctl->ops.update_bitmask)
  3226. phys_enc->hw_ctl->ops.update_bitmask(
  3227. phys_enc->hw_ctl,
  3228. SDE_HW_FLUSH_INTF,
  3229. hw_intf->idx, 1);
  3230. intf_valid = true;
  3231. }
  3232. if (!intf_valid) {
  3233. SDE_ERROR_ENC(to_sde_encoder_virt(drm_enc),
  3234. "intf not found to flush\n");
  3235. return -EFAULT;
  3236. }
  3237. } else {
  3238. sde_rm_init_hw_iter(&rm_iter, drm_enc->base.id, SDE_HW_BLK_LM);
  3239. while (sde_rm_get_hw(&phys_enc->sde_kms->rm, &rm_iter)) {
  3240. struct sde_hw_mixer *hw_lm =
  3241. (struct sde_hw_mixer *)rm_iter.hw;
  3242. if (!hw_lm)
  3243. continue;
  3244. /* update LM flush for HW without INTF TE */
  3245. if (phys_enc->hw_ctl->ops.update_bitmask_mixer)
  3246. phys_enc->hw_ctl->ops.update_bitmask_mixer(
  3247. phys_enc->hw_ctl,
  3248. hw_lm->idx, 1);
  3249. lm_valid = true;
  3250. }
  3251. if (!lm_valid) {
  3252. SDE_ERROR_ENC(to_sde_encoder_virt(drm_enc),
  3253. "lm not found to flush\n");
  3254. return -EFAULT;
  3255. }
  3256. }
  3257. return 0;
  3258. }
  3259. static void _sde_encoder_helper_hdr_plus_mempool_update(
  3260. struct sde_encoder_virt *sde_enc)
  3261. {
  3262. struct sde_connector_dyn_hdr_metadata *dhdr_meta = NULL;
  3263. struct sde_hw_mdp *mdptop = NULL;
  3264. sde_enc->dynamic_hdr_updated = false;
  3265. if (sde_enc->cur_master) {
  3266. mdptop = sde_enc->cur_master->hw_mdptop;
  3267. dhdr_meta = sde_connector_get_dyn_hdr_meta(
  3268. sde_enc->cur_master->connector);
  3269. }
  3270. if (!mdptop || !dhdr_meta || !dhdr_meta->dynamic_hdr_update)
  3271. return;
  3272. if (mdptop->ops.set_hdr_plus_metadata) {
  3273. sde_enc->dynamic_hdr_updated = true;
  3274. mdptop->ops.set_hdr_plus_metadata(
  3275. mdptop, dhdr_meta->dynamic_hdr_payload,
  3276. dhdr_meta->dynamic_hdr_payload_size,
  3277. sde_enc->cur_master->intf_idx == INTF_0 ?
  3278. 0 : 1);
  3279. }
  3280. }
  3281. void sde_encoder_needs_hw_reset(struct drm_encoder *drm_enc)
  3282. {
  3283. struct sde_encoder_virt *sde_enc = to_sde_encoder_virt(drm_enc);
  3284. struct sde_encoder_phys *phys;
  3285. int i;
  3286. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3287. phys = sde_enc->phys_encs[i];
  3288. if (phys && phys->ops.hw_reset)
  3289. phys->ops.hw_reset(phys);
  3290. }
  3291. }
  3292. int sde_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc,
  3293. struct sde_encoder_kickoff_params *params)
  3294. {
  3295. struct sde_encoder_virt *sde_enc;
  3296. struct sde_encoder_phys *phys;
  3297. struct sde_kms *sde_kms = NULL;
  3298. struct sde_crtc *sde_crtc;
  3299. bool needs_hw_reset = false, is_cmd_mode;
  3300. int i, rc, ret = 0;
  3301. struct msm_display_info *disp_info;
  3302. if (!drm_enc || !params || !drm_enc->dev ||
  3303. !drm_enc->dev->dev_private) {
  3304. SDE_ERROR("invalid args\n");
  3305. return -EINVAL;
  3306. }
  3307. sde_enc = to_sde_encoder_virt(drm_enc);
  3308. sde_kms = sde_encoder_get_kms(drm_enc);
  3309. if (!sde_kms)
  3310. return -EINVAL;
  3311. disp_info = &sde_enc->disp_info;
  3312. sde_crtc = to_sde_crtc(sde_enc->crtc);
  3313. SDE_DEBUG_ENC(sde_enc, "\n");
  3314. SDE_EVT32(DRMID(drm_enc));
  3315. is_cmd_mode = sde_encoder_check_curr_mode(drm_enc,
  3316. MSM_DISPLAY_CMD_MODE);
  3317. if (sde_enc->cur_master && sde_enc->cur_master->connector
  3318. && is_cmd_mode)
  3319. sde_enc->frame_trigger_mode = sde_connector_get_property(
  3320. sde_enc->cur_master->connector->state,
  3321. CONNECTOR_PROP_CMD_FRAME_TRIGGER_MODE);
  3322. _sde_encoder_helper_hdr_plus_mempool_update(sde_enc);
  3323. /* prepare for next kickoff, may include waiting on previous kickoff */
  3324. SDE_ATRACE_BEGIN("sde_encoder_prepare_for_kickoff");
  3325. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3326. phys = sde_enc->phys_encs[i];
  3327. params->frame_trigger_mode = sde_enc->frame_trigger_mode;
  3328. params->recovery_events_enabled =
  3329. sde_enc->recovery_events_enabled;
  3330. if (phys) {
  3331. if (phys->ops.prepare_for_kickoff) {
  3332. rc = phys->ops.prepare_for_kickoff(
  3333. phys, params);
  3334. if (rc)
  3335. ret = rc;
  3336. }
  3337. if (phys->enable_state == SDE_ENC_ERR_NEEDS_HW_RESET)
  3338. needs_hw_reset = true;
  3339. _sde_encoder_setup_dither(phys);
  3340. if (sde_enc->cur_master &&
  3341. sde_connector_is_qsync_updated(
  3342. sde_enc->cur_master->connector)) {
  3343. _helper_flush_qsync(phys);
  3344. }
  3345. }
  3346. }
  3347. rc = sde_encoder_resource_control(drm_enc, SDE_ENC_RC_EVENT_KICKOFF);
  3348. if (rc) {
  3349. SDE_ERROR_ENC(sde_enc, "resource kickoff failed rc %d\n", rc);
  3350. ret = rc;
  3351. goto end;
  3352. }
  3353. /* if any phys needs reset, reset all phys, in-order */
  3354. if (needs_hw_reset)
  3355. sde_encoder_needs_hw_reset(drm_enc);
  3356. _sde_encoder_update_master(drm_enc, params);
  3357. _sde_encoder_update_roi(drm_enc);
  3358. if (sde_enc->cur_master && sde_enc->cur_master->connector) {
  3359. rc = sde_connector_pre_kickoff(sde_enc->cur_master->connector);
  3360. if (rc) {
  3361. SDE_ERROR_ENC(sde_enc, "kickoff conn%d failed rc %d\n",
  3362. sde_enc->cur_master->connector->base.id,
  3363. rc);
  3364. ret = rc;
  3365. }
  3366. }
  3367. if (sde_enc->cur_master &&
  3368. ((is_cmd_mode && sde_enc->cur_master->cont_splash_enabled) ||
  3369. !sde_enc->cur_master->cont_splash_enabled)) {
  3370. rc = sde_encoder_dce_setup(sde_enc, params);
  3371. if (rc) {
  3372. SDE_ERROR_ENC(sde_enc, "failed to setup DSC: %d\n", rc);
  3373. ret = rc;
  3374. }
  3375. }
  3376. sde_encoder_dce_flush(sde_enc);
  3377. if (sde_enc->cur_master && !sde_enc->cur_master->cont_splash_enabled)
  3378. sde_configure_qdss(sde_enc, sde_enc->cur_master->hw_qdss,
  3379. sde_enc->cur_master, sde_kms->qdss_enabled);
  3380. end:
  3381. SDE_ATRACE_END("sde_encoder_prepare_for_kickoff");
  3382. return ret;
  3383. }
  3384. /**
  3385. * _sde_encoder_reset_ctl_hw - reset h/w configuration for all ctl's associated
  3386. * with the specified encoder, and unstage all pipes from it
  3387. * @encoder: encoder pointer
  3388. * Returns: 0 on success
  3389. */
  3390. static int _sde_encoder_reset_ctl_hw(struct drm_encoder *drm_enc)
  3391. {
  3392. struct sde_encoder_virt *sde_enc;
  3393. struct sde_encoder_phys *phys;
  3394. unsigned int i;
  3395. int rc = 0;
  3396. if (!drm_enc) {
  3397. SDE_ERROR("invalid encoder\n");
  3398. return -EINVAL;
  3399. }
  3400. sde_enc = to_sde_encoder_virt(drm_enc);
  3401. SDE_ATRACE_BEGIN("encoder_release_lm");
  3402. SDE_DEBUG_ENC(sde_enc, "\n");
  3403. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3404. phys = sde_enc->phys_encs[i];
  3405. if (!phys)
  3406. continue;
  3407. SDE_EVT32(DRMID(drm_enc), phys->intf_idx - INTF_0);
  3408. rc = sde_encoder_helper_reset_mixers(phys, NULL);
  3409. if (rc)
  3410. SDE_EVT32(DRMID(drm_enc), rc, SDE_EVTLOG_ERROR);
  3411. }
  3412. SDE_ATRACE_END("encoder_release_lm");
  3413. return rc;
  3414. }
  3415. void sde_encoder_kickoff(struct drm_encoder *drm_enc, bool is_error)
  3416. {
  3417. struct sde_encoder_virt *sde_enc;
  3418. struct sde_encoder_phys *phys;
  3419. ktime_t wakeup_time;
  3420. unsigned int i;
  3421. if (!drm_enc) {
  3422. SDE_ERROR("invalid encoder\n");
  3423. return;
  3424. }
  3425. SDE_ATRACE_BEGIN("encoder_kickoff");
  3426. sde_enc = to_sde_encoder_virt(drm_enc);
  3427. SDE_DEBUG_ENC(sde_enc, "\n");
  3428. /* create a 'no pipes' commit to release buffers on errors */
  3429. if (is_error)
  3430. _sde_encoder_reset_ctl_hw(drm_enc);
  3431. /* All phys encs are ready to go, trigger the kickoff */
  3432. _sde_encoder_kickoff_phys(sde_enc);
  3433. /* allow phys encs to handle any post-kickoff business */
  3434. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3435. phys = sde_enc->phys_encs[i];
  3436. if (phys && phys->ops.handle_post_kickoff)
  3437. phys->ops.handle_post_kickoff(phys);
  3438. }
  3439. if (sde_enc->disp_info.intf_type == DRM_MODE_CONNECTOR_DSI &&
  3440. !_sde_encoder_wakeup_time(drm_enc, &wakeup_time)) {
  3441. SDE_EVT32_VERBOSE(ktime_to_ms(wakeup_time));
  3442. mod_timer(&sde_enc->vsync_event_timer,
  3443. nsecs_to_jiffies(ktime_to_ns(wakeup_time)));
  3444. }
  3445. SDE_ATRACE_END("encoder_kickoff");
  3446. }
  3447. void sde_encoder_helper_get_pp_line_count(struct drm_encoder *drm_enc,
  3448. struct sde_hw_pp_vsync_info *info)
  3449. {
  3450. struct sde_encoder_virt *sde_enc;
  3451. struct sde_encoder_phys *phys;
  3452. int i, ret;
  3453. if (!drm_enc || !info)
  3454. return;
  3455. sde_enc = to_sde_encoder_virt(drm_enc);
  3456. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3457. phys = sde_enc->phys_encs[i];
  3458. if (phys && phys->hw_intf && phys->hw_pp
  3459. && phys->hw_intf->ops.get_vsync_info) {
  3460. ret = phys->hw_intf->ops.get_vsync_info(
  3461. phys->hw_intf, &info[i]);
  3462. if (!ret) {
  3463. info[i].pp_idx = phys->hw_pp->idx - PINGPONG_0;
  3464. info[i].intf_idx = phys->hw_intf->idx - INTF_0;
  3465. }
  3466. }
  3467. }
  3468. }
  3469. int sde_encoder_helper_reset_mixers(struct sde_encoder_phys *phys_enc,
  3470. struct drm_framebuffer *fb)
  3471. {
  3472. struct drm_encoder *drm_enc;
  3473. struct sde_hw_mixer_cfg mixer;
  3474. struct sde_rm_hw_iter lm_iter;
  3475. bool lm_valid = false;
  3476. if (!phys_enc || !phys_enc->parent) {
  3477. SDE_ERROR("invalid encoder\n");
  3478. return -EINVAL;
  3479. }
  3480. drm_enc = phys_enc->parent;
  3481. memset(&mixer, 0, sizeof(mixer));
  3482. /* reset associated CTL/LMs */
  3483. if (phys_enc->hw_ctl->ops.clear_all_blendstages)
  3484. phys_enc->hw_ctl->ops.clear_all_blendstages(phys_enc->hw_ctl);
  3485. sde_rm_init_hw_iter(&lm_iter, drm_enc->base.id, SDE_HW_BLK_LM);
  3486. while (sde_rm_get_hw(&phys_enc->sde_kms->rm, &lm_iter)) {
  3487. struct sde_hw_mixer *hw_lm = (struct sde_hw_mixer *)lm_iter.hw;
  3488. if (!hw_lm)
  3489. continue;
  3490. /* need to flush LM to remove it */
  3491. if (phys_enc->hw_ctl->ops.update_bitmask_mixer)
  3492. phys_enc->hw_ctl->ops.update_bitmask_mixer(
  3493. phys_enc->hw_ctl,
  3494. hw_lm->idx, 1);
  3495. if (fb) {
  3496. /* assume a single LM if targeting a frame buffer */
  3497. if (lm_valid)
  3498. continue;
  3499. mixer.out_height = fb->height;
  3500. mixer.out_width = fb->width;
  3501. if (hw_lm->ops.setup_mixer_out)
  3502. hw_lm->ops.setup_mixer_out(hw_lm, &mixer);
  3503. }
  3504. lm_valid = true;
  3505. /* only enable border color on LM */
  3506. if (phys_enc->hw_ctl->ops.setup_blendstage)
  3507. phys_enc->hw_ctl->ops.setup_blendstage(
  3508. phys_enc->hw_ctl, hw_lm->idx, NULL, NULL);
  3509. }
  3510. if (!lm_valid) {
  3511. SDE_ERROR_ENC(to_sde_encoder_virt(drm_enc), "lm not found\n");
  3512. return -EFAULT;
  3513. }
  3514. return 0;
  3515. }
  3516. int sde_encoder_prepare_commit(struct drm_encoder *drm_enc)
  3517. {
  3518. struct sde_encoder_virt *sde_enc;
  3519. struct sde_encoder_phys *phys;
  3520. int i, rc = 0, ret = 0;
  3521. struct sde_hw_ctl *ctl;
  3522. if (!drm_enc) {
  3523. SDE_ERROR("invalid encoder\n");
  3524. return -EINVAL;
  3525. }
  3526. sde_enc = to_sde_encoder_virt(drm_enc);
  3527. /* update the qsync parameters for the current frame */
  3528. if (sde_enc->cur_master)
  3529. sde_connector_set_qsync_params(
  3530. sde_enc->cur_master->connector);
  3531. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3532. phys = sde_enc->phys_encs[i];
  3533. if (phys && phys->ops.prepare_commit)
  3534. phys->ops.prepare_commit(phys);
  3535. if (phys && phys->enable_state == SDE_ENC_ERR_NEEDS_HW_RESET)
  3536. ret = -ETIMEDOUT;
  3537. if (phys && phys->hw_ctl) {
  3538. ctl = phys->hw_ctl;
  3539. /*
  3540. * avoid clearing the pending flush during the first
  3541. * frame update after idle power collpase as the
  3542. * restore path would have updated the pending flush
  3543. */
  3544. if (!sde_enc->idle_pc_restore &&
  3545. ctl->ops.clear_pending_flush)
  3546. ctl->ops.clear_pending_flush(ctl);
  3547. }
  3548. }
  3549. if (sde_enc->cur_master && sde_enc->cur_master->connector) {
  3550. rc = sde_connector_prepare_commit(
  3551. sde_enc->cur_master->connector);
  3552. if (rc)
  3553. SDE_ERROR_ENC(sde_enc,
  3554. "prepare commit failed conn %d rc %d\n",
  3555. sde_enc->cur_master->connector->base.id,
  3556. rc);
  3557. }
  3558. return ret;
  3559. }
  3560. void sde_encoder_helper_setup_misr(struct sde_encoder_phys *phys_enc,
  3561. bool enable, u32 frame_count)
  3562. {
  3563. if (!phys_enc)
  3564. return;
  3565. if (phys_enc->hw_intf && phys_enc->hw_intf->ops.setup_misr)
  3566. phys_enc->hw_intf->ops.setup_misr(phys_enc->hw_intf,
  3567. enable, frame_count);
  3568. }
  3569. int sde_encoder_helper_collect_misr(struct sde_encoder_phys *phys_enc,
  3570. bool nonblock, u32 *misr_value)
  3571. {
  3572. if (!phys_enc)
  3573. return -EINVAL;
  3574. return phys_enc->hw_intf && phys_enc->hw_intf->ops.collect_misr ?
  3575. phys_enc->hw_intf->ops.collect_misr(phys_enc->hw_intf,
  3576. nonblock, misr_value) : -ENOTSUPP;
  3577. }
  3578. #ifdef CONFIG_DEBUG_FS
  3579. static int _sde_encoder_status_show(struct seq_file *s, void *data)
  3580. {
  3581. struct sde_encoder_virt *sde_enc;
  3582. int i;
  3583. if (!s || !s->private)
  3584. return -EINVAL;
  3585. sde_enc = s->private;
  3586. mutex_lock(&sde_enc->enc_lock);
  3587. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3588. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  3589. if (!phys)
  3590. continue;
  3591. seq_printf(s, "intf:%d vsync:%8d underrun:%8d ",
  3592. phys->intf_idx - INTF_0,
  3593. atomic_read(&phys->vsync_cnt),
  3594. atomic_read(&phys->underrun_cnt));
  3595. switch (phys->intf_mode) {
  3596. case INTF_MODE_VIDEO:
  3597. seq_puts(s, "mode: video\n");
  3598. break;
  3599. case INTF_MODE_CMD:
  3600. seq_puts(s, "mode: command\n");
  3601. break;
  3602. case INTF_MODE_WB_BLOCK:
  3603. seq_puts(s, "mode: wb block\n");
  3604. break;
  3605. case INTF_MODE_WB_LINE:
  3606. seq_puts(s, "mode: wb line\n");
  3607. break;
  3608. default:
  3609. seq_puts(s, "mode: ???\n");
  3610. break;
  3611. }
  3612. }
  3613. mutex_unlock(&sde_enc->enc_lock);
  3614. return 0;
  3615. }
  3616. static int _sde_encoder_debugfs_status_open(struct inode *inode,
  3617. struct file *file)
  3618. {
  3619. return single_open(file, _sde_encoder_status_show, inode->i_private);
  3620. }
  3621. static ssize_t _sde_encoder_misr_setup(struct file *file,
  3622. const char __user *user_buf, size_t count, loff_t *ppos)
  3623. {
  3624. struct sde_encoder_virt *sde_enc;
  3625. int rc;
  3626. char buf[MISR_BUFF_SIZE + 1];
  3627. size_t buff_copy;
  3628. u32 frame_count, enable;
  3629. struct sde_kms *sde_kms = NULL;
  3630. struct drm_encoder *drm_enc;
  3631. if (!file || !file->private_data)
  3632. return -EINVAL;
  3633. sde_enc = file->private_data;
  3634. if (!sde_enc)
  3635. return -EINVAL;
  3636. sde_kms = sde_encoder_get_kms(&sde_enc->base);
  3637. if (!sde_kms)
  3638. return -EINVAL;
  3639. drm_enc = &sde_enc->base;
  3640. if (sde_kms_is_secure_session_inprogress(sde_kms)) {
  3641. SDE_DEBUG_ENC(sde_enc, "misr enable/disable not allowed\n");
  3642. return -ENOTSUPP;
  3643. }
  3644. buff_copy = min_t(size_t, count, MISR_BUFF_SIZE);
  3645. if (copy_from_user(buf, user_buf, buff_copy))
  3646. return -EINVAL;
  3647. buf[buff_copy] = 0; /* end of string */
  3648. if (sscanf(buf, "%u %u", &enable, &frame_count) != 2)
  3649. return -EINVAL;
  3650. rc = pm_runtime_get_sync(drm_enc->dev->dev);
  3651. if (rc < 0)
  3652. return rc;
  3653. sde_enc->misr_enable = enable;
  3654. sde_enc->misr_frame_count = frame_count;
  3655. sde_encoder_misr_configure(&sde_enc->base, enable, frame_count);
  3656. pm_runtime_put_sync(drm_enc->dev->dev);
  3657. return count;
  3658. }
  3659. static ssize_t _sde_encoder_misr_read(struct file *file,
  3660. char __user *user_buff, size_t count, loff_t *ppos)
  3661. {
  3662. struct sde_encoder_virt *sde_enc;
  3663. struct sde_kms *sde_kms = NULL;
  3664. struct drm_encoder *drm_enc;
  3665. int i = 0, len = 0;
  3666. char buf[MISR_BUFF_SIZE + 1] = {'\0'};
  3667. int rc;
  3668. if (*ppos)
  3669. return 0;
  3670. if (!file || !file->private_data)
  3671. return -EINVAL;
  3672. sde_enc = file->private_data;
  3673. sde_kms = sde_encoder_get_kms(&sde_enc->base);
  3674. if (!sde_kms)
  3675. return -EINVAL;
  3676. if (sde_kms_is_secure_session_inprogress(sde_kms)) {
  3677. SDE_DEBUG_ENC(sde_enc, "misr read not allowed\n");
  3678. return -ENOTSUPP;
  3679. }
  3680. drm_enc = &sde_enc->base;
  3681. rc = pm_runtime_get_sync(drm_enc->dev->dev);
  3682. if (rc < 0)
  3683. return rc;
  3684. if (!sde_enc->misr_enable) {
  3685. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  3686. "disabled\n");
  3687. goto buff_check;
  3688. }
  3689. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3690. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  3691. u32 misr_value = 0;
  3692. if (!phys || !phys->ops.collect_misr) {
  3693. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  3694. "invalid\n");
  3695. SDE_ERROR_ENC(sde_enc, "invalid misr ops\n");
  3696. continue;
  3697. }
  3698. rc = phys->ops.collect_misr(phys, false, &misr_value);
  3699. if (rc) {
  3700. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  3701. "invalid\n");
  3702. SDE_ERROR_ENC(sde_enc, "failed to collect misr %d\n",
  3703. rc);
  3704. continue;
  3705. } else {
  3706. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  3707. "Intf idx:%d\n",
  3708. phys->intf_idx - INTF_0);
  3709. len += scnprintf(buf + len, MISR_BUFF_SIZE - len,
  3710. "0x%x\n", misr_value);
  3711. }
  3712. }
  3713. buff_check:
  3714. if (count <= len) {
  3715. len = 0;
  3716. goto end;
  3717. }
  3718. if (copy_to_user(user_buff, buf, len)) {
  3719. len = -EFAULT;
  3720. goto end;
  3721. }
  3722. *ppos += len; /* increase offset */
  3723. end:
  3724. pm_runtime_put_sync(drm_enc->dev->dev);
  3725. return len;
  3726. }
  3727. static int _sde_encoder_init_debugfs(struct drm_encoder *drm_enc)
  3728. {
  3729. struct sde_encoder_virt *sde_enc;
  3730. struct sde_kms *sde_kms;
  3731. int i;
  3732. static const struct file_operations debugfs_status_fops = {
  3733. .open = _sde_encoder_debugfs_status_open,
  3734. .read = seq_read,
  3735. .llseek = seq_lseek,
  3736. .release = single_release,
  3737. };
  3738. static const struct file_operations debugfs_misr_fops = {
  3739. .open = simple_open,
  3740. .read = _sde_encoder_misr_read,
  3741. .write = _sde_encoder_misr_setup,
  3742. };
  3743. char name[SDE_NAME_SIZE];
  3744. if (!drm_enc) {
  3745. SDE_ERROR("invalid encoder\n");
  3746. return -EINVAL;
  3747. }
  3748. sde_enc = to_sde_encoder_virt(drm_enc);
  3749. sde_kms = sde_encoder_get_kms(drm_enc);
  3750. if (!sde_kms) {
  3751. SDE_ERROR("invalid sde_kms\n");
  3752. return -EINVAL;
  3753. }
  3754. snprintf(name, SDE_NAME_SIZE, "encoder%u", drm_enc->base.id);
  3755. /* create overall sub-directory for the encoder */
  3756. sde_enc->debugfs_root = debugfs_create_dir(name,
  3757. drm_enc->dev->primary->debugfs_root);
  3758. if (!sde_enc->debugfs_root)
  3759. return -ENOMEM;
  3760. /* don't error check these */
  3761. debugfs_create_file("status", 0400,
  3762. sde_enc->debugfs_root, sde_enc, &debugfs_status_fops);
  3763. debugfs_create_file("misr_data", 0600,
  3764. sde_enc->debugfs_root, sde_enc, &debugfs_misr_fops);
  3765. debugfs_create_bool("idle_power_collapse", 0600, sde_enc->debugfs_root,
  3766. &sde_enc->idle_pc_enabled);
  3767. debugfs_create_u32("frame_trigger_mode", 0400, sde_enc->debugfs_root,
  3768. &sde_enc->frame_trigger_mode);
  3769. for (i = 0; i < sde_enc->num_phys_encs; i++)
  3770. if (sde_enc->phys_encs[i] &&
  3771. sde_enc->phys_encs[i]->ops.late_register)
  3772. sde_enc->phys_encs[i]->ops.late_register(
  3773. sde_enc->phys_encs[i],
  3774. sde_enc->debugfs_root);
  3775. return 0;
  3776. }
  3777. static void _sde_encoder_destroy_debugfs(struct drm_encoder *drm_enc)
  3778. {
  3779. struct sde_encoder_virt *sde_enc;
  3780. if (!drm_enc)
  3781. return;
  3782. sde_enc = to_sde_encoder_virt(drm_enc);
  3783. debugfs_remove_recursive(sde_enc->debugfs_root);
  3784. }
  3785. #else
  3786. static int _sde_encoder_init_debugfs(struct drm_encoder *drm_enc)
  3787. {
  3788. return 0;
  3789. }
  3790. static void _sde_encoder_destroy_debugfs(struct drm_encoder *drm_enc)
  3791. {
  3792. }
  3793. #endif
  3794. static int sde_encoder_late_register(struct drm_encoder *encoder)
  3795. {
  3796. return _sde_encoder_init_debugfs(encoder);
  3797. }
  3798. static void sde_encoder_early_unregister(struct drm_encoder *encoder)
  3799. {
  3800. _sde_encoder_destroy_debugfs(encoder);
  3801. }
  3802. static int sde_encoder_virt_add_phys_encs(
  3803. struct msm_display_info *disp_info,
  3804. struct sde_encoder_virt *sde_enc,
  3805. struct sde_enc_phys_init_params *params)
  3806. {
  3807. struct sde_encoder_phys *enc = NULL;
  3808. u32 display_caps = disp_info->capabilities;
  3809. SDE_DEBUG_ENC(sde_enc, "\n");
  3810. /*
  3811. * We may create up to NUM_PHYS_ENCODER_TYPES physical encoder types
  3812. * in this function, check up-front.
  3813. */
  3814. if (sde_enc->num_phys_encs + NUM_PHYS_ENCODER_TYPES >=
  3815. ARRAY_SIZE(sde_enc->phys_encs)) {
  3816. SDE_ERROR_ENC(sde_enc, "too many physical encoders %d\n",
  3817. sde_enc->num_phys_encs);
  3818. return -EINVAL;
  3819. }
  3820. if (display_caps & MSM_DISPLAY_CAP_VID_MODE) {
  3821. enc = sde_encoder_phys_vid_init(params);
  3822. if (IS_ERR_OR_NULL(enc)) {
  3823. SDE_ERROR_ENC(sde_enc, "failed to init vid enc: %ld\n",
  3824. PTR_ERR(enc));
  3825. return !enc ? -EINVAL : PTR_ERR(enc);
  3826. }
  3827. sde_enc->phys_vid_encs[sde_enc->num_phys_encs] = enc;
  3828. }
  3829. if (display_caps & MSM_DISPLAY_CAP_CMD_MODE) {
  3830. enc = sde_encoder_phys_cmd_init(params);
  3831. if (IS_ERR_OR_NULL(enc)) {
  3832. SDE_ERROR_ENC(sde_enc, "failed to init cmd enc: %ld\n",
  3833. PTR_ERR(enc));
  3834. return !enc ? -EINVAL : PTR_ERR(enc);
  3835. }
  3836. sde_enc->phys_cmd_encs[sde_enc->num_phys_encs] = enc;
  3837. }
  3838. if (disp_info->curr_panel_mode == MSM_DISPLAY_VIDEO_MODE)
  3839. sde_enc->phys_encs[sde_enc->num_phys_encs] =
  3840. sde_enc->phys_vid_encs[sde_enc->num_phys_encs];
  3841. else
  3842. sde_enc->phys_encs[sde_enc->num_phys_encs] =
  3843. sde_enc->phys_cmd_encs[sde_enc->num_phys_encs];
  3844. ++sde_enc->num_phys_encs;
  3845. return 0;
  3846. }
  3847. static int sde_encoder_virt_add_phys_enc_wb(struct sde_encoder_virt *sde_enc,
  3848. struct sde_enc_phys_init_params *params)
  3849. {
  3850. struct sde_encoder_phys *enc = NULL;
  3851. if (!sde_enc) {
  3852. SDE_ERROR("invalid encoder\n");
  3853. return -EINVAL;
  3854. }
  3855. SDE_DEBUG_ENC(sde_enc, "\n");
  3856. if (sde_enc->num_phys_encs + 1 >= ARRAY_SIZE(sde_enc->phys_encs)) {
  3857. SDE_ERROR_ENC(sde_enc, "too many physical encoders %d\n",
  3858. sde_enc->num_phys_encs);
  3859. return -EINVAL;
  3860. }
  3861. enc = sde_encoder_phys_wb_init(params);
  3862. if (IS_ERR_OR_NULL(enc)) {
  3863. SDE_ERROR_ENC(sde_enc, "failed to init wb enc: %ld\n",
  3864. PTR_ERR(enc));
  3865. return !enc ? -EINVAL : PTR_ERR(enc);
  3866. }
  3867. sde_enc->phys_encs[sde_enc->num_phys_encs] = enc;
  3868. ++sde_enc->num_phys_encs;
  3869. return 0;
  3870. }
  3871. static int sde_encoder_setup_display(struct sde_encoder_virt *sde_enc,
  3872. struct sde_kms *sde_kms,
  3873. struct msm_display_info *disp_info,
  3874. int *drm_enc_mode)
  3875. {
  3876. int ret = 0;
  3877. int i = 0;
  3878. enum sde_intf_type intf_type;
  3879. struct sde_encoder_virt_ops parent_ops = {
  3880. sde_encoder_vblank_callback,
  3881. sde_encoder_underrun_callback,
  3882. sde_encoder_frame_done_callback,
  3883. sde_encoder_get_qsync_fps_callback,
  3884. };
  3885. struct sde_enc_phys_init_params phys_params;
  3886. if (!sde_enc || !sde_kms) {
  3887. SDE_ERROR("invalid arg(s), enc %d kms %d\n",
  3888. !sde_enc, !sde_kms);
  3889. return -EINVAL;
  3890. }
  3891. memset(&phys_params, 0, sizeof(phys_params));
  3892. phys_params.sde_kms = sde_kms;
  3893. phys_params.parent = &sde_enc->base;
  3894. phys_params.parent_ops = parent_ops;
  3895. phys_params.enc_spinlock = &sde_enc->enc_spinlock;
  3896. phys_params.vblank_ctl_lock = &sde_enc->vblank_ctl_lock;
  3897. SDE_DEBUG("\n");
  3898. if (disp_info->intf_type == DRM_MODE_CONNECTOR_DSI) {
  3899. *drm_enc_mode = DRM_MODE_ENCODER_DSI;
  3900. intf_type = INTF_DSI;
  3901. } else if (disp_info->intf_type == DRM_MODE_CONNECTOR_HDMIA) {
  3902. *drm_enc_mode = DRM_MODE_ENCODER_TMDS;
  3903. intf_type = INTF_HDMI;
  3904. } else if (disp_info->intf_type == DRM_MODE_CONNECTOR_DisplayPort) {
  3905. if (disp_info->capabilities & MSM_DISPLAY_CAP_MST_MODE)
  3906. *drm_enc_mode = DRM_MODE_ENCODER_DPMST;
  3907. else
  3908. *drm_enc_mode = DRM_MODE_ENCODER_TMDS;
  3909. intf_type = INTF_DP;
  3910. } else if (disp_info->intf_type == DRM_MODE_CONNECTOR_VIRTUAL) {
  3911. *drm_enc_mode = DRM_MODE_ENCODER_VIRTUAL;
  3912. intf_type = INTF_WB;
  3913. } else {
  3914. SDE_ERROR_ENC(sde_enc, "unsupported display interface type\n");
  3915. return -EINVAL;
  3916. }
  3917. WARN_ON(disp_info->num_of_h_tiles < 1);
  3918. sde_enc->display_num_of_h_tiles = disp_info->num_of_h_tiles;
  3919. sde_enc->te_source = disp_info->te_source;
  3920. SDE_DEBUG("dsi_info->num_of_h_tiles %d\n", disp_info->num_of_h_tiles);
  3921. if ((disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) ||
  3922. (disp_info->capabilities & MSM_DISPLAY_CAP_VID_MODE))
  3923. sde_enc->idle_pc_enabled = sde_kms->catalog->has_idle_pc;
  3924. mutex_lock(&sde_enc->enc_lock);
  3925. for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) {
  3926. /*
  3927. * Left-most tile is at index 0, content is controller id
  3928. * h_tile_instance_ids[2] = {0, 1}; DSI0 = left, DSI1 = right
  3929. * h_tile_instance_ids[2] = {1, 0}; DSI1 = left, DSI0 = right
  3930. */
  3931. u32 controller_id = disp_info->h_tile_instance[i];
  3932. if (disp_info->num_of_h_tiles > 1) {
  3933. if (i == 0)
  3934. phys_params.split_role = ENC_ROLE_MASTER;
  3935. else
  3936. phys_params.split_role = ENC_ROLE_SLAVE;
  3937. } else {
  3938. phys_params.split_role = ENC_ROLE_SOLO;
  3939. }
  3940. SDE_DEBUG("h_tile_instance %d = %d, split_role %d\n",
  3941. i, controller_id, phys_params.split_role);
  3942. if (sde_enc->ops.phys_init) {
  3943. struct sde_encoder_phys *enc;
  3944. enc = sde_enc->ops.phys_init(intf_type,
  3945. controller_id,
  3946. &phys_params);
  3947. if (enc) {
  3948. sde_enc->phys_encs[sde_enc->num_phys_encs] =
  3949. enc;
  3950. ++sde_enc->num_phys_encs;
  3951. } else
  3952. SDE_ERROR_ENC(sde_enc,
  3953. "failed to add phys encs\n");
  3954. continue;
  3955. }
  3956. if (intf_type == INTF_WB) {
  3957. phys_params.intf_idx = INTF_MAX;
  3958. phys_params.wb_idx = sde_encoder_get_wb(
  3959. sde_kms->catalog,
  3960. intf_type, controller_id);
  3961. if (phys_params.wb_idx == WB_MAX) {
  3962. SDE_ERROR_ENC(sde_enc,
  3963. "could not get wb: type %d, id %d\n",
  3964. intf_type, controller_id);
  3965. ret = -EINVAL;
  3966. }
  3967. } else {
  3968. phys_params.wb_idx = WB_MAX;
  3969. phys_params.intf_idx = sde_encoder_get_intf(
  3970. sde_kms->catalog, intf_type,
  3971. controller_id);
  3972. if (phys_params.intf_idx == INTF_MAX) {
  3973. SDE_ERROR_ENC(sde_enc,
  3974. "could not get wb: type %d, id %d\n",
  3975. intf_type, controller_id);
  3976. ret = -EINVAL;
  3977. }
  3978. }
  3979. if (!ret) {
  3980. if (intf_type == INTF_WB)
  3981. ret = sde_encoder_virt_add_phys_enc_wb(sde_enc,
  3982. &phys_params);
  3983. else
  3984. ret = sde_encoder_virt_add_phys_encs(
  3985. disp_info,
  3986. sde_enc,
  3987. &phys_params);
  3988. if (ret)
  3989. SDE_ERROR_ENC(sde_enc,
  3990. "failed to add phys encs\n");
  3991. }
  3992. }
  3993. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  3994. struct sde_encoder_phys *vid_phys = sde_enc->phys_vid_encs[i];
  3995. struct sde_encoder_phys *cmd_phys = sde_enc->phys_cmd_encs[i];
  3996. if (vid_phys) {
  3997. atomic_set(&vid_phys->vsync_cnt, 0);
  3998. atomic_set(&vid_phys->underrun_cnt, 0);
  3999. }
  4000. if (cmd_phys) {
  4001. atomic_set(&cmd_phys->vsync_cnt, 0);
  4002. atomic_set(&cmd_phys->underrun_cnt, 0);
  4003. }
  4004. }
  4005. mutex_unlock(&sde_enc->enc_lock);
  4006. return ret;
  4007. }
  4008. static const struct drm_encoder_helper_funcs sde_encoder_helper_funcs = {
  4009. .mode_set = sde_encoder_virt_mode_set,
  4010. .disable = sde_encoder_virt_disable,
  4011. .enable = sde_encoder_virt_enable,
  4012. .atomic_check = sde_encoder_virt_atomic_check,
  4013. };
  4014. static const struct drm_encoder_funcs sde_encoder_funcs = {
  4015. .destroy = sde_encoder_destroy,
  4016. .late_register = sde_encoder_late_register,
  4017. .early_unregister = sde_encoder_early_unregister,
  4018. };
  4019. struct drm_encoder *sde_encoder_init_with_ops(
  4020. struct drm_device *dev,
  4021. struct msm_display_info *disp_info,
  4022. const struct sde_encoder_ops *ops)
  4023. {
  4024. struct msm_drm_private *priv = dev->dev_private;
  4025. struct sde_kms *sde_kms = to_sde_kms(priv->kms);
  4026. struct drm_encoder *drm_enc = NULL;
  4027. struct sde_encoder_virt *sde_enc = NULL;
  4028. int drm_enc_mode = DRM_MODE_ENCODER_NONE;
  4029. char name[SDE_NAME_SIZE];
  4030. int ret = 0, i, intf_index = INTF_MAX;
  4031. struct sde_encoder_phys *phys = NULL;
  4032. sde_enc = kzalloc(sizeof(*sde_enc), GFP_KERNEL);
  4033. if (!sde_enc) {
  4034. ret = -ENOMEM;
  4035. goto fail;
  4036. }
  4037. if (ops)
  4038. sde_enc->ops = *ops;
  4039. mutex_init(&sde_enc->enc_lock);
  4040. ret = sde_encoder_setup_display(sde_enc, sde_kms, disp_info,
  4041. &drm_enc_mode);
  4042. if (ret)
  4043. goto fail;
  4044. sde_enc->cur_master = NULL;
  4045. spin_lock_init(&sde_enc->enc_spinlock);
  4046. mutex_init(&sde_enc->vblank_ctl_lock);
  4047. for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++)
  4048. atomic_set(&sde_enc->frame_done_cnt[i], 0);
  4049. drm_enc = &sde_enc->base;
  4050. drm_encoder_init(dev, drm_enc, &sde_encoder_funcs, drm_enc_mode, NULL);
  4051. drm_encoder_helper_add(drm_enc, &sde_encoder_helper_funcs);
  4052. if (disp_info->intf_type == DRM_MODE_CONNECTOR_DSI)
  4053. timer_setup(&sde_enc->vsync_event_timer,
  4054. sde_encoder_vsync_event_handler, 0);
  4055. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4056. phys = sde_enc->phys_encs[i];
  4057. if (!phys)
  4058. continue;
  4059. if (phys->ops.is_master && phys->ops.is_master(phys))
  4060. intf_index = phys->intf_idx - INTF_0;
  4061. }
  4062. snprintf(name, SDE_NAME_SIZE, "rsc_enc%u", drm_enc->base.id);
  4063. sde_enc->rsc_client = sde_rsc_client_create(SDE_RSC_INDEX, name,
  4064. (disp_info->display_type == SDE_CONNECTOR_PRIMARY) ?
  4065. SDE_RSC_PRIMARY_DISP_CLIENT :
  4066. SDE_RSC_EXTERNAL_DISP_CLIENT, intf_index + 1);
  4067. if (IS_ERR_OR_NULL(sde_enc->rsc_client)) {
  4068. SDE_DEBUG("sde rsc client create failed :%ld\n",
  4069. PTR_ERR(sde_enc->rsc_client));
  4070. sde_enc->rsc_client = NULL;
  4071. }
  4072. if (disp_info->capabilities & MSM_DISPLAY_CAP_CMD_MODE) {
  4073. ret = _sde_encoder_input_handler(sde_enc);
  4074. if (ret)
  4075. SDE_ERROR(
  4076. "input handler registration failed, rc = %d\n", ret);
  4077. }
  4078. mutex_init(&sde_enc->rc_lock);
  4079. kthread_init_delayed_work(&sde_enc->delayed_off_work,
  4080. sde_encoder_off_work);
  4081. sde_enc->vblank_enabled = false;
  4082. sde_enc->qdss_status = false;
  4083. kthread_init_work(&sde_enc->vsync_event_work,
  4084. sde_encoder_vsync_event_work_handler);
  4085. kthread_init_work(&sde_enc->input_event_work,
  4086. sde_encoder_input_event_work_handler);
  4087. kthread_init_work(&sde_enc->esd_trigger_work,
  4088. sde_encoder_esd_trigger_work_handler);
  4089. memcpy(&sde_enc->disp_info, disp_info, sizeof(*disp_info));
  4090. SDE_DEBUG_ENC(sde_enc, "created\n");
  4091. return drm_enc;
  4092. fail:
  4093. SDE_ERROR("failed to create encoder\n");
  4094. if (drm_enc)
  4095. sde_encoder_destroy(drm_enc);
  4096. return ERR_PTR(ret);
  4097. }
  4098. struct drm_encoder *sde_encoder_init(
  4099. struct drm_device *dev,
  4100. struct msm_display_info *disp_info)
  4101. {
  4102. return sde_encoder_init_with_ops(dev, disp_info, NULL);
  4103. }
  4104. int sde_encoder_wait_for_event(struct drm_encoder *drm_enc,
  4105. enum msm_event_wait event)
  4106. {
  4107. int (*fn_wait)(struct sde_encoder_phys *phys_enc) = NULL;
  4108. struct sde_encoder_virt *sde_enc = NULL;
  4109. int i, ret = 0;
  4110. char atrace_buf[32];
  4111. if (!drm_enc) {
  4112. SDE_ERROR("invalid encoder\n");
  4113. return -EINVAL;
  4114. }
  4115. sde_enc = to_sde_encoder_virt(drm_enc);
  4116. SDE_DEBUG_ENC(sde_enc, "\n");
  4117. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4118. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  4119. switch (event) {
  4120. case MSM_ENC_COMMIT_DONE:
  4121. fn_wait = phys->ops.wait_for_commit_done;
  4122. break;
  4123. case MSM_ENC_TX_COMPLETE:
  4124. fn_wait = phys->ops.wait_for_tx_complete;
  4125. break;
  4126. case MSM_ENC_VBLANK:
  4127. fn_wait = phys->ops.wait_for_vblank;
  4128. break;
  4129. case MSM_ENC_ACTIVE_REGION:
  4130. fn_wait = phys->ops.wait_for_active;
  4131. break;
  4132. default:
  4133. SDE_ERROR_ENC(sde_enc, "unknown wait event %d\n",
  4134. event);
  4135. return -EINVAL;
  4136. }
  4137. if (phys && fn_wait) {
  4138. snprintf(atrace_buf, sizeof(atrace_buf),
  4139. "wait_completion_event_%d", event);
  4140. SDE_ATRACE_BEGIN(atrace_buf);
  4141. ret = fn_wait(phys);
  4142. SDE_ATRACE_END(atrace_buf);
  4143. if (ret)
  4144. return ret;
  4145. }
  4146. }
  4147. return ret;
  4148. }
  4149. void sde_encoder_helper_get_jitter_bounds_ns(struct drm_encoder *drm_enc,
  4150. u64 *l_bound, u64 *u_bound)
  4151. {
  4152. struct sde_encoder_virt *sde_enc;
  4153. u64 jitter_ns, frametime_ns;
  4154. struct msm_mode_info *info;
  4155. if (!drm_enc) {
  4156. SDE_ERROR("invalid encoder\n");
  4157. return;
  4158. }
  4159. sde_enc = to_sde_encoder_virt(drm_enc);
  4160. info = &sde_enc->mode_info;
  4161. frametime_ns = (1 * 1000000000) / info->frame_rate;
  4162. jitter_ns = info->jitter_numer * frametime_ns;
  4163. do_div(jitter_ns, info->jitter_denom * 100);
  4164. *l_bound = frametime_ns - jitter_ns;
  4165. *u_bound = frametime_ns + jitter_ns;
  4166. }
  4167. u32 sde_encoder_get_fps(struct drm_encoder *drm_enc)
  4168. {
  4169. struct sde_encoder_virt *sde_enc;
  4170. if (!drm_enc) {
  4171. SDE_ERROR("invalid encoder\n");
  4172. return 0;
  4173. }
  4174. sde_enc = to_sde_encoder_virt(drm_enc);
  4175. return sde_enc->mode_info.frame_rate;
  4176. }
  4177. enum sde_intf_mode sde_encoder_get_intf_mode(struct drm_encoder *encoder)
  4178. {
  4179. struct sde_encoder_virt *sde_enc = NULL;
  4180. int i;
  4181. if (!encoder) {
  4182. SDE_ERROR("invalid encoder\n");
  4183. return INTF_MODE_NONE;
  4184. }
  4185. sde_enc = to_sde_encoder_virt(encoder);
  4186. if (sde_enc->cur_master)
  4187. return sde_enc->cur_master->intf_mode;
  4188. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4189. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  4190. if (phys)
  4191. return phys->intf_mode;
  4192. }
  4193. return INTF_MODE_NONE;
  4194. }
  4195. static void _sde_encoder_cache_hw_res_cont_splash(
  4196. struct drm_encoder *encoder,
  4197. struct sde_kms *sde_kms)
  4198. {
  4199. int i, idx;
  4200. struct sde_encoder_virt *sde_enc;
  4201. struct sde_encoder_phys *phys_enc;
  4202. struct sde_rm_hw_iter dsc_iter, pp_iter, ctl_iter, intf_iter;
  4203. sde_enc = to_sde_encoder_virt(encoder);
  4204. sde_rm_init_hw_iter(&pp_iter, encoder->base.id, SDE_HW_BLK_PINGPONG);
  4205. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  4206. sde_enc->hw_pp[i] = NULL;
  4207. if (!sde_rm_get_hw(&sde_kms->rm, &pp_iter))
  4208. break;
  4209. sde_enc->hw_pp[i] = (struct sde_hw_pingpong *) pp_iter.hw;
  4210. }
  4211. sde_rm_init_hw_iter(&dsc_iter, encoder->base.id, SDE_HW_BLK_DSC);
  4212. for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
  4213. sde_enc->hw_dsc[i] = NULL;
  4214. if (!sde_rm_get_hw(&sde_kms->rm, &dsc_iter))
  4215. break;
  4216. sde_enc->hw_dsc[i] = (struct sde_hw_dsc *) dsc_iter.hw;
  4217. }
  4218. /*
  4219. * If we have multiple phys encoders with one controller, make
  4220. * sure to populate the controller pointer in both phys encoders.
  4221. */
  4222. for (idx = 0; idx < sde_enc->num_phys_encs; idx++) {
  4223. phys_enc = sde_enc->phys_encs[idx];
  4224. phys_enc->hw_ctl = NULL;
  4225. sde_rm_init_hw_iter(&ctl_iter, encoder->base.id,
  4226. SDE_HW_BLK_CTL);
  4227. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4228. if (sde_rm_get_hw(&sde_kms->rm, &ctl_iter)) {
  4229. phys_enc->hw_ctl =
  4230. (struct sde_hw_ctl *) ctl_iter.hw;
  4231. pr_debug("HW CTL intf_idx:%d hw_ctl:[0x%pK]\n",
  4232. phys_enc->intf_idx, phys_enc->hw_ctl);
  4233. }
  4234. }
  4235. }
  4236. sde_rm_init_hw_iter(&intf_iter, encoder->base.id, SDE_HW_BLK_INTF);
  4237. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4238. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  4239. phys->hw_intf = NULL;
  4240. if (!sde_rm_get_hw(&sde_kms->rm, &intf_iter))
  4241. break;
  4242. phys->hw_intf = (struct sde_hw_intf *) intf_iter.hw;
  4243. }
  4244. }
  4245. /**
  4246. * sde_encoder_update_caps_for_cont_splash - update encoder settings during
  4247. * device bootup when cont_splash is enabled
  4248. * @drm_enc: Pointer to drm encoder structure
  4249. * @splash_display: Pointer to sde_splash_display corresponding to this encoder
  4250. * @enable: boolean indicates enable or displae state of splash
  4251. * @Return: true if successful in updating the encoder structure
  4252. */
  4253. int sde_encoder_update_caps_for_cont_splash(struct drm_encoder *encoder,
  4254. struct sde_splash_display *splash_display, bool enable)
  4255. {
  4256. struct sde_encoder_virt *sde_enc;
  4257. struct msm_drm_private *priv;
  4258. struct sde_kms *sde_kms;
  4259. struct drm_connector *conn = NULL;
  4260. struct sde_connector *sde_conn = NULL;
  4261. struct sde_connector_state *sde_conn_state = NULL;
  4262. struct drm_display_mode *drm_mode = NULL;
  4263. struct sde_encoder_phys *phys_enc;
  4264. int ret = 0, i;
  4265. if (!encoder) {
  4266. SDE_ERROR("invalid drm enc\n");
  4267. return -EINVAL;
  4268. }
  4269. sde_enc = to_sde_encoder_virt(encoder);
  4270. sde_kms = sde_encoder_get_kms(&sde_enc->base);
  4271. if (!sde_kms) {
  4272. SDE_ERROR("invalid sde_kms\n");
  4273. return -EINVAL;
  4274. }
  4275. priv = encoder->dev->dev_private;
  4276. if (!priv->num_connectors) {
  4277. SDE_ERROR_ENC(sde_enc, "No connectors registered\n");
  4278. return -EINVAL;
  4279. }
  4280. SDE_DEBUG_ENC(sde_enc,
  4281. "num of connectors: %d\n", priv->num_connectors);
  4282. SDE_DEBUG_ENC(sde_enc, "enable: %d\n", enable);
  4283. if (!enable) {
  4284. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4285. phys_enc = sde_enc->phys_encs[i];
  4286. if (phys_enc)
  4287. phys_enc->cont_splash_enabled = false;
  4288. }
  4289. return ret;
  4290. }
  4291. if (!splash_display) {
  4292. SDE_ERROR_ENC(sde_enc, "invalid splash data\n");
  4293. return -EINVAL;
  4294. }
  4295. for (i = 0; i < priv->num_connectors; i++) {
  4296. SDE_DEBUG_ENC(sde_enc, "connector id: %d\n",
  4297. priv->connectors[i]->base.id);
  4298. sde_conn = to_sde_connector(priv->connectors[i]);
  4299. if (!sde_conn->encoder) {
  4300. SDE_DEBUG_ENC(sde_enc,
  4301. "encoder not attached to connector\n");
  4302. continue;
  4303. }
  4304. if (sde_conn->encoder->base.id
  4305. == encoder->base.id) {
  4306. conn = (priv->connectors[i]);
  4307. break;
  4308. }
  4309. }
  4310. if (!conn || !conn->state) {
  4311. SDE_ERROR_ENC(sde_enc, "connector not found\n");
  4312. return -EINVAL;
  4313. }
  4314. sde_conn_state = to_sde_connector_state(conn->state);
  4315. if (!sde_conn->ops.get_mode_info) {
  4316. SDE_ERROR_ENC(sde_enc, "conn: get_mode_info ops not found\n");
  4317. return -EINVAL;
  4318. }
  4319. ret = sde_connector_get_mode_info(&sde_conn->base,
  4320. &encoder->crtc->state->adjusted_mode,
  4321. &sde_conn_state->mode_info);
  4322. if (ret) {
  4323. SDE_ERROR_ENC(sde_enc,
  4324. "conn: ->get_mode_info failed. ret=%d\n", ret);
  4325. return ret;
  4326. }
  4327. if (sde_conn->encoder) {
  4328. conn->state->best_encoder = sde_conn->encoder;
  4329. SDE_DEBUG_ENC(sde_enc,
  4330. "configured cstate->best_encoder to ID = %d\n",
  4331. conn->state->best_encoder->base.id);
  4332. } else {
  4333. SDE_ERROR_ENC(sde_enc, "No encoder mapped to connector=%d\n",
  4334. conn->base.id);
  4335. }
  4336. ret = sde_rm_reserve(&sde_kms->rm, encoder, encoder->crtc->state,
  4337. conn->state, false);
  4338. if (ret) {
  4339. SDE_ERROR_ENC(sde_enc,
  4340. "failed to reserve hw resources, %d\n", ret);
  4341. return ret;
  4342. }
  4343. SDE_DEBUG_ENC(sde_enc, "connector topology = %llu\n",
  4344. sde_connector_get_topology_name(conn));
  4345. drm_mode = &encoder->crtc->state->adjusted_mode;
  4346. SDE_DEBUG_ENC(sde_enc, "hdisplay = %d, vdisplay = %d\n",
  4347. drm_mode->hdisplay, drm_mode->vdisplay);
  4348. drm_set_preferred_mode(conn, drm_mode->hdisplay, drm_mode->vdisplay);
  4349. if (encoder->bridge) {
  4350. SDE_DEBUG_ENC(sde_enc, "Bridge mapped to encoder\n");
  4351. /*
  4352. * For cont-splash use case, we update the mode
  4353. * configurations manually. This will skip the
  4354. * usually mode set call when actual frame is
  4355. * pushed from framework. The bridge needs to
  4356. * be updated with the current drm mode by
  4357. * calling the bridge mode set ops.
  4358. */
  4359. if (encoder->bridge->funcs) {
  4360. SDE_DEBUG_ENC(sde_enc, "calling mode_set\n");
  4361. encoder->bridge->funcs->mode_set(encoder->bridge,
  4362. drm_mode, drm_mode);
  4363. }
  4364. } else {
  4365. SDE_ERROR_ENC(sde_enc, "No bridge attached to encoder\n");
  4366. }
  4367. _sde_encoder_cache_hw_res_cont_splash(encoder, sde_kms);
  4368. for (i = 0; i < sde_enc->num_phys_encs; i++) {
  4369. struct sde_encoder_phys *phys = sde_enc->phys_encs[i];
  4370. if (!phys) {
  4371. SDE_ERROR_ENC(sde_enc,
  4372. "phys encoders not initialized\n");
  4373. return -EINVAL;
  4374. }
  4375. /* update connector for master and slave phys encoders */
  4376. phys->connector = conn;
  4377. phys->cont_splash_enabled = true;
  4378. phys->hw_pp = sde_enc->hw_pp[i];
  4379. if (phys->ops.cont_splash_mode_set)
  4380. phys->ops.cont_splash_mode_set(phys, drm_mode);
  4381. if (phys->ops.is_master && phys->ops.is_master(phys))
  4382. sde_enc->cur_master = phys;
  4383. }
  4384. return ret;
  4385. }
  4386. int sde_encoder_display_failure_notification(struct drm_encoder *enc,
  4387. bool skip_pre_kickoff)
  4388. {
  4389. struct msm_drm_thread *event_thread = NULL;
  4390. struct msm_drm_private *priv = NULL;
  4391. struct sde_encoder_virt *sde_enc = NULL;
  4392. if (!enc || !enc->dev || !enc->dev->dev_private) {
  4393. SDE_ERROR("invalid parameters\n");
  4394. return -EINVAL;
  4395. }
  4396. priv = enc->dev->dev_private;
  4397. sde_enc = to_sde_encoder_virt(enc);
  4398. if (!sde_enc->crtc || (sde_enc->crtc->index
  4399. >= ARRAY_SIZE(priv->event_thread))) {
  4400. SDE_DEBUG_ENC(sde_enc,
  4401. "invalid cached CRTC: %d or crtc index: %d\n",
  4402. sde_enc->crtc == NULL,
  4403. sde_enc->crtc ? sde_enc->crtc->index : -EINVAL);
  4404. return -EINVAL;
  4405. }
  4406. SDE_EVT32_VERBOSE(DRMID(enc));
  4407. event_thread = &priv->event_thread[sde_enc->crtc->index];
  4408. if (!skip_pre_kickoff) {
  4409. kthread_queue_work(&event_thread->worker,
  4410. &sde_enc->esd_trigger_work);
  4411. kthread_flush_work(&sde_enc->esd_trigger_work);
  4412. }
  4413. /*
  4414. * panel may stop generating te signal (vsync) during esd failure. rsc
  4415. * hardware may hang without vsync. Avoid rsc hang by generating the
  4416. * vsync from watchdog timer instead of panel.
  4417. */
  4418. sde_encoder_helper_switch_vsync(enc, true);
  4419. if (!skip_pre_kickoff)
  4420. sde_encoder_wait_for_event(enc, MSM_ENC_TX_COMPLETE);
  4421. return 0;
  4422. }
  4423. bool sde_encoder_recovery_events_enabled(struct drm_encoder *encoder)
  4424. {
  4425. struct sde_encoder_virt *sde_enc;
  4426. if (!encoder) {
  4427. SDE_ERROR("invalid drm enc\n");
  4428. return false;
  4429. }
  4430. sde_enc = to_sde_encoder_virt(encoder);
  4431. return sde_enc->recovery_events_enabled;
  4432. }
  4433. void sde_encoder_recovery_events_handler(struct drm_encoder *encoder,
  4434. bool enabled)
  4435. {
  4436. struct sde_encoder_virt *sde_enc;
  4437. if (!encoder) {
  4438. SDE_ERROR("invalid drm enc\n");
  4439. return;
  4440. }
  4441. sde_enc = to_sde_encoder_virt(encoder);
  4442. sde_enc->recovery_events_enabled = enabled;
  4443. }