sde_plane.c 132 KB

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  1. /*
  2. * Copyright (C) 2014-2020 The Linux Foundation. All rights reserved.
  3. * Copyright (C) 2013 Red Hat
  4. * Author: Rob Clark <[email protected]>
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published by
  8. * the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but WITHOUT
  11. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  13. * more details.
  14. *
  15. * You should have received a copy of the GNU General Public License along with
  16. * this program. If not, see <http://www.gnu.org/licenses/>.
  17. */
  18. #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__
  19. #include <linux/debugfs.h>
  20. #include <linux/dma-buf.h>
  21. #include <drm/sde_drm.h>
  22. #include <drm/msm_drm_pp.h>
  23. #include "msm_prop.h"
  24. #include "msm_drv.h"
  25. #include "sde_kms.h"
  26. #include "sde_fence.h"
  27. #include "sde_formats.h"
  28. #include "sde_hw_sspp.h"
  29. #include "sde_hw_catalog_format.h"
  30. #include "sde_trace.h"
  31. #include "sde_crtc.h"
  32. #include "sde_vbif.h"
  33. #include "sde_plane.h"
  34. #include "sde_color_processing.h"
  35. #define SDE_DEBUG_PLANE(pl, fmt, ...) SDE_DEBUG("plane%d " fmt,\
  36. (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
  37. #define SDE_ERROR_PLANE(pl, fmt, ...) SDE_ERROR("plane%d " fmt,\
  38. (pl) ? (pl)->base.base.id : -1, ##__VA_ARGS__)
  39. #define DECIMATED_DIMENSION(dim, deci) (((dim) + ((1 << (deci)) - 1)) >> (deci))
  40. #define PHASE_STEP_SHIFT 21
  41. #define PHASE_STEP_UNIT_SCALE ((int) (1 << PHASE_STEP_SHIFT))
  42. #define PHASE_RESIDUAL 15
  43. #define SHARP_STRENGTH_DEFAULT 32
  44. #define SHARP_EDGE_THR_DEFAULT 112
  45. #define SHARP_SMOOTH_THR_DEFAULT 8
  46. #define SHARP_NOISE_THR_DEFAULT 2
  47. #define SDE_NAME_SIZE 12
  48. #define SDE_PLANE_COLOR_FILL_FLAG BIT(31)
  49. #define TIME_MULTIPLEX_RECT(r0, r1, buffer_lines) \
  50. ((r0).y >= ((r1).y + (r1).h + buffer_lines))
  51. /* multirect rect index */
  52. enum {
  53. R0,
  54. R1,
  55. R_MAX
  56. };
  57. #define SDE_QSEED_DEFAULT_DYN_EXP 0x0
  58. #define DEFAULT_REFRESH_RATE 60
  59. /**
  60. * enum sde_plane_qos - Different qos configurations for each pipe
  61. *
  62. * @SDE_PLANE_QOS_VBLANK_CTRL: Setup VBLANK qos for the pipe.
  63. * @SDE_PLANE_QOS_VBLANK_AMORTIZE: Enables Amortization within pipe.
  64. * this configuration is mutually exclusive from VBLANK_CTRL.
  65. * @SDE_PLANE_QOS_PANIC_CTRL: Setup panic for the pipe.
  66. */
  67. enum sde_plane_qos {
  68. SDE_PLANE_QOS_VBLANK_CTRL = BIT(0),
  69. SDE_PLANE_QOS_VBLANK_AMORTIZE = BIT(1),
  70. SDE_PLANE_QOS_PANIC_CTRL = BIT(2),
  71. };
  72. /*
  73. * struct sde_plane - local sde plane structure
  74. * @aspace: address space pointer
  75. * @csc_cfg: Decoded user configuration for csc
  76. * @csc_usr_ptr: Points to csc_cfg if valid user config available
  77. * @csc_ptr: Points to sde_csc_cfg structure to use for current
  78. * @mplane_list: List of multirect planes of the same pipe
  79. * @catalog: Points to sde catalog structure
  80. * @revalidate: force revalidation of all the plane properties
  81. * @xin_halt_forced_clk: whether or not clocks were forced on for xin halt
  82. * @blob_rot_caps: Pointer to rotator capability blob
  83. */
  84. struct sde_plane {
  85. struct drm_plane base;
  86. struct mutex lock;
  87. enum sde_sspp pipe;
  88. uint32_t features; /* capabilities from catalog */
  89. uint32_t perf_features; /* perf capabilities from catalog */
  90. uint32_t nformats;
  91. uint32_t formats[64];
  92. struct sde_hw_pipe *pipe_hw;
  93. struct sde_hw_pipe_cfg pipe_cfg;
  94. struct sde_hw_sharp_cfg sharp_cfg;
  95. struct sde_hw_pipe_qos_cfg pipe_qos_cfg;
  96. uint32_t color_fill;
  97. bool is_error;
  98. bool is_rt_pipe;
  99. bool is_virtual;
  100. struct list_head mplane_list;
  101. struct sde_mdss_cfg *catalog;
  102. bool revalidate;
  103. bool xin_halt_forced_clk;
  104. struct sde_csc_cfg csc_cfg;
  105. struct sde_csc_cfg *csc_usr_ptr;
  106. struct sde_csc_cfg *csc_ptr;
  107. const struct sde_sspp_sub_blks *pipe_sblk;
  108. char pipe_name[SDE_NAME_SIZE];
  109. struct msm_property_info property_info;
  110. struct msm_property_data property_data[PLANE_PROP_COUNT];
  111. struct drm_property_blob *blob_info;
  112. struct drm_property_blob *blob_rot_caps;
  113. /* debugfs related stuff */
  114. struct dentry *debugfs_root;
  115. bool debugfs_default_scale;
  116. };
  117. #define to_sde_plane(x) container_of(x, struct sde_plane, base)
  118. static int plane_prop_array[PLANE_PROP_COUNT] = {SDE_PLANE_DIRTY_ALL};
  119. static struct sde_kms *_sde_plane_get_kms(struct drm_plane *plane)
  120. {
  121. struct msm_drm_private *priv;
  122. if (!plane || !plane->dev)
  123. return NULL;
  124. priv = plane->dev->dev_private;
  125. if (!priv)
  126. return NULL;
  127. return to_sde_kms(priv->kms);
  128. }
  129. static struct sde_hw_ctl *_sde_plane_get_hw_ctl(const struct drm_plane *plane)
  130. {
  131. struct drm_plane_state *pstate = NULL;
  132. struct drm_crtc *drm_crtc = NULL;
  133. struct sde_crtc *sde_crtc = NULL;
  134. struct sde_crtc_mixer *mixer = NULL;
  135. struct sde_hw_ctl *ctl = NULL;
  136. if (!plane) {
  137. DRM_ERROR("Invalid plane %pK\n", plane);
  138. return NULL;
  139. }
  140. pstate = plane->state;
  141. if (!pstate) {
  142. DRM_ERROR("Invalid plane state %pK\n", pstate);
  143. return NULL;
  144. }
  145. drm_crtc = pstate->crtc;
  146. if (!drm_crtc) {
  147. DRM_ERROR("Invalid drm_crtc %pK\n", drm_crtc);
  148. return NULL;
  149. }
  150. sde_crtc = to_sde_crtc(drm_crtc);
  151. if (!sde_crtc) {
  152. DRM_ERROR("invalid sde_crtc %pK\n", sde_crtc);
  153. return NULL;
  154. }
  155. /* it will always return the first mixer and single CTL */
  156. mixer = sde_crtc->mixers;
  157. if (!mixer) {
  158. DRM_ERROR("invalid mixer %pK\n", mixer);
  159. return NULL;
  160. }
  161. ctl = mixer->hw_ctl;
  162. if (!mixer) {
  163. DRM_ERROR("invalid ctl %pK\n", ctl);
  164. return NULL;
  165. }
  166. return ctl;
  167. }
  168. static bool sde_plane_enabled(const struct drm_plane_state *state)
  169. {
  170. return state && state->fb && state->crtc;
  171. }
  172. bool sde_plane_is_sec_ui_allowed(struct drm_plane *plane)
  173. {
  174. struct sde_plane *psde;
  175. if (!plane)
  176. return false;
  177. psde = to_sde_plane(plane);
  178. return !(psde->features & BIT(SDE_SSPP_BLOCK_SEC_UI));
  179. }
  180. void sde_plane_setup_src_split_order(struct drm_plane *plane,
  181. enum sde_sspp_multirect_index rect_mode, bool enable)
  182. {
  183. struct sde_plane *psde;
  184. if (!plane)
  185. return;
  186. psde = to_sde_plane(plane);
  187. if (psde->pipe_hw->ops.set_src_split_order)
  188. psde->pipe_hw->ops.set_src_split_order(psde->pipe_hw,
  189. rect_mode, enable);
  190. }
  191. void sde_plane_set_sid(struct drm_plane *plane, u32 vm)
  192. {
  193. struct sde_plane *psde;
  194. struct sde_kms *sde_kms;
  195. struct msm_drm_private *priv;
  196. if (!plane || !plane->dev) {
  197. SDE_ERROR("invalid plane %d\n");
  198. return;
  199. }
  200. priv = plane->dev->dev_private;
  201. if (!priv || !priv->kms) {
  202. SDE_ERROR("invalid KMS reference\n");
  203. return;
  204. }
  205. sde_kms = to_sde_kms(priv->kms);
  206. psde = to_sde_plane(plane);
  207. sde_hw_set_sspp_sid(sde_kms->hw_sid, psde->pipe, vm);
  208. }
  209. /**
  210. * _sde_plane_set_qos_lut - set danger, safe and creq LUT of the given plane
  211. * @plane: Pointer to drm plane
  212. * @crtc: Pointer to drm crtc to find refresh rate on mode
  213. * @fb: Pointer to framebuffer associated with the given plane
  214. */
  215. static void _sde_plane_set_qos_lut(struct drm_plane *plane,
  216. struct drm_crtc *crtc,
  217. struct drm_framebuffer *fb)
  218. {
  219. struct sde_plane *psde;
  220. const struct sde_format *fmt = NULL;
  221. u32 frame_rate, qos_count, fps_index = 0, lut_index, index;
  222. struct sde_perf_cfg *perf;
  223. struct sde_plane_state *pstate;
  224. if (!plane || !fb) {
  225. SDE_ERROR("invalid arguments\n");
  226. return;
  227. }
  228. psde = to_sde_plane(plane);
  229. pstate = to_sde_plane_state(plane->state);
  230. if (!psde->pipe_hw || !psde->pipe_sblk || !psde->catalog) {
  231. SDE_ERROR("invalid arguments\n");
  232. return;
  233. } else if (!psde->pipe_hw->ops.setup_qos_lut) {
  234. return;
  235. }
  236. frame_rate = crtc->mode.vrefresh;
  237. perf = &psde->catalog->perf;
  238. qos_count = perf->qos_refresh_count;
  239. while (qos_count && perf->qos_refresh_rate) {
  240. if (frame_rate >= perf->qos_refresh_rate[qos_count - 1]) {
  241. fps_index = qos_count - 1;
  242. break;
  243. }
  244. qos_count--;
  245. }
  246. if (!psde->is_rt_pipe) {
  247. lut_index = SDE_QOS_LUT_USAGE_NRT;
  248. } else {
  249. fmt = sde_get_sde_format_ext(
  250. fb->format->format,
  251. fb->modifier);
  252. if (fmt && SDE_FORMAT_IS_LINEAR(fmt) &&
  253. pstate->scaler3_cfg.enable)
  254. lut_index = SDE_QOS_LUT_USAGE_LINEAR_QSEED;
  255. else if (fmt && SDE_FORMAT_IS_LINEAR(fmt))
  256. lut_index = SDE_QOS_LUT_USAGE_LINEAR;
  257. else if (pstate->scaler3_cfg.enable)
  258. lut_index = SDE_QOS_LUT_USAGE_MACROTILE_QSEED;
  259. else
  260. lut_index = SDE_QOS_LUT_USAGE_MACROTILE;
  261. }
  262. index = (fps_index * SDE_QOS_LUT_USAGE_MAX) + lut_index;
  263. psde->pipe_qos_cfg.danger_lut = perf->danger_lut[index];
  264. psde->pipe_qos_cfg.safe_lut = perf->safe_lut[index];
  265. psde->pipe_qos_cfg.creq_lut = perf->creq_lut[index];
  266. trace_sde_perf_set_qos_luts(psde->pipe - SSPP_VIG0,
  267. (fmt) ? fmt->base.pixel_format : 0,
  268. (fmt) ? fmt->fetch_mode : 0,
  269. psde->pipe_qos_cfg.danger_lut,
  270. psde->pipe_qos_cfg.safe_lut,
  271. psde->pipe_qos_cfg.creq_lut);
  272. SDE_DEBUG(
  273. "plane%u: pnum:%d fmt:%4.4s fps:%d mode:%d luts[0x%x,0x%x 0x%llx]\n",
  274. plane->base.id,
  275. psde->pipe - SSPP_VIG0,
  276. fmt ? (char *)&fmt->base.pixel_format : NULL, frame_rate,
  277. fmt ? fmt->fetch_mode : -1,
  278. psde->pipe_qos_cfg.danger_lut,
  279. psde->pipe_qos_cfg.safe_lut,
  280. psde->pipe_qos_cfg.creq_lut);
  281. psde->pipe_hw->ops.setup_qos_lut(psde->pipe_hw, &psde->pipe_qos_cfg);
  282. }
  283. /**
  284. * _sde_plane_set_qos_ctrl - set QoS control of the given plane
  285. * @plane: Pointer to drm plane
  286. * @enable: true to enable QoS control
  287. * @flags: QoS control mode (enum sde_plane_qos)
  288. */
  289. static void _sde_plane_set_qos_ctrl(struct drm_plane *plane,
  290. bool enable, u32 flags)
  291. {
  292. struct sde_plane *psde;
  293. if (!plane) {
  294. SDE_ERROR("invalid arguments\n");
  295. return;
  296. }
  297. psde = to_sde_plane(plane);
  298. if (!psde->pipe_hw || !psde->pipe_sblk) {
  299. SDE_ERROR("invalid arguments\n");
  300. return;
  301. } else if (!psde->pipe_hw->ops.setup_qos_ctrl) {
  302. return;
  303. }
  304. if (flags & SDE_PLANE_QOS_VBLANK_CTRL) {
  305. psde->pipe_qos_cfg.creq_vblank = psde->pipe_sblk->creq_vblank;
  306. psde->pipe_qos_cfg.danger_vblank =
  307. psde->pipe_sblk->danger_vblank;
  308. psde->pipe_qos_cfg.vblank_en = enable;
  309. }
  310. if (flags & SDE_PLANE_QOS_VBLANK_AMORTIZE) {
  311. /* this feature overrules previous VBLANK_CTRL */
  312. psde->pipe_qos_cfg.vblank_en = false;
  313. psde->pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */
  314. }
  315. if (flags & SDE_PLANE_QOS_PANIC_CTRL)
  316. psde->pipe_qos_cfg.danger_safe_en = enable;
  317. if (!psde->is_rt_pipe) {
  318. psde->pipe_qos_cfg.vblank_en = false;
  319. psde->pipe_qos_cfg.danger_safe_en = false;
  320. }
  321. SDE_DEBUG("plane%u: pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n",
  322. plane->base.id,
  323. psde->pipe - SSPP_VIG0,
  324. psde->pipe_qos_cfg.danger_safe_en,
  325. psde->pipe_qos_cfg.vblank_en,
  326. psde->pipe_qos_cfg.creq_vblank,
  327. psde->pipe_qos_cfg.danger_vblank,
  328. psde->is_rt_pipe);
  329. psde->pipe_hw->ops.setup_qos_ctrl(psde->pipe_hw,
  330. &psde->pipe_qos_cfg);
  331. }
  332. void sde_plane_set_revalidate(struct drm_plane *plane, bool enable)
  333. {
  334. struct sde_plane *psde;
  335. if (!plane)
  336. return;
  337. psde = to_sde_plane(plane);
  338. psde->revalidate = enable;
  339. }
  340. int sde_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable)
  341. {
  342. struct sde_plane *psde;
  343. int rc;
  344. if (!plane) {
  345. SDE_ERROR("invalid arguments\n");
  346. return -EINVAL;
  347. }
  348. psde = to_sde_plane(plane);
  349. if (!psde->is_rt_pipe)
  350. goto end;
  351. rc = pm_runtime_get_sync(plane->dev->dev);
  352. if (rc < 0) {
  353. SDE_ERROR("failed to enable power resource %d\n", rc);
  354. SDE_EVT32(rc, SDE_EVTLOG_ERROR);
  355. return rc;
  356. }
  357. _sde_plane_set_qos_ctrl(plane, enable, SDE_PLANE_QOS_PANIC_CTRL);
  358. pm_runtime_put_sync(plane->dev->dev);
  359. end:
  360. return 0;
  361. }
  362. /**
  363. * _sde_plane_set_ot_limit - set OT limit for the given plane
  364. * @plane: Pointer to drm plane
  365. * @crtc: Pointer to drm crtc
  366. */
  367. static void _sde_plane_set_ot_limit(struct drm_plane *plane,
  368. struct drm_crtc *crtc)
  369. {
  370. struct sde_plane *psde;
  371. struct sde_vbif_set_ot_params ot_params;
  372. struct msm_drm_private *priv;
  373. struct sde_kms *sde_kms;
  374. if (!plane || !plane->dev || !crtc) {
  375. SDE_ERROR("invalid arguments plane %d crtc %d\n",
  376. !plane, !crtc);
  377. return;
  378. }
  379. priv = plane->dev->dev_private;
  380. if (!priv || !priv->kms) {
  381. SDE_ERROR("invalid KMS reference\n");
  382. return;
  383. }
  384. sde_kms = to_sde_kms(priv->kms);
  385. psde = to_sde_plane(plane);
  386. if (!psde->pipe_hw) {
  387. SDE_ERROR("invalid pipe reference\n");
  388. return;
  389. }
  390. memset(&ot_params, 0, sizeof(ot_params));
  391. ot_params.xin_id = psde->pipe_hw->cap->xin_id;
  392. ot_params.num = psde->pipe_hw->idx - SSPP_NONE;
  393. ot_params.width = psde->pipe_cfg.src_rect.w;
  394. ot_params.height = psde->pipe_cfg.src_rect.h;
  395. ot_params.is_wfd = !psde->is_rt_pipe;
  396. ot_params.frame_rate = crtc->mode.vrefresh;
  397. ot_params.vbif_idx = VBIF_RT;
  398. ot_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  399. ot_params.rd = true;
  400. sde_vbif_set_ot_limit(sde_kms, &ot_params);
  401. }
  402. /**
  403. * _sde_plane_set_vbif_qos - set vbif QoS for the given plane
  404. * @plane: Pointer to drm plane
  405. */
  406. static void _sde_plane_set_qos_remap(struct drm_plane *plane)
  407. {
  408. struct sde_plane *psde;
  409. struct sde_vbif_set_qos_params qos_params;
  410. struct msm_drm_private *priv;
  411. struct sde_kms *sde_kms;
  412. if (!plane || !plane->dev) {
  413. SDE_ERROR("invalid arguments\n");
  414. return;
  415. }
  416. priv = plane->dev->dev_private;
  417. if (!priv || !priv->kms) {
  418. SDE_ERROR("invalid KMS reference\n");
  419. return;
  420. }
  421. sde_kms = to_sde_kms(priv->kms);
  422. psde = to_sde_plane(plane);
  423. if (!psde->pipe_hw) {
  424. SDE_ERROR("invalid pipe reference\n");
  425. return;
  426. }
  427. memset(&qos_params, 0, sizeof(qos_params));
  428. qos_params.vbif_idx = VBIF_RT;
  429. qos_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  430. qos_params.xin_id = psde->pipe_hw->cap->xin_id;
  431. qos_params.num = psde->pipe_hw->idx - SSPP_VIG0;
  432. qos_params.client_type = psde->is_rt_pipe ?
  433. VBIF_RT_CLIENT : VBIF_NRT_CLIENT;
  434. SDE_DEBUG("plane%d pipe:%d vbif:%d xin:%d rt:%d, clk_ctrl:%d\n",
  435. plane->base.id, qos_params.num,
  436. qos_params.vbif_idx,
  437. qos_params.xin_id, qos_params.client_type,
  438. qos_params.clk_ctrl);
  439. sde_vbif_set_qos_remap(sde_kms, &qos_params);
  440. }
  441. /**
  442. * _sde_plane_set_ts_prefill - set prefill with traffic shaper
  443. * @plane: Pointer to drm plane
  444. * @pstate: Pointer to sde plane state
  445. */
  446. static void _sde_plane_set_ts_prefill(struct drm_plane *plane,
  447. struct sde_plane_state *pstate)
  448. {
  449. struct sde_plane *psde;
  450. struct sde_hw_pipe_ts_cfg cfg;
  451. struct msm_drm_private *priv;
  452. struct sde_kms *sde_kms;
  453. if (!plane || !plane->dev) {
  454. SDE_ERROR("invalid arguments");
  455. return;
  456. }
  457. priv = plane->dev->dev_private;
  458. if (!priv || !priv->kms) {
  459. SDE_ERROR("invalid KMS reference\n");
  460. return;
  461. }
  462. sde_kms = to_sde_kms(priv->kms);
  463. psde = to_sde_plane(plane);
  464. if (!psde->pipe_hw) {
  465. SDE_ERROR("invalid pipe reference\n");
  466. return;
  467. }
  468. if (!psde->pipe_hw || !psde->pipe_hw->ops.setup_ts_prefill)
  469. return;
  470. _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_VBLANK_AMORTIZE);
  471. memset(&cfg, 0, sizeof(cfg));
  472. cfg.size = sde_plane_get_property(pstate,
  473. PLANE_PROP_PREFILL_SIZE);
  474. cfg.time = sde_plane_get_property(pstate,
  475. PLANE_PROP_PREFILL_TIME);
  476. SDE_DEBUG("plane%d size:%llu time:%llu\n",
  477. plane->base.id, cfg.size, cfg.time);
  478. SDE_EVT32_VERBOSE(DRMID(plane), cfg.size, cfg.time);
  479. psde->pipe_hw->ops.setup_ts_prefill(psde->pipe_hw, &cfg,
  480. pstate->multirect_index);
  481. }
  482. /* helper to update a state's input fence pointer from the property */
  483. static void _sde_plane_set_input_fence(struct sde_plane *psde,
  484. struct sde_plane_state *pstate, uint64_t fd)
  485. {
  486. if (!psde || !pstate) {
  487. SDE_ERROR("invalid arg(s), plane %d state %d\n",
  488. !psde, !pstate);
  489. return;
  490. }
  491. /* clear previous reference */
  492. if (pstate->input_fence)
  493. sde_sync_put(pstate->input_fence);
  494. /* get fence pointer for later */
  495. if (fd == 0)
  496. pstate->input_fence = NULL;
  497. else
  498. pstate->input_fence = sde_sync_get(fd);
  499. SDE_DEBUG_PLANE(psde, "0x%llX\n", fd);
  500. }
  501. int sde_plane_wait_input_fence(struct drm_plane *plane, uint32_t wait_ms)
  502. {
  503. struct sde_plane *psde;
  504. struct sde_plane_state *pstate;
  505. uint32_t prefix;
  506. void *input_fence;
  507. int ret = -EINVAL;
  508. signed long rc;
  509. if (!plane) {
  510. SDE_ERROR("invalid plane\n");
  511. } else if (!plane->state) {
  512. SDE_ERROR_PLANE(to_sde_plane(plane), "invalid state\n");
  513. } else {
  514. psde = to_sde_plane(plane);
  515. pstate = to_sde_plane_state(plane->state);
  516. input_fence = pstate->input_fence;
  517. if (input_fence) {
  518. prefix = sde_sync_get_name_prefix(input_fence);
  519. rc = sde_sync_wait(input_fence, wait_ms);
  520. switch (rc) {
  521. case 0:
  522. SDE_ERROR_PLANE(psde, "%ums timeout on %08X fd %d\n",
  523. wait_ms, prefix, sde_plane_get_property(pstate,
  524. PLANE_PROP_INPUT_FENCE));
  525. psde->is_error = true;
  526. sde_kms_timeline_status(plane->dev);
  527. ret = -ETIMEDOUT;
  528. break;
  529. case -ERESTARTSYS:
  530. SDE_ERROR_PLANE(psde,
  531. "%ums wait interrupted on %08X\n",
  532. wait_ms, prefix);
  533. psde->is_error = true;
  534. ret = -ERESTARTSYS;
  535. break;
  536. case -EINVAL:
  537. SDE_ERROR_PLANE(psde,
  538. "invalid fence param for %08X\n",
  539. prefix);
  540. psde->is_error = true;
  541. ret = -EINVAL;
  542. break;
  543. default:
  544. SDE_DEBUG_PLANE(psde, "signaled\n");
  545. ret = 0;
  546. break;
  547. }
  548. SDE_EVT32_VERBOSE(DRMID(plane), -ret, prefix);
  549. } else {
  550. ret = 0;
  551. }
  552. }
  553. return ret;
  554. }
  555. /**
  556. * _sde_plane_get_aspace: gets the address space based on the
  557. * fb_translation mode property
  558. */
  559. static int _sde_plane_get_aspace(
  560. struct sde_plane *psde,
  561. struct sde_plane_state *pstate,
  562. struct msm_gem_address_space **aspace)
  563. {
  564. struct sde_kms *kms;
  565. int mode;
  566. if (!psde || !pstate || !aspace) {
  567. SDE_ERROR("invalid parameters\n");
  568. return -EINVAL;
  569. }
  570. kms = _sde_plane_get_kms(&psde->base);
  571. if (!kms) {
  572. SDE_ERROR("invalid kms\n");
  573. return -EINVAL;
  574. }
  575. mode = sde_plane_get_property(pstate,
  576. PLANE_PROP_FB_TRANSLATION_MODE);
  577. switch (mode) {
  578. case SDE_DRM_FB_NON_SEC:
  579. *aspace = kms->aspace[MSM_SMMU_DOMAIN_UNSECURE];
  580. if (!aspace)
  581. return -EINVAL;
  582. break;
  583. case SDE_DRM_FB_SEC:
  584. *aspace = kms->aspace[MSM_SMMU_DOMAIN_SECURE];
  585. if (!aspace)
  586. return -EINVAL;
  587. break;
  588. case SDE_DRM_FB_NON_SEC_DIR_TRANS:
  589. case SDE_DRM_FB_SEC_DIR_TRANS:
  590. *aspace = NULL;
  591. break;
  592. default:
  593. SDE_ERROR("invalid fb_translation mode:%d\n", mode);
  594. return -EFAULT;
  595. }
  596. return 0;
  597. }
  598. static inline void _sde_plane_set_scanout(struct drm_plane *plane,
  599. struct sde_plane_state *pstate,
  600. struct sde_hw_pipe_cfg *pipe_cfg,
  601. struct drm_framebuffer *fb)
  602. {
  603. struct sde_plane *psde;
  604. struct msm_gem_address_space *aspace = NULL;
  605. int ret, mode;
  606. bool secure = false;
  607. if (!plane || !pstate || !pipe_cfg || !fb) {
  608. SDE_ERROR(
  609. "invalid arg(s), plane %d state %d cfg %d fb %d\n",
  610. !plane, !pstate, !pipe_cfg, !fb);
  611. return;
  612. }
  613. psde = to_sde_plane(plane);
  614. if (!psde->pipe_hw) {
  615. SDE_ERROR_PLANE(psde, "invalid pipe_hw\n");
  616. return;
  617. }
  618. ret = _sde_plane_get_aspace(psde, pstate, &aspace);
  619. if (ret) {
  620. SDE_ERROR_PLANE(psde, "Failed to get aspace %d\n", ret);
  621. return;
  622. }
  623. /*
  624. * framebuffer prepare is deferred for prepare_fb calls that
  625. * happen during the transition from secure to non-secure.
  626. * Handle the prepare at this point for such cases. This can be
  627. * expected for one or two frames during the transition.
  628. */
  629. if (aspace && pstate->defer_prepare_fb) {
  630. SDE_EVT32(DRMID(plane), psde->pipe, aspace->domain_attached);
  631. ret = msm_framebuffer_prepare(fb, pstate->aspace);
  632. if (ret) {
  633. SDE_ERROR_PLANE(psde,
  634. "failed to prepare framebuffer %d\n", ret);
  635. return;
  636. }
  637. pstate->defer_prepare_fb = false;
  638. }
  639. mode = sde_plane_get_property(pstate, PLANE_PROP_FB_TRANSLATION_MODE);
  640. if ((mode == SDE_DRM_FB_SEC) || (mode == SDE_DRM_FB_SEC_DIR_TRANS))
  641. secure = true;
  642. ret = sde_format_populate_layout(aspace, fb, &pipe_cfg->layout);
  643. if (ret == -EAGAIN)
  644. SDE_DEBUG_PLANE(psde, "not updating same src addrs\n");
  645. else if (ret) {
  646. SDE_ERROR_PLANE(psde, "failed to get format layout, %d\n", ret);
  647. /*
  648. * Force solid fill color on error. This is to prevent
  649. * smmu faults during secure session transition.
  650. */
  651. psde->is_error = true;
  652. } else if (psde->pipe_hw->ops.setup_sourceaddress) {
  653. SDE_EVT32_VERBOSE(psde->pipe_hw->idx,
  654. pipe_cfg->layout.width,
  655. pipe_cfg->layout.height,
  656. pipe_cfg->layout.plane_addr[0],
  657. pipe_cfg->layout.plane_size[0],
  658. pipe_cfg->layout.plane_addr[1],
  659. pipe_cfg->layout.plane_size[1],
  660. pipe_cfg->layout.plane_addr[2],
  661. pipe_cfg->layout.plane_size[2],
  662. pipe_cfg->layout.plane_addr[3],
  663. pipe_cfg->layout.plane_size[3],
  664. pstate->multirect_index,
  665. secure);
  666. psde->pipe_hw->ops.setup_sourceaddress(psde->pipe_hw, pipe_cfg,
  667. pstate->multirect_index);
  668. }
  669. }
  670. static int _sde_plane_setup_scaler3_lut(struct sde_plane *psde,
  671. struct sde_plane_state *pstate)
  672. {
  673. struct sde_hw_scaler3_cfg *cfg;
  674. int ret = 0;
  675. if (!psde || !pstate) {
  676. SDE_ERROR("invalid args\n");
  677. return -EINVAL;
  678. }
  679. cfg = &pstate->scaler3_cfg;
  680. cfg->dir_lut = msm_property_get_blob(
  681. &psde->property_info,
  682. &pstate->property_state, &cfg->dir_len,
  683. PLANE_PROP_SCALER_LUT_ED);
  684. cfg->cir_lut = msm_property_get_blob(
  685. &psde->property_info,
  686. &pstate->property_state, &cfg->cir_len,
  687. PLANE_PROP_SCALER_LUT_CIR);
  688. cfg->sep_lut = msm_property_get_blob(
  689. &psde->property_info,
  690. &pstate->property_state, &cfg->sep_len,
  691. PLANE_PROP_SCALER_LUT_SEP);
  692. if (!cfg->dir_lut || !cfg->cir_lut || !cfg->sep_lut)
  693. ret = -ENODATA;
  694. return ret;
  695. }
  696. static int _sde_plane_setup_scaler3lite_lut(struct sde_plane *psde,
  697. struct sde_plane_state *pstate)
  698. {
  699. struct sde_hw_scaler3_cfg *cfg;
  700. cfg = &pstate->scaler3_cfg;
  701. cfg->sep_lut = msm_property_get_blob(
  702. &psde->property_info,
  703. &pstate->property_state, &cfg->sep_len,
  704. PLANE_PROP_SCALER_LUT_SEP);
  705. return cfg->sep_lut ? 0 : -ENODATA;
  706. }
  707. static void _sde_plane_setup_scaler3(struct sde_plane *psde,
  708. struct sde_plane_state *pstate, const struct sde_format *fmt,
  709. uint32_t chroma_subsmpl_h, uint32_t chroma_subsmpl_v)
  710. {
  711. uint32_t decimated, i, src_w, src_h, dst_w, dst_h, src_h_pre_down;
  712. struct sde_hw_scaler3_cfg *scale_cfg;
  713. bool pre_down_supported = (psde->features & BIT(SDE_SSPP_PREDOWNSCALE));
  714. bool inline_rotation = (pstate->rotation & DRM_MODE_ROTATE_90);
  715. if (!psde || !pstate || !fmt ||
  716. !chroma_subsmpl_h || !chroma_subsmpl_v) {
  717. SDE_ERROR("psde %d pstate %d fmt %d smp_h %d smp_v %d\n",
  718. !!psde, !!pstate, !!fmt, chroma_subsmpl_h,
  719. chroma_subsmpl_v);
  720. return;
  721. }
  722. scale_cfg = &pstate->scaler3_cfg;
  723. src_w = psde->pipe_cfg.src_rect.w;
  724. src_h = psde->pipe_cfg.src_rect.h;
  725. dst_w = psde->pipe_cfg.dst_rect.w;
  726. dst_h = psde->pipe_cfg.dst_rect.h;
  727. memset(scale_cfg, 0, sizeof(*scale_cfg));
  728. memset(&pstate->pixel_ext, 0, sizeof(struct sde_hw_pixel_ext));
  729. /*
  730. * For inline rotation cases, scaler config is post-rotation,
  731. * so swap the dimensions here. However, pixel extension will
  732. * need pre-rotation settings, this will be corrected below
  733. * when calculating pixel extension settings.
  734. */
  735. if (inline_rotation)
  736. swap(src_w, src_h);
  737. decimated = DECIMATED_DIMENSION(src_w,
  738. psde->pipe_cfg.horz_decimation);
  739. scale_cfg->phase_step_x[SDE_SSPP_COMP_0] =
  740. mult_frac((1 << PHASE_STEP_SHIFT), decimated, dst_w);
  741. decimated = DECIMATED_DIMENSION(src_h,
  742. psde->pipe_cfg.vert_decimation);
  743. scale_cfg->phase_step_y[SDE_SSPP_COMP_0] =
  744. mult_frac((1 << PHASE_STEP_SHIFT), decimated, dst_h);
  745. scale_cfg->phase_step_y[SDE_SSPP_COMP_1_2] =
  746. scale_cfg->phase_step_y[SDE_SSPP_COMP_0] / chroma_subsmpl_v;
  747. scale_cfg->phase_step_x[SDE_SSPP_COMP_1_2] =
  748. scale_cfg->phase_step_x[SDE_SSPP_COMP_0] / chroma_subsmpl_h;
  749. scale_cfg->phase_step_x[SDE_SSPP_COMP_2] =
  750. scale_cfg->phase_step_x[SDE_SSPP_COMP_1_2];
  751. scale_cfg->phase_step_y[SDE_SSPP_COMP_2] =
  752. scale_cfg->phase_step_y[SDE_SSPP_COMP_1_2];
  753. scale_cfg->phase_step_x[SDE_SSPP_COMP_3] =
  754. scale_cfg->phase_step_x[SDE_SSPP_COMP_0];
  755. scale_cfg->phase_step_y[SDE_SSPP_COMP_3] =
  756. scale_cfg->phase_step_y[SDE_SSPP_COMP_0];
  757. for (i = 0; i < SDE_MAX_PLANES; i++) {
  758. /*
  759. * For inline rotation cases with pre-downscaling enabled
  760. * set x pre-downscale value if required. Only x direction
  761. * is currently supported. Use src_h as values have been swapped
  762. * and x direction corresponds to height value.
  763. */
  764. src_h_pre_down = src_h;
  765. if (pre_down_supported && inline_rotation) {
  766. if (i == 0 && (src_h > mult_frac(dst_h, 11, 5)))
  767. src_h_pre_down = src_h / 2;
  768. }
  769. scale_cfg->src_width[i] = DECIMATED_DIMENSION(src_w,
  770. psde->pipe_cfg.horz_decimation);
  771. scale_cfg->src_height[i] = DECIMATED_DIMENSION(src_h_pre_down,
  772. psde->pipe_cfg.vert_decimation);
  773. if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2) {
  774. scale_cfg->src_width[i] /= chroma_subsmpl_h;
  775. scale_cfg->src_height[i] /= chroma_subsmpl_v;
  776. }
  777. scale_cfg->preload_x[i] = psde->pipe_sblk->scaler_blk.h_preload;
  778. scale_cfg->preload_y[i] = psde->pipe_sblk->scaler_blk.v_preload;
  779. /* For pixel extension we need the pre-rotated orientation */
  780. if (inline_rotation) {
  781. pstate->pixel_ext.num_ext_pxls_top[i] =
  782. scale_cfg->src_width[i];
  783. pstate->pixel_ext.num_ext_pxls_left[i] =
  784. scale_cfg->src_height[i];
  785. } else {
  786. pstate->pixel_ext.num_ext_pxls_top[i] =
  787. scale_cfg->src_height[i];
  788. pstate->pixel_ext.num_ext_pxls_left[i] =
  789. scale_cfg->src_width[i];
  790. }
  791. }
  792. if ((!(SDE_FORMAT_IS_YUV(fmt)) && (src_h == dst_h)
  793. && (src_w == dst_w) && !inline_rotation) ||
  794. pstate->multirect_mode)
  795. return;
  796. SDE_DEBUG_PLANE(psde,
  797. "setting bilinear: src:%dx%d dst:%dx%d chroma:%dx%d fmt:%x\n",
  798. src_w, src_h, dst_w, dst_h,
  799. chroma_subsmpl_v, chroma_subsmpl_h,
  800. fmt->base.pixel_format);
  801. scale_cfg->dst_width = dst_w;
  802. scale_cfg->dst_height = dst_h;
  803. scale_cfg->y_rgb_filter_cfg = SDE_SCALE_BIL;
  804. scale_cfg->uv_filter_cfg = SDE_SCALE_BIL;
  805. scale_cfg->alpha_filter_cfg = SDE_SCALE_ALPHA_BIL;
  806. scale_cfg->lut_flag = 0;
  807. scale_cfg->blend_cfg = 1;
  808. scale_cfg->enable = 1;
  809. scale_cfg->dyn_exp_disabled = SDE_QSEED_DEFAULT_DYN_EXP;
  810. }
  811. /**
  812. * _sde_plane_setup_scaler2 - determine default scaler phase steps/filter type
  813. * @psde: Pointer to SDE plane object
  814. * @src: Source size
  815. * @dst: Destination size
  816. * @phase_steps: Pointer to output array for phase steps
  817. * @filter: Pointer to output array for filter type
  818. * @fmt: Pointer to format definition
  819. * @chroma_subsampling: Subsampling amount for chroma channel
  820. *
  821. * Returns: 0 on success
  822. */
  823. static int _sde_plane_setup_scaler2(struct sde_plane *psde,
  824. uint32_t src, uint32_t dst, uint32_t *phase_steps,
  825. enum sde_hw_filter *filter, const struct sde_format *fmt,
  826. uint32_t chroma_subsampling)
  827. {
  828. if (!psde || !phase_steps || !filter || !fmt) {
  829. SDE_ERROR(
  830. "invalid arg(s), plane %d phase %d filter %d fmt %d\n",
  831. !psde, !phase_steps, !filter, !fmt);
  832. return -EINVAL;
  833. }
  834. /* calculate phase steps, leave init phase as zero */
  835. phase_steps[SDE_SSPP_COMP_0] =
  836. mult_frac(1 << PHASE_STEP_SHIFT, src, dst);
  837. phase_steps[SDE_SSPP_COMP_1_2] =
  838. phase_steps[SDE_SSPP_COMP_0] / chroma_subsampling;
  839. phase_steps[SDE_SSPP_COMP_2] = phase_steps[SDE_SSPP_COMP_1_2];
  840. phase_steps[SDE_SSPP_COMP_3] = phase_steps[SDE_SSPP_COMP_0];
  841. /* calculate scaler config, if necessary */
  842. if (SDE_FORMAT_IS_YUV(fmt) || src != dst) {
  843. filter[SDE_SSPP_COMP_3] =
  844. (src <= dst) ? SDE_SCALE_FILTER_BIL :
  845. SDE_SCALE_FILTER_PCMN;
  846. if (SDE_FORMAT_IS_YUV(fmt)) {
  847. filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_CA;
  848. filter[SDE_SSPP_COMP_1_2] = filter[SDE_SSPP_COMP_3];
  849. } else {
  850. filter[SDE_SSPP_COMP_0] = filter[SDE_SSPP_COMP_3];
  851. filter[SDE_SSPP_COMP_1_2] =
  852. SDE_SCALE_FILTER_NEAREST;
  853. }
  854. } else {
  855. /* disable scaler */
  856. filter[SDE_SSPP_COMP_0] = SDE_SCALE_FILTER_MAX;
  857. filter[SDE_SSPP_COMP_1_2] = SDE_SCALE_FILTER_MAX;
  858. filter[SDE_SSPP_COMP_3] = SDE_SCALE_FILTER_MAX;
  859. }
  860. return 0;
  861. }
  862. /**
  863. * _sde_plane_setup_pixel_ext - determine default pixel extension values
  864. * @psde: Pointer to SDE plane object
  865. * @src: Source size
  866. * @dst: Destination size
  867. * @decimated_src: Source size after decimation, if any
  868. * @phase_steps: Pointer to output array for phase steps
  869. * @out_src: Output array for pixel extension values
  870. * @out_edge1: Output array for pixel extension first edge
  871. * @out_edge2: Output array for pixel extension second edge
  872. * @filter: Pointer to array for filter type
  873. * @fmt: Pointer to format definition
  874. * @chroma_subsampling: Subsampling amount for chroma channel
  875. * @post_compare: Whether to chroma subsampled source size for comparisions
  876. */
  877. static void _sde_plane_setup_pixel_ext(struct sde_plane *psde,
  878. uint32_t src, uint32_t dst, uint32_t decimated_src,
  879. uint32_t *phase_steps, uint32_t *out_src, int *out_edge1,
  880. int *out_edge2, enum sde_hw_filter *filter,
  881. const struct sde_format *fmt, uint32_t chroma_subsampling,
  882. bool post_compare)
  883. {
  884. int64_t edge1, edge2, caf;
  885. uint32_t src_work;
  886. int i, tmp;
  887. if (psde && phase_steps && out_src && out_edge1 &&
  888. out_edge2 && filter && fmt) {
  889. /* handle CAF for YUV formats */
  890. if (SDE_FORMAT_IS_YUV(fmt) && *filter == SDE_SCALE_FILTER_CA)
  891. caf = PHASE_STEP_UNIT_SCALE;
  892. else
  893. caf = 0;
  894. for (i = 0; i < SDE_MAX_PLANES; i++) {
  895. src_work = decimated_src;
  896. if (i == SDE_SSPP_COMP_1_2 || i == SDE_SSPP_COMP_2)
  897. src_work /= chroma_subsampling;
  898. if (post_compare)
  899. src = src_work;
  900. if (!SDE_FORMAT_IS_YUV(fmt) && (src == dst)) {
  901. /* unity */
  902. edge1 = 0;
  903. edge2 = 0;
  904. } else if (dst >= src) {
  905. /* upscale */
  906. edge1 = (1 << PHASE_RESIDUAL);
  907. edge1 -= caf;
  908. edge2 = (1 << PHASE_RESIDUAL);
  909. edge2 += (dst - 1) * *(phase_steps + i);
  910. edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
  911. edge2 += caf;
  912. edge2 = -(edge2);
  913. } else {
  914. /* downscale */
  915. edge1 = 0;
  916. edge2 = (dst - 1) * *(phase_steps + i);
  917. edge2 -= (src_work - 1) * PHASE_STEP_UNIT_SCALE;
  918. edge2 += *(phase_steps + i);
  919. edge2 = -(edge2);
  920. }
  921. /* only enable CAF for luma plane */
  922. caf = 0;
  923. /* populate output arrays */
  924. *(out_src + i) = src_work;
  925. /* edge updates taken from __pxl_extn_helper */
  926. if (edge1 >= 0) {
  927. tmp = (uint32_t)edge1;
  928. tmp >>= PHASE_STEP_SHIFT;
  929. *(out_edge1 + i) = -tmp;
  930. } else {
  931. tmp = (uint32_t)(-edge1);
  932. *(out_edge1 + i) =
  933. (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
  934. PHASE_STEP_SHIFT;
  935. }
  936. if (edge2 >= 0) {
  937. tmp = (uint32_t)edge2;
  938. tmp >>= PHASE_STEP_SHIFT;
  939. *(out_edge2 + i) = -tmp;
  940. } else {
  941. tmp = (uint32_t)(-edge2);
  942. *(out_edge2 + i) =
  943. (tmp + PHASE_STEP_UNIT_SCALE - 1) >>
  944. PHASE_STEP_SHIFT;
  945. }
  946. }
  947. }
  948. }
  949. static inline void _sde_plane_setup_csc(struct sde_plane *psde)
  950. {
  951. static const struct sde_csc_cfg sde_csc_YUV2RGB_601L = {
  952. {
  953. /* S15.16 format */
  954. 0x00012A00, 0x00000000, 0x00019880,
  955. 0x00012A00, 0xFFFF9B80, 0xFFFF3000,
  956. 0x00012A00, 0x00020480, 0x00000000,
  957. },
  958. /* signed bias */
  959. { 0xfff0, 0xff80, 0xff80,},
  960. { 0x0, 0x0, 0x0,},
  961. /* unsigned clamp */
  962. { 0x10, 0xeb, 0x10, 0xf0, 0x10, 0xf0,},
  963. { 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,},
  964. };
  965. static const struct sde_csc_cfg sde_csc10_YUV2RGB_601L = {
  966. {
  967. /* S15.16 format */
  968. 0x00012A00, 0x00000000, 0x00019880,
  969. 0x00012A00, 0xFFFF9B80, 0xFFFF3000,
  970. 0x00012A00, 0x00020480, 0x00000000,
  971. },
  972. /* signed bias */
  973. { 0xffc0, 0xfe00, 0xfe00,},
  974. { 0x0, 0x0, 0x0,},
  975. /* unsigned clamp */
  976. { 0x40, 0x3ac, 0x40, 0x3c0, 0x40, 0x3c0,},
  977. { 0x00, 0x3ff, 0x00, 0x3ff, 0x00, 0x3ff,},
  978. };
  979. if (!psde) {
  980. SDE_ERROR("invalid plane\n");
  981. return;
  982. }
  983. /* revert to kernel default if override not available */
  984. if (psde->csc_usr_ptr)
  985. psde->csc_ptr = psde->csc_usr_ptr;
  986. else if (BIT(SDE_SSPP_CSC_10BIT) & psde->features)
  987. psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc10_YUV2RGB_601L;
  988. else
  989. psde->csc_ptr = (struct sde_csc_cfg *)&sde_csc_YUV2RGB_601L;
  990. SDE_DEBUG_PLANE(psde, "using 0x%X 0x%X 0x%X...\n",
  991. psde->csc_ptr->csc_mv[0],
  992. psde->csc_ptr->csc_mv[1],
  993. psde->csc_ptr->csc_mv[2]);
  994. }
  995. static void sde_color_process_plane_setup(struct drm_plane *plane)
  996. {
  997. struct sde_plane *psde;
  998. struct sde_plane_state *pstate;
  999. uint32_t hue, saturation, value, contrast;
  1000. struct drm_msm_memcol *memcol = NULL;
  1001. struct drm_msm_3d_gamut *vig_gamut = NULL;
  1002. struct drm_msm_igc_lut *igc = NULL;
  1003. struct drm_msm_pgc_lut *gc = NULL;
  1004. size_t memcol_sz = 0, size = 0;
  1005. struct sde_hw_cp_cfg hw_cfg = {};
  1006. struct sde_hw_ctl *ctl = _sde_plane_get_hw_ctl(plane);
  1007. psde = to_sde_plane(plane);
  1008. pstate = to_sde_plane_state(plane->state);
  1009. hue = (uint32_t) sde_plane_get_property(pstate, PLANE_PROP_HUE_ADJUST);
  1010. if (psde->pipe_hw->ops.setup_pa_hue)
  1011. psde->pipe_hw->ops.setup_pa_hue(psde->pipe_hw, &hue);
  1012. saturation = (uint32_t) sde_plane_get_property(pstate,
  1013. PLANE_PROP_SATURATION_ADJUST);
  1014. if (psde->pipe_hw->ops.setup_pa_sat)
  1015. psde->pipe_hw->ops.setup_pa_sat(psde->pipe_hw, &saturation);
  1016. value = (uint32_t) sde_plane_get_property(pstate,
  1017. PLANE_PROP_VALUE_ADJUST);
  1018. if (psde->pipe_hw->ops.setup_pa_val)
  1019. psde->pipe_hw->ops.setup_pa_val(psde->pipe_hw, &value);
  1020. contrast = (uint32_t) sde_plane_get_property(pstate,
  1021. PLANE_PROP_CONTRAST_ADJUST);
  1022. if (psde->pipe_hw->ops.setup_pa_cont)
  1023. psde->pipe_hw->ops.setup_pa_cont(psde->pipe_hw, &contrast);
  1024. if (psde->pipe_hw->ops.setup_pa_memcolor) {
  1025. /* Skin memory color setup */
  1026. memcol = msm_property_get_blob(&psde->property_info,
  1027. &pstate->property_state,
  1028. &memcol_sz,
  1029. PLANE_PROP_SKIN_COLOR);
  1030. psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
  1031. MEMCOLOR_SKIN, memcol);
  1032. /* Sky memory color setup */
  1033. memcol = msm_property_get_blob(&psde->property_info,
  1034. &pstate->property_state,
  1035. &memcol_sz,
  1036. PLANE_PROP_SKY_COLOR);
  1037. psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
  1038. MEMCOLOR_SKY, memcol);
  1039. /* Foliage memory color setup */
  1040. memcol = msm_property_get_blob(&psde->property_info,
  1041. &pstate->property_state,
  1042. &memcol_sz,
  1043. PLANE_PROP_FOLIAGE_COLOR);
  1044. psde->pipe_hw->ops.setup_pa_memcolor(psde->pipe_hw,
  1045. MEMCOLOR_FOLIAGE, memcol);
  1046. }
  1047. if (pstate->dirty & SDE_PLANE_DIRTY_VIG_GAMUT &&
  1048. psde->pipe_hw->ops.setup_vig_gamut) {
  1049. vig_gamut = msm_property_get_blob(&psde->property_info,
  1050. &pstate->property_state,
  1051. &size,
  1052. PLANE_PROP_VIG_GAMUT);
  1053. hw_cfg.last_feature = 0;
  1054. hw_cfg.ctl = ctl;
  1055. hw_cfg.len = sizeof(struct drm_msm_3d_gamut);
  1056. hw_cfg.payload = vig_gamut;
  1057. psde->pipe_hw->ops.setup_vig_gamut(psde->pipe_hw, &hw_cfg);
  1058. }
  1059. if (pstate->dirty & SDE_PLANE_DIRTY_VIG_IGC &&
  1060. psde->pipe_hw->ops.setup_vig_igc) {
  1061. igc = msm_property_get_blob(&psde->property_info,
  1062. &pstate->property_state,
  1063. &size,
  1064. PLANE_PROP_VIG_IGC);
  1065. hw_cfg.last_feature = 0;
  1066. hw_cfg.ctl = ctl;
  1067. hw_cfg.len = sizeof(struct drm_msm_igc_lut);
  1068. hw_cfg.payload = igc;
  1069. psde->pipe_hw->ops.setup_vig_igc(psde->pipe_hw, &hw_cfg);
  1070. }
  1071. if (pstate->dirty & SDE_PLANE_DIRTY_DMA_IGC &&
  1072. psde->pipe_hw->ops.setup_dma_igc) {
  1073. igc = msm_property_get_blob(&psde->property_info,
  1074. &pstate->property_state,
  1075. &size,
  1076. PLANE_PROP_DMA_IGC);
  1077. hw_cfg.last_feature = 0;
  1078. hw_cfg.ctl = ctl;
  1079. hw_cfg.len = sizeof(struct drm_msm_igc_lut);
  1080. hw_cfg.payload = igc;
  1081. psde->pipe_hw->ops.setup_dma_igc(psde->pipe_hw, &hw_cfg,
  1082. pstate->multirect_index);
  1083. }
  1084. if (pstate->dirty & SDE_PLANE_DIRTY_DMA_GC &&
  1085. psde->pipe_hw->ops.setup_dma_gc) {
  1086. gc = msm_property_get_blob(&psde->property_info,
  1087. &pstate->property_state,
  1088. &size,
  1089. PLANE_PROP_DMA_GC);
  1090. hw_cfg.last_feature = 0;
  1091. hw_cfg.ctl = ctl;
  1092. hw_cfg.len = sizeof(struct drm_msm_pgc_lut);
  1093. hw_cfg.payload = gc;
  1094. psde->pipe_hw->ops.setup_dma_gc(psde->pipe_hw, &hw_cfg,
  1095. pstate->multirect_index);
  1096. }
  1097. }
  1098. static void _sde_plane_setup_scaler(struct sde_plane *psde,
  1099. struct sde_plane_state *pstate,
  1100. const struct sde_format *fmt, bool color_fill)
  1101. {
  1102. struct sde_hw_pixel_ext *pe;
  1103. uint32_t chroma_subsmpl_h, chroma_subsmpl_v;
  1104. const struct drm_format_info *info = NULL;
  1105. if (!psde || !fmt || !pstate) {
  1106. SDE_ERROR("invalid arg(s), plane %d fmt %d state %d\n",
  1107. !psde, !fmt, !pstate);
  1108. return;
  1109. }
  1110. info = drm_format_info(fmt->base.pixel_format);
  1111. pe = &pstate->pixel_ext;
  1112. psde->pipe_cfg.horz_decimation =
  1113. sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
  1114. psde->pipe_cfg.vert_decimation =
  1115. sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
  1116. /* don't chroma subsample if decimating */
  1117. chroma_subsmpl_h = psde->pipe_cfg.horz_decimation ? 1 : info->hsub;
  1118. chroma_subsmpl_v = psde->pipe_cfg.vert_decimation ? 1 : info->vsub;
  1119. /* update scaler */
  1120. if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3) ||
  1121. (psde->features & BIT(SDE_SSPP_SCALER_QSEED3LITE))) {
  1122. int rc = -EINVAL;
  1123. if (!color_fill && !psde->debugfs_default_scale)
  1124. rc = is_qseed3_rev_qseed3lite(psde->pipe_hw->catalog) ?
  1125. _sde_plane_setup_scaler3lite_lut(psde, pstate) :
  1126. _sde_plane_setup_scaler3_lut(psde, pstate);
  1127. if (rc || pstate->scaler_check_state !=
  1128. SDE_PLANE_SCLCHECK_SCALER_V2) {
  1129. SDE_EVT32_VERBOSE(DRMID(&psde->base), color_fill,
  1130. pstate->scaler_check_state,
  1131. psde->debugfs_default_scale, rc,
  1132. psde->pipe_cfg.src_rect.w,
  1133. psde->pipe_cfg.src_rect.h,
  1134. psde->pipe_cfg.dst_rect.w,
  1135. psde->pipe_cfg.dst_rect.h,
  1136. pstate->multirect_mode);
  1137. /* calculate default config for QSEED3 */
  1138. _sde_plane_setup_scaler3(psde, pstate, fmt,
  1139. chroma_subsmpl_h, chroma_subsmpl_v);
  1140. }
  1141. } else if (pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V1 ||
  1142. color_fill || psde->debugfs_default_scale) {
  1143. uint32_t deci_dim, i;
  1144. /* calculate default configuration for QSEED2 */
  1145. memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
  1146. SDE_DEBUG_PLANE(psde, "default config\n");
  1147. deci_dim = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.w,
  1148. psde->pipe_cfg.horz_decimation);
  1149. _sde_plane_setup_scaler2(psde,
  1150. deci_dim,
  1151. psde->pipe_cfg.dst_rect.w,
  1152. pe->phase_step_x,
  1153. pe->horz_filter, fmt, chroma_subsmpl_h);
  1154. if (SDE_FORMAT_IS_YUV(fmt))
  1155. deci_dim &= ~0x1;
  1156. _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.w,
  1157. psde->pipe_cfg.dst_rect.w, deci_dim,
  1158. pe->phase_step_x,
  1159. pe->roi_w,
  1160. pe->num_ext_pxls_left,
  1161. pe->num_ext_pxls_right, pe->horz_filter, fmt,
  1162. chroma_subsmpl_h, 0);
  1163. deci_dim = DECIMATED_DIMENSION(psde->pipe_cfg.src_rect.h,
  1164. psde->pipe_cfg.vert_decimation);
  1165. _sde_plane_setup_scaler2(psde,
  1166. deci_dim,
  1167. psde->pipe_cfg.dst_rect.h,
  1168. pe->phase_step_y,
  1169. pe->vert_filter, fmt, chroma_subsmpl_v);
  1170. _sde_plane_setup_pixel_ext(psde, psde->pipe_cfg.src_rect.h,
  1171. psde->pipe_cfg.dst_rect.h, deci_dim,
  1172. pe->phase_step_y,
  1173. pe->roi_h,
  1174. pe->num_ext_pxls_top,
  1175. pe->num_ext_pxls_btm, pe->vert_filter, fmt,
  1176. chroma_subsmpl_v, 1);
  1177. for (i = 0; i < SDE_MAX_PLANES; i++) {
  1178. if (pe->num_ext_pxls_left[i] >= 0)
  1179. pe->left_rpt[i] = pe->num_ext_pxls_left[i];
  1180. else
  1181. pe->left_ftch[i] = pe->num_ext_pxls_left[i];
  1182. if (pe->num_ext_pxls_right[i] >= 0)
  1183. pe->right_rpt[i] = pe->num_ext_pxls_right[i];
  1184. else
  1185. pe->right_ftch[i] = pe->num_ext_pxls_right[i];
  1186. if (pe->num_ext_pxls_top[i] >= 0)
  1187. pe->top_rpt[i] = pe->num_ext_pxls_top[i];
  1188. else
  1189. pe->top_ftch[i] = pe->num_ext_pxls_top[i];
  1190. if (pe->num_ext_pxls_btm[i] >= 0)
  1191. pe->btm_rpt[i] = pe->num_ext_pxls_btm[i];
  1192. else
  1193. pe->btm_ftch[i] = pe->num_ext_pxls_btm[i];
  1194. }
  1195. }
  1196. if (psde->pipe_hw->ops.setup_pre_downscale)
  1197. psde->pipe_hw->ops.setup_pre_downscale(psde->pipe_hw,
  1198. &pstate->pre_down);
  1199. }
  1200. /**
  1201. * _sde_plane_color_fill - enables color fill on plane
  1202. * @psde: Pointer to SDE plane object
  1203. * @color: RGB fill color value, [23..16] Blue, [15..8] Green, [7..0] Red
  1204. * @alpha: 8-bit fill alpha value, 255 selects 100% alpha
  1205. * Returns: 0 on success
  1206. */
  1207. static int _sde_plane_color_fill(struct sde_plane *psde,
  1208. uint32_t color, uint32_t alpha)
  1209. {
  1210. const struct sde_format *fmt;
  1211. const struct drm_plane *plane;
  1212. struct sde_plane_state *pstate;
  1213. bool blend_enable = true;
  1214. if (!psde || !psde->base.state) {
  1215. SDE_ERROR("invalid plane\n");
  1216. return -EINVAL;
  1217. }
  1218. if (!psde->pipe_hw) {
  1219. SDE_ERROR_PLANE(psde, "invalid plane h/w pointer\n");
  1220. return -EINVAL;
  1221. }
  1222. plane = &psde->base;
  1223. pstate = to_sde_plane_state(plane->state);
  1224. SDE_DEBUG_PLANE(psde, "\n");
  1225. /*
  1226. * select fill format to match user property expectation,
  1227. * h/w only supports RGB variants
  1228. */
  1229. fmt = sde_get_sde_format(DRM_FORMAT_ABGR8888);
  1230. blend_enable = (SDE_DRM_BLEND_OP_OPAQUE !=
  1231. sde_plane_get_property(pstate, PLANE_PROP_BLEND_OP));
  1232. /* update sspp */
  1233. if (fmt && psde->pipe_hw->ops.setup_solidfill) {
  1234. psde->pipe_hw->ops.setup_solidfill(psde->pipe_hw,
  1235. (color & 0xFFFFFF) | ((alpha & 0xFF) << 24),
  1236. pstate->multirect_index);
  1237. /* override scaler/decimation if solid fill */
  1238. psde->pipe_cfg.src_rect.x = 0;
  1239. psde->pipe_cfg.src_rect.y = 0;
  1240. psde->pipe_cfg.src_rect.w = psde->pipe_cfg.dst_rect.w;
  1241. psde->pipe_cfg.src_rect.h = psde->pipe_cfg.dst_rect.h;
  1242. _sde_plane_setup_scaler(psde, pstate, fmt, true);
  1243. if (psde->pipe_hw->ops.setup_format)
  1244. psde->pipe_hw->ops.setup_format(psde->pipe_hw,
  1245. fmt, blend_enable,
  1246. SDE_SSPP_SOLID_FILL,
  1247. pstate->multirect_index);
  1248. if (psde->pipe_hw->ops.setup_rects)
  1249. psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
  1250. &psde->pipe_cfg,
  1251. pstate->multirect_index);
  1252. if (psde->pipe_hw->ops.setup_pe)
  1253. psde->pipe_hw->ops.setup_pe(psde->pipe_hw,
  1254. &pstate->pixel_ext);
  1255. if (psde->pipe_hw->ops.setup_scaler &&
  1256. pstate->multirect_index != SDE_SSPP_RECT_1) {
  1257. psde->pipe_hw->ctl = _sde_plane_get_hw_ctl(plane);
  1258. psde->pipe_hw->ops.setup_scaler(psde->pipe_hw,
  1259. &psde->pipe_cfg, &pstate->pixel_ext,
  1260. &pstate->scaler3_cfg);
  1261. }
  1262. }
  1263. return 0;
  1264. }
  1265. /**
  1266. * sde_plane_rot_atomic_check - verify rotator update of the given state
  1267. * @plane: Pointer to drm plane
  1268. * @state: Pointer to drm plane state to be validated
  1269. * return: 0 if success; error code otherwise
  1270. */
  1271. static int sde_plane_rot_atomic_check(struct drm_plane *plane,
  1272. struct drm_plane_state *state)
  1273. {
  1274. struct sde_plane *psde;
  1275. struct sde_plane_state *pstate, *old_pstate;
  1276. int ret = 0;
  1277. u32 rotation;
  1278. if (!plane || !state) {
  1279. SDE_ERROR("invalid plane/state\n");
  1280. return -EINVAL;
  1281. }
  1282. psde = to_sde_plane(plane);
  1283. pstate = to_sde_plane_state(state);
  1284. old_pstate = to_sde_plane_state(plane->state);
  1285. /* check inline rotation and simplify the transform */
  1286. rotation = drm_rotation_simplify(
  1287. state->rotation,
  1288. DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
  1289. DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y);
  1290. if ((rotation & DRM_MODE_ROTATE_180) ||
  1291. (rotation & DRM_MODE_ROTATE_270)) {
  1292. SDE_ERROR_PLANE(psde,
  1293. "invalid rotation transform must be simplified 0x%x\n",
  1294. rotation);
  1295. ret = -EINVAL;
  1296. goto exit;
  1297. }
  1298. if (rotation & DRM_MODE_ROTATE_90) {
  1299. struct msm_drm_private *priv = plane->dev->dev_private;
  1300. struct sde_kms *sde_kms;
  1301. const struct msm_format *msm_fmt;
  1302. const struct sde_format *fmt;
  1303. struct sde_rect src;
  1304. bool q16_data = true;
  1305. POPULATE_RECT(&src, state->src_x, state->src_y,
  1306. state->src_w, state->src_h, q16_data);
  1307. /*
  1308. * DRM framework expects rotation flag in counter-clockwise
  1309. * direction and the HW expects in clockwise direction.
  1310. * Flip the flags to match with HW.
  1311. */
  1312. rotation ^= (DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y);
  1313. if (!psde->pipe_sblk->in_rot_maxdwnscale_rt_num ||
  1314. !psde->pipe_sblk->in_rot_maxdwnscale_rt_denom ||
  1315. !psde->pipe_sblk->in_rot_maxdwnscale_nrt ||
  1316. !psde->pipe_sblk->in_rot_maxheight ||
  1317. !psde->pipe_sblk->in_rot_format_list ||
  1318. !(psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT))) {
  1319. SDE_ERROR_PLANE(psde,
  1320. "wrong config rt:%d/%d nrt:%d fmt:%d h:%d 0x%x\n",
  1321. !psde->pipe_sblk->in_rot_maxdwnscale_rt_num,
  1322. !psde->pipe_sblk->in_rot_maxdwnscale_rt_denom,
  1323. !psde->pipe_sblk->in_rot_maxdwnscale_nrt,
  1324. !psde->pipe_sblk->in_rot_format_list,
  1325. !psde->pipe_sblk->in_rot_maxheight,
  1326. psde->features);
  1327. ret = -EINVAL;
  1328. goto exit;
  1329. }
  1330. /* check for valid height */
  1331. if (src.h > psde->pipe_sblk->in_rot_maxheight) {
  1332. SDE_ERROR_PLANE(psde,
  1333. "invalid height for inline rot:%d max:%d\n",
  1334. src.h, psde->pipe_sblk->in_rot_maxheight);
  1335. ret = -EINVAL;
  1336. goto exit;
  1337. }
  1338. if (!sde_plane_enabled(state))
  1339. goto exit;
  1340. /* check for valid formats supported by inline rot */
  1341. sde_kms = to_sde_kms(priv->kms);
  1342. msm_fmt = msm_framebuffer_format(state->fb);
  1343. fmt = to_sde_format(msm_fmt);
  1344. ret = sde_format_validate_fmt(&sde_kms->base, fmt,
  1345. psde->pipe_sblk->in_rot_format_list);
  1346. }
  1347. exit:
  1348. pstate->rotation = rotation;
  1349. return ret;
  1350. }
  1351. static bool _sde_plane_halt_requests(struct drm_plane *plane,
  1352. uint32_t xin_id, bool halt_forced_clk, bool enable)
  1353. {
  1354. struct sde_plane *psde;
  1355. struct msm_drm_private *priv;
  1356. struct sde_vbif_set_xin_halt_params halt_params;
  1357. if (!plane || !plane->dev) {
  1358. SDE_ERROR("invalid arguments\n");
  1359. return false;
  1360. }
  1361. psde = to_sde_plane(plane);
  1362. if (!psde->pipe_hw || !psde->pipe_hw->cap) {
  1363. SDE_ERROR("invalid pipe reference\n");
  1364. return false;
  1365. }
  1366. priv = plane->dev->dev_private;
  1367. if (!priv || !priv->kms) {
  1368. SDE_ERROR("invalid KMS reference\n");
  1369. return false;
  1370. }
  1371. memset(&halt_params, 0, sizeof(halt_params));
  1372. halt_params.vbif_idx = VBIF_RT;
  1373. halt_params.xin_id = xin_id;
  1374. halt_params.clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  1375. halt_params.forced_on = halt_forced_clk;
  1376. halt_params.enable = enable;
  1377. return sde_vbif_set_xin_halt(to_sde_kms(priv->kms), &halt_params);
  1378. }
  1379. void sde_plane_halt_requests(struct drm_plane *plane, bool enable)
  1380. {
  1381. struct sde_plane *psde;
  1382. if (!plane) {
  1383. SDE_ERROR("invalid plane\n");
  1384. return;
  1385. }
  1386. psde = to_sde_plane(plane);
  1387. if (!psde->pipe_hw || !psde->pipe_hw->cap) {
  1388. SDE_ERROR("invalid pipe reference\n");
  1389. return;
  1390. }
  1391. SDE_EVT32(DRMID(plane), psde->xin_halt_forced_clk, enable);
  1392. psde->xin_halt_forced_clk =
  1393. _sde_plane_halt_requests(plane, psde->pipe_hw->cap->xin_id,
  1394. psde->xin_halt_forced_clk, enable);
  1395. }
  1396. void sde_plane_secure_ctrl_xin_client(struct drm_plane *plane,
  1397. struct drm_crtc *crtc)
  1398. {
  1399. struct sde_plane *psde;
  1400. if (!plane || !crtc) {
  1401. SDE_ERROR("invalid plane/crtc\n");
  1402. return;
  1403. }
  1404. psde = to_sde_plane(plane);
  1405. if (psde->features & BIT(SDE_SSPP_BLOCK_SEC_UI))
  1406. return;
  1407. /* do all VBIF programming for the sec-ui allowed SSPP */
  1408. _sde_plane_set_qos_remap(plane);
  1409. _sde_plane_set_ot_limit(plane, crtc);
  1410. }
  1411. /**
  1412. * sde_plane_rot_install_properties - install plane rotator properties
  1413. * @plane: Pointer to drm plane
  1414. * @catalog: Pointer to mdss configuration
  1415. * return: none
  1416. */
  1417. static void sde_plane_rot_install_properties(struct drm_plane *plane,
  1418. struct sde_mdss_cfg *catalog)
  1419. {
  1420. struct sde_plane *psde = to_sde_plane(plane);
  1421. unsigned long supported_rotations = DRM_MODE_ROTATE_0 |
  1422. DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y;
  1423. int ret = 0;
  1424. if (!plane || !psde) {
  1425. SDE_ERROR("invalid plane\n");
  1426. return;
  1427. } else if (!catalog) {
  1428. SDE_ERROR("invalid catalog\n");
  1429. return;
  1430. }
  1431. if (psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT))
  1432. supported_rotations |= DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
  1433. DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
  1434. ret = drm_plane_create_rotation_property(plane,
  1435. DRM_MODE_ROTATE_0, supported_rotations);
  1436. if (ret) {
  1437. DRM_ERROR("create rotation property failed: %d\n", ret);
  1438. return;
  1439. }
  1440. }
  1441. void sde_plane_clear_multirect(const struct drm_plane_state *drm_state)
  1442. {
  1443. struct sde_plane_state *pstate;
  1444. if (!drm_state)
  1445. return;
  1446. pstate = to_sde_plane_state(drm_state);
  1447. pstate->multirect_index = SDE_SSPP_RECT_SOLO;
  1448. pstate->multirect_mode = SDE_SSPP_MULTIRECT_NONE;
  1449. }
  1450. /**
  1451. * multi_rect validate API allows to validate only R0 and R1 RECT
  1452. * passing for each plane. Client of this API must not pass multiple
  1453. * plane which are not sharing same XIN client. Such calls will fail
  1454. * even though kernel client is passing valid multirect configuration.
  1455. */
  1456. int sde_plane_validate_multirect_v2(struct sde_multirect_plane_states *plane)
  1457. {
  1458. struct sde_plane_state *pstate[R_MAX];
  1459. const struct drm_plane_state *drm_state[R_MAX];
  1460. struct sde_rect src[R_MAX], dst[R_MAX];
  1461. struct sde_plane *sde_plane[R_MAX];
  1462. const struct sde_format *fmt[R_MAX];
  1463. int xin_id[R_MAX];
  1464. bool q16_data = true;
  1465. int i, j, buffer_lines, width_threshold[R_MAX];
  1466. unsigned int max_tile_height = 1;
  1467. bool parallel_fetch_qualified = true;
  1468. enum sde_sspp_multirect_mode mode = SDE_SSPP_MULTIRECT_NONE;
  1469. const struct msm_format *msm_fmt;
  1470. bool const_alpha_enable = true;
  1471. for (i = 0; i < R_MAX; i++) {
  1472. drm_state[i] = i ? plane->r1 : plane->r0;
  1473. if (!drm_state[i]) {
  1474. SDE_ERROR("drm plane state is NULL\n");
  1475. return -EINVAL;
  1476. }
  1477. pstate[i] = to_sde_plane_state(drm_state[i]);
  1478. sde_plane[i] = to_sde_plane(drm_state[i]->plane);
  1479. xin_id[i] = sde_plane[i]->pipe_hw->cap->xin_id;
  1480. for (j = 0; j < i; j++) {
  1481. if (xin_id[i] != xin_id[j]) {
  1482. SDE_ERROR_PLANE(sde_plane[i],
  1483. "invalid multirect validate call base:%d xin_id:%d curr:%d xin:%d\n",
  1484. j, xin_id[j], i, xin_id[i]);
  1485. return -EINVAL;
  1486. }
  1487. }
  1488. msm_fmt = msm_framebuffer_format(drm_state[i]->fb);
  1489. if (!msm_fmt) {
  1490. SDE_ERROR_PLANE(sde_plane[i], "null fb\n");
  1491. return -EINVAL;
  1492. }
  1493. fmt[i] = to_sde_format(msm_fmt);
  1494. if (SDE_FORMAT_IS_UBWC(fmt[i]) &&
  1495. (fmt[i]->tile_height > max_tile_height))
  1496. max_tile_height = fmt[i]->tile_height;
  1497. POPULATE_RECT(&src[i], drm_state[i]->src_x, drm_state[i]->src_y,
  1498. drm_state[i]->src_w, drm_state[i]->src_h, q16_data);
  1499. POPULATE_RECT(&dst[i], drm_state[i]->crtc_x,
  1500. drm_state[i]->crtc_y, drm_state[i]->crtc_w,
  1501. drm_state[i]->crtc_h, !q16_data);
  1502. if (src[i].w != dst[i].w || src[i].h != dst[i].h) {
  1503. SDE_ERROR_PLANE(sde_plane[i],
  1504. "scaling is not supported in multirect mode\n");
  1505. return -EINVAL;
  1506. }
  1507. if (pstate[i]->rotation & DRM_MODE_ROTATE_90) {
  1508. SDE_ERROR_PLANE(sde_plane[i],
  1509. "inline rotation is not supported in mulirect mode\n");
  1510. return -EINVAL;
  1511. }
  1512. if (SDE_FORMAT_IS_YUV(fmt[i])) {
  1513. SDE_ERROR_PLANE(sde_plane[i],
  1514. "Unsupported format for multirect mode\n");
  1515. return -EINVAL;
  1516. }
  1517. /**
  1518. * SSPP PD_MEM is split half - one for each RECT.
  1519. * Tiled formats need 5 lines of buffering while fetching
  1520. * whereas linear formats need only 2 lines.
  1521. * So we cannot support more than half of the supported SSPP
  1522. * width for tiled formats.
  1523. */
  1524. width_threshold[i] = sde_plane[i]->pipe_sblk->maxlinewidth;
  1525. if (SDE_FORMAT_IS_UBWC(fmt[i]))
  1526. width_threshold[i] /= 2;
  1527. if (parallel_fetch_qualified && src[i].w > width_threshold[i])
  1528. parallel_fetch_qualified = false;
  1529. if (sde_plane[i]->is_virtual)
  1530. mode = sde_plane_get_property(pstate[i],
  1531. PLANE_PROP_MULTIRECT_MODE);
  1532. if (pstate[i]->const_alpha_en != const_alpha_enable)
  1533. const_alpha_enable = false;
  1534. }
  1535. buffer_lines = 2 * max_tile_height;
  1536. /**
  1537. * fallback to driver mode selection logic if client is using
  1538. * multirect plane without setting property.
  1539. *
  1540. * validate multirect mode configuration based on rectangle
  1541. */
  1542. switch (mode) {
  1543. case SDE_SSPP_MULTIRECT_NONE:
  1544. if (parallel_fetch_qualified)
  1545. mode = SDE_SSPP_MULTIRECT_PARALLEL;
  1546. else if (TIME_MULTIPLEX_RECT(dst[R1], dst[R0], buffer_lines) ||
  1547. TIME_MULTIPLEX_RECT(dst[R0], dst[R1], buffer_lines))
  1548. mode = SDE_SSPP_MULTIRECT_TIME_MX;
  1549. else
  1550. SDE_ERROR(
  1551. "planes(%d - %d) multirect mode selection fail\n",
  1552. drm_state[R0]->plane->base.id,
  1553. drm_state[R1]->plane->base.id);
  1554. break;
  1555. case SDE_SSPP_MULTIRECT_PARALLEL:
  1556. if (!parallel_fetch_qualified) {
  1557. SDE_ERROR("R0 plane:%d width_threshold:%d src_w:%d\n",
  1558. drm_state[R0]->plane->base.id,
  1559. width_threshold[R0], src[R0].w);
  1560. SDE_ERROR("R1 plane:%d width_threshold:%d src_w:%d\n",
  1561. drm_state[R1]->plane->base.id,
  1562. width_threshold[R1], src[R1].w);
  1563. SDE_ERROR("parallel fetch not qualified\n");
  1564. mode = SDE_SSPP_MULTIRECT_NONE;
  1565. }
  1566. break;
  1567. case SDE_SSPP_MULTIRECT_TIME_MX:
  1568. if (!TIME_MULTIPLEX_RECT(dst[R1], dst[R0], buffer_lines) &&
  1569. !TIME_MULTIPLEX_RECT(dst[R0], dst[R1], buffer_lines)) {
  1570. SDE_ERROR(
  1571. "buffer_lines:%d R0 plane:%d dst_y:%d dst_h:%d\n",
  1572. buffer_lines, drm_state[R0]->plane->base.id,
  1573. dst[R0].y, dst[R0].h);
  1574. SDE_ERROR(
  1575. "buffer_lines:%d R1 plane:%d dst_y:%d dst_h:%d\n",
  1576. buffer_lines, drm_state[R1]->plane->base.id,
  1577. dst[R1].y, dst[R1].h);
  1578. SDE_ERROR("time multiplexed fetch not qualified\n");
  1579. mode = SDE_SSPP_MULTIRECT_NONE;
  1580. }
  1581. break;
  1582. default:
  1583. SDE_ERROR("bad mode:%d selection\n", mode);
  1584. mode = SDE_SSPP_MULTIRECT_NONE;
  1585. break;
  1586. }
  1587. for (i = 0; i < R_MAX; i++) {
  1588. pstate[i]->multirect_mode = mode;
  1589. pstate[i]->const_alpha_en = const_alpha_enable;
  1590. }
  1591. if (mode == SDE_SSPP_MULTIRECT_NONE)
  1592. return -EINVAL;
  1593. if (sde_plane[R0]->is_virtual) {
  1594. pstate[R0]->multirect_index = SDE_SSPP_RECT_1;
  1595. pstate[R1]->multirect_index = SDE_SSPP_RECT_0;
  1596. } else {
  1597. pstate[R0]->multirect_index = SDE_SSPP_RECT_0;
  1598. pstate[R1]->multirect_index = SDE_SSPP_RECT_1;
  1599. }
  1600. SDE_DEBUG_PLANE(sde_plane[R0], "R0: %d - %d\n",
  1601. pstate[R0]->multirect_mode, pstate[R0]->multirect_index);
  1602. SDE_DEBUG_PLANE(sde_plane[R1], "R1: %d - %d\n",
  1603. pstate[R1]->multirect_mode, pstate[R1]->multirect_index);
  1604. return 0;
  1605. }
  1606. /**
  1607. * sde_plane_ctl_flush - set/clear control flush bitmask for the given plane
  1608. * @plane: Pointer to drm plane structure
  1609. * @ctl: Pointer to hardware control driver
  1610. * @set: set if true else clear
  1611. */
  1612. void sde_plane_ctl_flush(struct drm_plane *plane, struct sde_hw_ctl *ctl,
  1613. bool set)
  1614. {
  1615. if (!plane || !ctl) {
  1616. SDE_ERROR("invalid parameters\n");
  1617. return;
  1618. }
  1619. if (!ctl->ops.update_bitmask_sspp) {
  1620. SDE_ERROR("invalid ops\n");
  1621. return;
  1622. }
  1623. ctl->ops.update_bitmask_sspp(ctl, sde_plane_pipe(plane), set);
  1624. }
  1625. static int sde_plane_prepare_fb(struct drm_plane *plane,
  1626. struct drm_plane_state *new_state)
  1627. {
  1628. struct drm_framebuffer *fb = new_state->fb;
  1629. struct sde_plane *psde = to_sde_plane(plane);
  1630. struct sde_plane_state *pstate = to_sde_plane_state(new_state);
  1631. struct sde_hw_fmt_layout layout;
  1632. struct msm_gem_address_space *aspace;
  1633. int ret;
  1634. if (!fb)
  1635. return 0;
  1636. SDE_DEBUG_PLANE(psde, "FB[%u]\n", fb->base.id);
  1637. ret = _sde_plane_get_aspace(psde, pstate, &aspace);
  1638. if (ret) {
  1639. SDE_ERROR_PLANE(psde, "Failed to get aspace\n");
  1640. return ret;
  1641. }
  1642. /* cache aspace */
  1643. pstate->aspace = aspace;
  1644. /*
  1645. * when transitioning from secure to non-secure,
  1646. * plane->prepare_fb happens before the commit. In such case,
  1647. * defer the prepare_fb and handled it late, during the commit
  1648. * after attaching the domains as part of the transition
  1649. */
  1650. pstate->defer_prepare_fb = (aspace && !aspace->domain_attached) ?
  1651. true : false;
  1652. if (pstate->defer_prepare_fb) {
  1653. SDE_EVT32(DRMID(plane), psde->pipe);
  1654. SDE_DEBUG_PLANE(psde,
  1655. "domain not attached, prepare_fb handled later\n");
  1656. return 0;
  1657. }
  1658. if (pstate->aspace && fb) {
  1659. ret = msm_framebuffer_prepare(fb,
  1660. pstate->aspace);
  1661. if (ret) {
  1662. SDE_ERROR("failed to prepare framebuffer\n");
  1663. return ret;
  1664. }
  1665. }
  1666. /* validate framebuffer layout before commit */
  1667. ret = sde_format_populate_layout(pstate->aspace,
  1668. fb, &layout);
  1669. if (ret) {
  1670. SDE_ERROR_PLANE(psde, "failed to get format layout, %d\n", ret);
  1671. return ret;
  1672. }
  1673. return 0;
  1674. }
  1675. /**
  1676. * _sde_plane_fetch_halt - halts vbif transactions for a plane
  1677. * @plane: Pointer to plane
  1678. * Returns: 0 on success
  1679. */
  1680. static int _sde_plane_fetch_halt(struct drm_plane *plane)
  1681. {
  1682. struct sde_plane *psde;
  1683. int xin_id;
  1684. enum sde_clk_ctrl_type clk_ctrl;
  1685. struct msm_drm_private *priv;
  1686. struct sde_kms *sde_kms;
  1687. psde = to_sde_plane(plane);
  1688. if (!plane || !plane->dev || !psde->pipe_hw) {
  1689. SDE_ERROR("invalid arguments\n");
  1690. return -EINVAL;
  1691. }
  1692. priv = plane->dev->dev_private;
  1693. if (!priv || !priv->kms) {
  1694. SDE_ERROR("invalid KMS reference\n");
  1695. return -EINVAL;
  1696. }
  1697. sde_kms = to_sde_kms(priv->kms);
  1698. clk_ctrl = psde->pipe_hw->cap->clk_ctrl;
  1699. xin_id = psde->pipe_hw->cap->xin_id;
  1700. SDE_DEBUG_PLANE(psde, "pipe:%d xin_id:%d clk_ctrl:%d\n",
  1701. psde->pipe - SSPP_VIG0, xin_id, clk_ctrl);
  1702. SDE_EVT32_VERBOSE(psde, psde->pipe - SSPP_VIG0, xin_id, clk_ctrl);
  1703. return sde_vbif_halt_plane_xin(sde_kms, xin_id, clk_ctrl);
  1704. }
  1705. static void sde_plane_cleanup_fb(struct drm_plane *plane,
  1706. struct drm_plane_state *old_state)
  1707. {
  1708. struct sde_plane *psde = to_sde_plane(plane);
  1709. struct sde_plane_state *old_pstate;
  1710. int ret;
  1711. if (!old_state || !old_state->fb || !plane || !plane->state)
  1712. return;
  1713. old_pstate = to_sde_plane_state(old_state);
  1714. SDE_DEBUG_PLANE(psde, "FB[%u]\n", old_state->fb->base.id);
  1715. /*
  1716. * plane->state gets populated for next frame after swap_state. If
  1717. * plane->state->crtc pointer is not populated then it is not used in
  1718. * the next frame, hence making it an unused plane.
  1719. */
  1720. if ((plane->state->crtc == NULL) && !psde->is_virtual) {
  1721. SDE_DEBUG_PLANE(psde, "unused pipe:%u\n",
  1722. psde->pipe - SSPP_VIG0);
  1723. /* halt this plane now */
  1724. ret = pm_runtime_get_sync(plane->dev->dev);
  1725. if (ret < 0) {
  1726. SDE_ERROR("power resource enable failed with %d", ret);
  1727. SDE_EVT32(ret, SDE_EVTLOG_ERROR);
  1728. return;
  1729. }
  1730. ret = _sde_plane_fetch_halt(plane);
  1731. if (ret) {
  1732. SDE_ERROR_PLANE(psde,
  1733. "unused pipe %u halt failed\n",
  1734. psde->pipe - SSPP_VIG0);
  1735. SDE_EVT32(DRMID(plane), psde->pipe - SSPP_VIG0,
  1736. ret, SDE_EVTLOG_ERROR);
  1737. }
  1738. pm_runtime_put_sync(plane->dev->dev);
  1739. }
  1740. msm_framebuffer_cleanup(old_state->fb, old_pstate->aspace);
  1741. }
  1742. static void _sde_plane_sspp_atomic_check_mode_changed(struct sde_plane *psde,
  1743. struct drm_plane_state *state,
  1744. struct drm_plane_state *old_state)
  1745. {
  1746. struct sde_plane_state *pstate = to_sde_plane_state(state);
  1747. struct sde_plane_state *old_pstate = to_sde_plane_state(old_state);
  1748. struct drm_framebuffer *fb, *old_fb;
  1749. /* no need to check it again */
  1750. if (pstate->dirty == SDE_PLANE_DIRTY_ALL)
  1751. return;
  1752. if (!sde_plane_enabled(state) || !sde_plane_enabled(old_state)
  1753. || psde->is_error) {
  1754. SDE_DEBUG_PLANE(psde,
  1755. "enabling/disabling full modeset required\n");
  1756. pstate->dirty |= SDE_PLANE_DIRTY_ALL;
  1757. } else if (to_sde_plane_state(old_state)->pending) {
  1758. SDE_DEBUG_PLANE(psde, "still pending\n");
  1759. pstate->dirty |= SDE_PLANE_DIRTY_ALL;
  1760. } else if (pstate->multirect_index != old_pstate->multirect_index ||
  1761. pstate->multirect_mode != old_pstate->multirect_mode) {
  1762. SDE_DEBUG_PLANE(psde, "multirect config updated\n");
  1763. pstate->dirty |= SDE_PLANE_DIRTY_ALL;
  1764. } else if (state->src_w != old_state->src_w ||
  1765. state->src_h != old_state->src_h ||
  1766. state->src_x != old_state->src_x ||
  1767. state->src_y != old_state->src_y) {
  1768. SDE_DEBUG_PLANE(psde, "src rect updated\n");
  1769. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1770. } else if (state->crtc_w != old_state->crtc_w ||
  1771. state->crtc_h != old_state->crtc_h ||
  1772. state->crtc_x != old_state->crtc_x ||
  1773. state->crtc_y != old_state->crtc_y) {
  1774. SDE_DEBUG_PLANE(psde, "crtc rect updated\n");
  1775. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1776. } else if (pstate->excl_rect.w != old_pstate->excl_rect.w ||
  1777. pstate->excl_rect.h != old_pstate->excl_rect.h ||
  1778. pstate->excl_rect.x != old_pstate->excl_rect.x ||
  1779. pstate->excl_rect.y != old_pstate->excl_rect.y) {
  1780. SDE_DEBUG_PLANE(psde, "excl_rect updated\n");
  1781. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1782. } else if (pstate->rotation != old_pstate->rotation) {
  1783. SDE_DEBUG_PLANE(psde, "rotation updated 0x%x->0x%x\n",
  1784. pstate->rotation, old_pstate->rotation);
  1785. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT;
  1786. }
  1787. fb = state->fb;
  1788. old_fb = old_state->fb;
  1789. if (!fb || !old_fb) {
  1790. SDE_DEBUG_PLANE(psde, "can't compare fb handles\n");
  1791. } else if ((fb->format->format != old_fb->format->format) ||
  1792. pstate->const_alpha_en != old_pstate->const_alpha_en) {
  1793. SDE_DEBUG_PLANE(psde, "format change\n");
  1794. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT | SDE_PLANE_DIRTY_RECTS;
  1795. } else {
  1796. uint64_t new_mod = fb->modifier;
  1797. uint64_t old_mod = old_fb->modifier;
  1798. uint32_t *new_pitches = fb->pitches;
  1799. uint32_t *old_pitches = old_fb->pitches;
  1800. uint32_t *new_offset = fb->offsets;
  1801. uint32_t *old_offset = old_fb->offsets;
  1802. int i;
  1803. if (new_mod != old_mod) {
  1804. SDE_DEBUG_PLANE(psde,
  1805. "format modifiers change new_mode:%llu old_mode:%llu\n",
  1806. new_mod, old_mod);
  1807. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT |
  1808. SDE_PLANE_DIRTY_RECTS;
  1809. }
  1810. for (i = 0; i < ARRAY_SIZE(fb->pitches); i++) {
  1811. if (new_pitches[i] != old_pitches[i]) {
  1812. SDE_DEBUG_PLANE(psde,
  1813. "pitches change plane:%d old_pitches:%u new_pitches:%u\n",
  1814. i, old_pitches[i], new_pitches[i]);
  1815. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  1816. break;
  1817. }
  1818. }
  1819. for (i = 0; i < ARRAY_SIZE(fb->offsets); i++) {
  1820. if (new_offset[i] != old_offset[i]) {
  1821. SDE_DEBUG_PLANE(psde,
  1822. "offset change plane:%d old_offset:%u new_offset:%u\n",
  1823. i, old_offset[i], new_offset[i]);
  1824. pstate->dirty |= SDE_PLANE_DIRTY_FORMAT |
  1825. SDE_PLANE_DIRTY_RECTS;
  1826. break;
  1827. }
  1828. }
  1829. }
  1830. }
  1831. int sde_plane_validate_src_addr(struct drm_plane *plane,
  1832. unsigned long base_addr, u32 size)
  1833. {
  1834. int ret = -EINVAL;
  1835. u32 addr;
  1836. struct sde_plane *psde = to_sde_plane(plane);
  1837. if (!psde || !base_addr || !size) {
  1838. SDE_ERROR_PLANE(psde, "invalid arguments\n");
  1839. return ret;
  1840. }
  1841. if (psde->pipe_hw && psde->pipe_hw->ops.get_sourceaddress) {
  1842. addr = psde->pipe_hw->ops.get_sourceaddress(psde->pipe_hw,
  1843. is_sde_plane_virtual(plane));
  1844. if ((addr >= base_addr) && (addr < (base_addr + size)))
  1845. ret = 0;
  1846. }
  1847. return ret;
  1848. }
  1849. static inline bool _sde_plane_is_pre_downscale_enabled(
  1850. struct sde_hw_inline_pre_downscale_cfg *pre_down)
  1851. {
  1852. return pre_down->pre_downscale_x_0 || pre_down->pre_downscale_y_0;
  1853. }
  1854. static int _sde_plane_validate_scaler_v2(struct sde_plane *psde,
  1855. struct sde_plane_state *pstate,
  1856. const struct sde_format *fmt,
  1857. uint32_t img_w, uint32_t img_h,
  1858. uint32_t src_w, uint32_t src_h,
  1859. uint32_t deci_w, uint32_t deci_h)
  1860. {
  1861. struct sde_hw_inline_pre_downscale_cfg *pd_cfg;
  1862. bool pre_down_en;
  1863. int i;
  1864. if (!psde || !pstate || !fmt) {
  1865. SDE_ERROR_PLANE(psde, "invalid arguments\n");
  1866. return -EINVAL;
  1867. }
  1868. if (psde->debugfs_default_scale ||
  1869. (pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2 &&
  1870. pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2_CHECK))
  1871. return 0;
  1872. pd_cfg = &pstate->pre_down;
  1873. pre_down_en = _sde_plane_is_pre_downscale_enabled(pd_cfg);
  1874. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_INVALID;
  1875. for (i = 0; i < SDE_MAX_PLANES; i++) {
  1876. uint32_t hor_req_pixels, hor_fetch_pixels;
  1877. uint32_t vert_req_pixels, vert_fetch_pixels;
  1878. uint32_t src_w_tmp, src_h_tmp;
  1879. uint32_t scaler_w, scaler_h;
  1880. uint32_t pre_down_ratio_x = 1, pre_down_ratio_y = 1;
  1881. bool rot;
  1882. /* re-use color plane 1's config for plane 2 */
  1883. if (i == 2)
  1884. continue;
  1885. if (pre_down_en) {
  1886. if (i == 0 && pd_cfg->pre_downscale_x_0)
  1887. pre_down_ratio_x = pd_cfg->pre_downscale_x_0;
  1888. if (i == 0 && pd_cfg->pre_downscale_y_0)
  1889. pre_down_ratio_y = pd_cfg->pre_downscale_y_0;
  1890. if ((i == 1 || i == 2) && pd_cfg->pre_downscale_x_1)
  1891. pre_down_ratio_x = pd_cfg->pre_downscale_x_1;
  1892. if ((i == 1 || i == 2) && pd_cfg->pre_downscale_y_1)
  1893. pre_down_ratio_y = pd_cfg->pre_downscale_y_1;
  1894. SDE_DEBUG_PLANE(psde, "pre_down[%d]: x:%d, y:%d\n",
  1895. i, pre_down_ratio_x, pre_down_ratio_y);
  1896. }
  1897. src_w_tmp = src_w;
  1898. src_h_tmp = src_h;
  1899. /*
  1900. * For chroma plane, width is half for the following sub sampled
  1901. * formats. Except in case of decimation, where hardware avoids
  1902. * 1 line of decimation instead of downsampling.
  1903. */
  1904. if (i == 1) {
  1905. if (!deci_w &&
  1906. (fmt->chroma_sample == SDE_CHROMA_420 ||
  1907. fmt->chroma_sample == SDE_CHROMA_H2V1))
  1908. src_w_tmp >>= 1;
  1909. if (!deci_h &&
  1910. (fmt->chroma_sample == SDE_CHROMA_420 ||
  1911. fmt->chroma_sample == SDE_CHROMA_H1V2))
  1912. src_h_tmp >>= 1;
  1913. }
  1914. hor_req_pixels = pstate->pixel_ext.roi_w[i];
  1915. vert_req_pixels = pstate->pixel_ext.roi_h[i];
  1916. hor_fetch_pixels = DECIMATED_DIMENSION(src_w_tmp +
  1917. (int8_t)(pstate->pixel_ext.left_ftch[i] & 0xFF) +
  1918. (int8_t)(pstate->pixel_ext.right_ftch[i] & 0xFF),
  1919. deci_w);
  1920. vert_fetch_pixels = DECIMATED_DIMENSION(src_h_tmp +
  1921. (int8_t)(pstate->pixel_ext.top_ftch[i] & 0xFF) +
  1922. (int8_t)(pstate->pixel_ext.btm_ftch[i] & 0xFF),
  1923. deci_h);
  1924. if ((hor_req_pixels != hor_fetch_pixels) ||
  1925. (hor_fetch_pixels > img_w) ||
  1926. (vert_req_pixels != vert_fetch_pixels) ||
  1927. (vert_fetch_pixels > img_h)) {
  1928. SDE_ERROR_PLANE(psde,
  1929. "req %d/%d, fetch %d/%d, src %dx%d\n",
  1930. hor_req_pixels, vert_req_pixels,
  1931. hor_fetch_pixels, vert_fetch_pixels,
  1932. img_w, img_h);
  1933. return -EINVAL;
  1934. }
  1935. /*
  1936. * swap the scaler src width & height for inline-rotation 90
  1937. * comparison with Pixel-Extension, as PE is based on
  1938. * pre-rotation and QSEED is based on post-rotation
  1939. */
  1940. rot = pstate->rotation & DRM_MODE_ROTATE_90;
  1941. scaler_w = rot ? pstate->scaler3_cfg.src_height[i]
  1942. : pstate->scaler3_cfg.src_width[i];
  1943. scaler_h = rot ? pstate->scaler3_cfg.src_width[i]
  1944. : pstate->scaler3_cfg.src_height[i];
  1945. /*
  1946. * Alpha plane can only be scaled using bilinear or pixel
  1947. * repeat/drop, src_width and src_height are only specified
  1948. * for Y and UV plane
  1949. */
  1950. if (i != 3 && (hor_req_pixels / pre_down_ratio_x != scaler_w ||
  1951. vert_req_pixels / pre_down_ratio_y !=
  1952. scaler_h)) {
  1953. SDE_ERROR_PLANE(psde,
  1954. "roi[%d] roi:%dx%d scaler:%dx%d src:%dx%d rot:%d pd:%d/%d\n",
  1955. i, pstate->pixel_ext.roi_w[i],
  1956. pstate->pixel_ext.roi_h[i], scaler_w, scaler_h,
  1957. src_w, src_h, rot, pre_down_ratio_x, pre_down_ratio_y);
  1958. return -EINVAL;
  1959. }
  1960. /*
  1961. * SSPP fetch , unpack output and QSEED3 input lines need
  1962. * to match for Y plane
  1963. */
  1964. if (i == 0 &&
  1965. (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) &
  1966. BIT(SDE_DRM_DEINTERLACE)) &&
  1967. ((pstate->scaler3_cfg.src_height[i] != (src_h/2)) ||
  1968. (pstate->pixel_ext.roi_h[i] != (src_h/2)))) {
  1969. SDE_ERROR_PLANE(psde,
  1970. "de-interlace fail roi[%d] %d/%d, src %dx%d, src %dx%d\n",
  1971. i, pstate->pixel_ext.roi_w[i],
  1972. pstate->pixel_ext.roi_h[i],
  1973. pstate->scaler3_cfg.src_width[i],
  1974. pstate->scaler3_cfg.src_height[i],
  1975. src_w, src_h);
  1976. return -EINVAL;
  1977. }
  1978. }
  1979. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_SCALER_V2;
  1980. return 0;
  1981. }
  1982. static inline bool _sde_plane_has_pre_downscale(struct sde_plane *psde)
  1983. {
  1984. return (psde->features & BIT(SDE_SSPP_PREDOWNSCALE));
  1985. }
  1986. static int _sde_atomic_check_pre_downscale(struct sde_plane *psde,
  1987. struct sde_plane_state *pstate, struct sde_rect *dst,
  1988. u32 src_w, u32 src_h)
  1989. {
  1990. int ret = 0;
  1991. u32 min_ratio_numer, min_ratio_denom;
  1992. struct sde_hw_inline_pre_downscale_cfg *pd_cfg = &pstate->pre_down;
  1993. bool pd_x;
  1994. bool pd_y;
  1995. if (!_sde_plane_is_pre_downscale_enabled(pd_cfg))
  1996. return ret;
  1997. pd_x = pd_cfg->pre_downscale_x_0 > 1;
  1998. pd_y = pd_cfg->pre_downscale_y_0 > 1;
  1999. min_ratio_numer = psde->pipe_sblk->in_rot_maxdwnscale_rt_nopd_num;
  2000. min_ratio_denom = psde->pipe_sblk->in_rot_maxdwnscale_rt_nopd_denom;
  2001. if (pd_x && !_sde_plane_has_pre_downscale(psde)) {
  2002. SDE_ERROR_PLANE(psde,
  2003. "hw does not support pre-downscale X: 0x%x\n",
  2004. psde->features);
  2005. ret = -EINVAL;
  2006. } else if (pd_y && !(psde->features & BIT(SDE_SSPP_PREDOWNSCALE_Y))) {
  2007. SDE_ERROR_PLANE(psde,
  2008. "hw does not support pre-downscale Y: 0x%x\n",
  2009. psde->features);
  2010. ret = -EINVAL;
  2011. } else if (!min_ratio_numer || !min_ratio_denom) {
  2012. SDE_ERROR_PLANE(psde,
  2013. "min downscale ratio not set! %u / %u\n",
  2014. min_ratio_numer, min_ratio_denom);
  2015. ret = -EINVAL;
  2016. /* compare pre-rotated src w/h with post-rotated dst h/w resp. */
  2017. } else if (pd_x && (src_w < mult_frac(dst->h, min_ratio_numer,
  2018. min_ratio_denom))) {
  2019. SDE_ERROR_PLANE(psde,
  2020. "failed min downscale-x check %u->%u, %u/%u\n",
  2021. src_w, dst->h, min_ratio_numer, min_ratio_denom);
  2022. ret = -EINVAL;
  2023. } else if (pd_y && (src_h < mult_frac(dst->w, min_ratio_numer,
  2024. min_ratio_denom))) {
  2025. SDE_ERROR_PLANE(psde,
  2026. "failed min downscale-y check %u->%u, %u/%u\n",
  2027. src_h, dst->w, min_ratio_numer, min_ratio_denom);
  2028. ret = -EINVAL;
  2029. }
  2030. return ret;
  2031. }
  2032. static void _sde_plane_get_max_downscale_limits(struct sde_plane *psde,
  2033. struct sde_plane_state *pstate, bool rt_client, u32 dst_h,
  2034. u32 src_h, u32 *max_numer_w, u32 *max_denom_w,
  2035. u32 *max_numer_h, u32 *max_denom_h)
  2036. {
  2037. bool rotated, has_predown, default_scale;
  2038. const struct sde_sspp_sub_blks *sblk;
  2039. struct sde_hw_inline_pre_downscale_cfg *pd;
  2040. rotated = pstate->rotation & DRM_MODE_ROTATE_90;
  2041. sblk = psde->pipe_sblk;
  2042. *max_numer_w = sblk->maxdwnscale;
  2043. *max_denom_w = 1;
  2044. *max_numer_h = sblk->maxdwnscale;
  2045. *max_denom_h = 1;
  2046. has_predown = _sde_plane_has_pre_downscale(psde);
  2047. if (has_predown)
  2048. pd = &pstate->pre_down;
  2049. default_scale = psde->debugfs_default_scale ||
  2050. (pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2 &&
  2051. pstate->scaler_check_state != SDE_PLANE_SCLCHECK_SCALER_V2_CHECK);
  2052. /**
  2053. * Inline rotation has different max vertical downscaling limits since
  2054. * the source-width becomes the scaler's pre-downscaled source-height.
  2055. **/
  2056. if (rotated) {
  2057. if (rt_client && has_predown) {
  2058. if (default_scale)
  2059. pd->pre_downscale_x_0 = (src_h >
  2060. mult_frac(dst_h, 11, 5)) ? 2 : 0;
  2061. *max_numer_h = pd->pre_downscale_x_0 ?
  2062. sblk->in_rot_maxdwnscale_rt_num :
  2063. sblk->in_rot_maxdwnscale_rt_nopd_num;
  2064. *max_denom_h = pd->pre_downscale_x_0 ?
  2065. sblk->in_rot_maxdwnscale_rt_denom :
  2066. sblk->in_rot_maxdwnscale_rt_nopd_denom;
  2067. } else if (rt_client) {
  2068. *max_numer_h = sblk->in_rot_maxdwnscale_rt_num;
  2069. *max_denom_h = sblk->in_rot_maxdwnscale_rt_denom;
  2070. } else {
  2071. *max_numer_h = sblk->in_rot_maxdwnscale_nrt;
  2072. }
  2073. }
  2074. }
  2075. static int _sde_atomic_check_decimation_scaler(struct drm_plane_state *state,
  2076. struct sde_plane *psde, const struct sde_format *fmt,
  2077. struct sde_plane_state *pstate, struct sde_rect *src,
  2078. struct sde_rect *dst, u32 width, u32 height)
  2079. {
  2080. int ret = 0;
  2081. uint32_t deci_w, deci_h, src_deci_w, src_deci_h;
  2082. uint32_t scaler_src_w, scaler_src_h;
  2083. uint32_t max_downscale_num_w, max_downscale_denom_w;
  2084. uint32_t max_downscale_num_h, max_downscale_denom_h;
  2085. uint32_t max_upscale, max_linewidth;
  2086. bool inline_rotation, rt_client;
  2087. struct drm_crtc *crtc;
  2088. struct drm_crtc_state *new_cstate;
  2089. const struct sde_sspp_sub_blks *sblk;
  2090. if (!state || !state->state || !state->crtc) {
  2091. SDE_ERROR_PLANE(psde, "invalid arguments\n");
  2092. return -EINVAL;
  2093. }
  2094. deci_w = sde_plane_get_property(pstate, PLANE_PROP_H_DECIMATE);
  2095. deci_h = sde_plane_get_property(pstate, PLANE_PROP_V_DECIMATE);
  2096. src_deci_w = DECIMATED_DIMENSION(src->w, deci_w);
  2097. src_deci_h = DECIMATED_DIMENSION(src->h, deci_h);
  2098. /* with inline rotator, the source of the scaler is post-rotated */
  2099. inline_rotation = pstate->rotation & DRM_MODE_ROTATE_90 ? true : false;
  2100. if (inline_rotation) {
  2101. scaler_src_w = src_deci_h;
  2102. scaler_src_h = src_deci_w;
  2103. } else {
  2104. scaler_src_w = src_deci_w;
  2105. scaler_src_h = src_deci_h;
  2106. }
  2107. sblk = psde->pipe_sblk;
  2108. max_upscale = sblk->maxupscale;
  2109. if (inline_rotation)
  2110. max_linewidth = sblk->in_rot_maxheight;
  2111. else if (scaler_src_w != state->crtc_w || scaler_src_h != state->crtc_h)
  2112. max_linewidth = sblk->scaling_linewidth;
  2113. else
  2114. max_linewidth = sblk->maxlinewidth;
  2115. crtc = state->crtc;
  2116. new_cstate = drm_atomic_get_new_crtc_state(state->state, crtc);
  2117. rt_client = sde_crtc_is_rt_client(crtc, new_cstate);
  2118. _sde_plane_get_max_downscale_limits(psde, pstate, rt_client, dst->h,
  2119. scaler_src_h, &max_downscale_num_w, &max_downscale_denom_w,
  2120. &max_downscale_num_h, &max_downscale_denom_h);
  2121. /* decimation validation */
  2122. if ((deci_w || deci_h)
  2123. && ((deci_w > sblk->maxhdeciexp)
  2124. || (deci_h > sblk->maxvdeciexp))) {
  2125. SDE_ERROR_PLANE(psde, "too much decimation requested\n");
  2126. ret = -EINVAL;
  2127. } else if ((deci_w || deci_h)
  2128. && (fmt->fetch_mode != SDE_FETCH_LINEAR)) {
  2129. SDE_ERROR_PLANE(psde, "decimation requires linear fetch\n");
  2130. ret = -EINVAL;
  2131. } else if (!(psde->features & SDE_SSPP_SCALER) &&
  2132. ((src->w != dst->w) || (src->h != dst->h))) {
  2133. SDE_ERROR_PLANE(psde,
  2134. "pipe doesn't support scaling %ux%u->%ux%u\n",
  2135. src->w, src->h, dst->w, dst->h);
  2136. ret = -EINVAL;
  2137. /* check scaler source width */
  2138. } else if (scaler_src_w > max_linewidth) {
  2139. SDE_ERROR_PLANE(psde,
  2140. "invalid src w:%u, scaler w:%u, line w:%u, rot: %d\n",
  2141. src->w, scaler_src_w, max_linewidth, inline_rotation);
  2142. ret = -E2BIG;
  2143. /* check max scaler capability */
  2144. } else if (((scaler_src_w * max_upscale) < dst->w) ||
  2145. ((scaler_src_h * max_upscale) < dst->h) ||
  2146. (mult_frac(dst->w, max_downscale_num_w, max_downscale_denom_w)
  2147. < scaler_src_w) ||
  2148. (mult_frac(dst->h, max_downscale_num_h, max_downscale_denom_h)
  2149. < scaler_src_h)) {
  2150. SDE_ERROR_PLANE(psde,
  2151. "too much scaling %ux%u->%ux%u rot:%d dwn:%d/%d %d/%d\n",
  2152. scaler_src_w, scaler_src_h, dst->w, dst->h,
  2153. inline_rotation, max_downscale_num_w,
  2154. max_downscale_denom_w, max_downscale_num_h,
  2155. max_downscale_denom_h);
  2156. ret = -E2BIG;
  2157. /* check inline pre-downscale support */
  2158. } else if (inline_rotation && _sde_atomic_check_pre_downscale(psde,
  2159. pstate, dst, src_deci_w, src_deci_h)) {
  2160. ret = -EINVAL;
  2161. /* QSEED validation */
  2162. } else if (_sde_plane_validate_scaler_v2(psde, pstate, fmt,
  2163. width, height, src->w, src->h,
  2164. deci_w, deci_h)) {
  2165. ret = -EINVAL;
  2166. }
  2167. return ret;
  2168. }
  2169. static int _sde_atomic_check_excl_rect(struct sde_plane *psde,
  2170. struct sde_plane_state *pstate, struct sde_rect *src,
  2171. const struct sde_format *fmt, int ret)
  2172. {
  2173. /* check excl rect configs */
  2174. if (!ret && pstate->excl_rect.w && pstate->excl_rect.h) {
  2175. struct sde_rect intersect;
  2176. /*
  2177. * Check exclusion rect against src rect.
  2178. * it must intersect with source rect.
  2179. */
  2180. sde_kms_rect_intersect(src, &pstate->excl_rect, &intersect);
  2181. if (intersect.w != pstate->excl_rect.w ||
  2182. intersect.h != pstate->excl_rect.h ||
  2183. SDE_FORMAT_IS_YUV(fmt)) {
  2184. SDE_ERROR_PLANE(psde,
  2185. "invalid excl_rect:{%d,%d,%d,%d} src:{%d,%d,%d,%d}, fmt: %4.4s\n",
  2186. pstate->excl_rect.x, pstate->excl_rect.y,
  2187. pstate->excl_rect.w, pstate->excl_rect.h,
  2188. src->x, src->y, src->w, src->h,
  2189. (char *)&fmt->base.pixel_format);
  2190. ret = -EINVAL;
  2191. }
  2192. SDE_DEBUG_PLANE(psde, "excl_rect: {%d,%d,%d,%d}\n",
  2193. pstate->excl_rect.x, pstate->excl_rect.y,
  2194. pstate->excl_rect.w, pstate->excl_rect.h);
  2195. }
  2196. return ret;
  2197. }
  2198. static int _sde_plane_validate_shared_crtc(struct sde_plane *psde,
  2199. struct drm_plane_state *state)
  2200. {
  2201. struct sde_kms *sde_kms;
  2202. struct sde_splash_display *splash_display;
  2203. int i, j;
  2204. sde_kms = _sde_plane_get_kms(&psde->base);
  2205. if (!sde_kms || !state->crtc)
  2206. return 0;
  2207. for (i = 0; i < MAX_DSI_DISPLAYS; i++) {
  2208. splash_display = &sde_kms->splash_data.splash_display[i];
  2209. if (splash_display && splash_display->cont_splash_enabled &&
  2210. splash_display->encoder &&
  2211. state->crtc != splash_display->encoder->crtc) {
  2212. for (j = 0; j < MAX_DATA_PATH_PER_DSIPLAY; j++) {
  2213. if (splash_display->pipes[j].sspp ==
  2214. psde->pipe) {
  2215. SDE_ERROR_PLANE(psde,
  2216. "pipe:%d used in cont-splash on crtc:%d\n",
  2217. psde->pipe,
  2218. splash_display->encoder->crtc->base.id);
  2219. return -EINVAL;
  2220. }
  2221. }
  2222. }
  2223. }
  2224. return 0;
  2225. }
  2226. static int _sde_plane_sspp_atomic_check_helper(struct sde_plane *psde,
  2227. const struct sde_format *fmt,
  2228. struct sde_rect src, struct sde_rect dst,
  2229. u32 width, u32 height)
  2230. {
  2231. int ret = 0;
  2232. u32 min_src_size = SDE_FORMAT_IS_YUV(fmt) ? 2 : 1;
  2233. if (SDE_FORMAT_IS_YUV(fmt) &&
  2234. (!(psde->features & SDE_SSPP_SCALER) ||
  2235. !(psde->features & (BIT(SDE_SSPP_CSC)
  2236. | BIT(SDE_SSPP_CSC_10BIT))))) {
  2237. SDE_ERROR_PLANE(psde,
  2238. "plane doesn't have scaler/csc for yuv\n");
  2239. ret = -EINVAL;
  2240. /* check src bounds */
  2241. } else if (width > MAX_IMG_WIDTH || height > MAX_IMG_HEIGHT ||
  2242. src.w < min_src_size || src.h < min_src_size ||
  2243. CHECK_LAYER_BOUNDS(src.x, src.w, width) ||
  2244. CHECK_LAYER_BOUNDS(src.y, src.h, height)) {
  2245. SDE_ERROR_PLANE(psde, "invalid source %u, %u, %ux%u\n",
  2246. src.x, src.y, src.w, src.h);
  2247. ret = -E2BIG;
  2248. /* valid yuv image */
  2249. } else if (SDE_FORMAT_IS_YUV(fmt) && ((src.x & 0x1) || (src.y & 0x1) ||
  2250. (src.w & 0x1) || (src.h & 0x1))) {
  2251. SDE_ERROR_PLANE(psde, "invalid yuv source %u, %u, %ux%u\n",
  2252. src.x, src.y, src.w, src.h);
  2253. ret = -EINVAL;
  2254. /* min dst support */
  2255. } else if (dst.w < 0x1 || dst.h < 0x1) {
  2256. SDE_ERROR_PLANE(psde, "invalid dest rect %u, %u, %ux%u\n",
  2257. dst.x, dst.y, dst.w, dst.h);
  2258. ret = -EINVAL;
  2259. } else if (SDE_FORMAT_IS_UBWC(fmt) &&
  2260. !psde->catalog->ubwc_version) {
  2261. SDE_ERROR_PLANE(psde, "ubwc not supported\n");
  2262. ret = -EINVAL;
  2263. }
  2264. return ret;
  2265. }
  2266. static int sde_plane_sspp_atomic_check(struct drm_plane *plane,
  2267. struct drm_plane_state *state)
  2268. {
  2269. int ret = 0;
  2270. struct sde_plane *psde;
  2271. struct sde_plane_state *pstate;
  2272. const struct msm_format *msm_fmt;
  2273. const struct sde_format *fmt;
  2274. struct sde_rect src, dst;
  2275. bool q16_data = true;
  2276. struct drm_framebuffer *fb;
  2277. u32 width;
  2278. u32 height;
  2279. psde = to_sde_plane(plane);
  2280. pstate = to_sde_plane_state(state);
  2281. if (!psde->pipe_sblk) {
  2282. SDE_ERROR_PLANE(psde, "invalid catalog\n");
  2283. return -EINVAL;
  2284. }
  2285. /* src values are in Q16 fixed point, convert to integer */
  2286. POPULATE_RECT(&src, state->src_x, state->src_y,
  2287. state->src_w, state->src_h, q16_data);
  2288. POPULATE_RECT(&dst, state->crtc_x, state->crtc_y, state->crtc_w,
  2289. state->crtc_h, !q16_data);
  2290. SDE_DEBUG_PLANE(psde, "check %d -> %d\n",
  2291. sde_plane_enabled(plane->state), sde_plane_enabled(state));
  2292. if (!sde_plane_enabled(state))
  2293. goto modeset_update;
  2294. fb = state->fb;
  2295. width = fb ? state->fb->width : 0x0;
  2296. height = fb ? state->fb->height : 0x0;
  2297. SDE_DEBUG("plane%d sspp:%x/%dx%d/%4.4s/%llx\n",
  2298. plane->base.id,
  2299. pstate->rotation,
  2300. width, height,
  2301. fb ? (char *) &state->fb->format->format : 0x0,
  2302. fb ? state->fb->modifier : 0x0);
  2303. SDE_DEBUG("src:%dx%d %d,%d crtc:%dx%d+%d+%d\n",
  2304. state->src_w >> 16, state->src_h >> 16,
  2305. state->src_x >> 16, state->src_y >> 16,
  2306. state->crtc_w, state->crtc_h,
  2307. state->crtc_x, state->crtc_y);
  2308. msm_fmt = msm_framebuffer_format(fb);
  2309. fmt = to_sde_format(msm_fmt);
  2310. ret = _sde_plane_sspp_atomic_check_helper(psde, fmt, src, dst, width,
  2311. height);
  2312. if (ret)
  2313. return ret;
  2314. ret = _sde_atomic_check_decimation_scaler(state, psde, fmt, pstate,
  2315. &src, &dst, width, height);
  2316. if (ret)
  2317. return ret;
  2318. ret = _sde_atomic_check_excl_rect(psde, pstate,
  2319. &src, fmt, ret);
  2320. if (ret)
  2321. return ret;
  2322. ret = _sde_plane_validate_shared_crtc(psde, state);
  2323. if (ret)
  2324. return ret;
  2325. pstate->const_alpha_en = fmt->alpha_enable &&
  2326. (SDE_DRM_BLEND_OP_OPAQUE !=
  2327. sde_plane_get_property(pstate, PLANE_PROP_BLEND_OP)) &&
  2328. (pstate->stage != SDE_STAGE_0);
  2329. modeset_update:
  2330. if (!ret)
  2331. _sde_plane_sspp_atomic_check_mode_changed(psde,
  2332. state, plane->state);
  2333. return ret;
  2334. }
  2335. static int sde_plane_atomic_check(struct drm_plane *plane,
  2336. struct drm_plane_state *state)
  2337. {
  2338. int ret = 0;
  2339. struct sde_plane *psde;
  2340. struct sde_plane_state *pstate;
  2341. if (!plane || !state) {
  2342. SDE_ERROR("invalid arg(s), plane %d state %d\n",
  2343. !plane, !state);
  2344. ret = -EINVAL;
  2345. goto exit;
  2346. }
  2347. psde = to_sde_plane(plane);
  2348. pstate = to_sde_plane_state(state);
  2349. SDE_DEBUG_PLANE(psde, "\n");
  2350. ret = sde_plane_rot_atomic_check(plane, state);
  2351. if (ret)
  2352. goto exit;
  2353. ret = sde_plane_sspp_atomic_check(plane, state);
  2354. exit:
  2355. return ret;
  2356. }
  2357. void sde_plane_flush(struct drm_plane *plane)
  2358. {
  2359. struct sde_plane *psde;
  2360. struct sde_plane_state *pstate;
  2361. if (!plane || !plane->state) {
  2362. SDE_ERROR("invalid plane\n");
  2363. return;
  2364. }
  2365. psde = to_sde_plane(plane);
  2366. pstate = to_sde_plane_state(plane->state);
  2367. /*
  2368. * These updates have to be done immediately before the plane flush
  2369. * timing, and may not be moved to the atomic_update/mode_set functions.
  2370. */
  2371. if (psde->is_error)
  2372. /* force white frame with 100% alpha pipe output on error */
  2373. _sde_plane_color_fill(psde, 0xFFFFFF, 0xFF);
  2374. else if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG)
  2375. /* force 100% alpha */
  2376. _sde_plane_color_fill(psde, psde->color_fill, 0xFF);
  2377. else if (psde->pipe_hw && psde->csc_ptr && psde->pipe_hw->ops.setup_csc)
  2378. psde->pipe_hw->ops.setup_csc(psde->pipe_hw, psde->csc_ptr);
  2379. /* flag h/w flush complete */
  2380. if (plane->state)
  2381. pstate->pending = false;
  2382. }
  2383. /**
  2384. * sde_plane_set_error: enable/disable error condition
  2385. * @plane: pointer to drm_plane structure
  2386. */
  2387. void sde_plane_set_error(struct drm_plane *plane, bool error)
  2388. {
  2389. struct sde_plane *psde;
  2390. if (!plane)
  2391. return;
  2392. psde = to_sde_plane(plane);
  2393. psde->is_error = error;
  2394. }
  2395. static void _sde_plane_sspp_setup_sys_cache(struct sde_plane *psde,
  2396. struct sde_plane_state *pstate, bool is_tp10)
  2397. {
  2398. struct sde_sc_cfg *sc_cfg = psde->catalog->sc_cfg;
  2399. if (!psde->pipe_hw->ops.setup_sys_cache ||
  2400. !(psde->perf_features & BIT(SDE_PERF_SSPP_SYS_CACHE)))
  2401. return;
  2402. SDE_DEBUG("features:0x%x rotation:0x%x\n",
  2403. psde->features, pstate->rotation);
  2404. pstate->sc_cfg.rd_en = false;
  2405. pstate->sc_cfg.rd_scid = 0x0;
  2406. pstate->sc_cfg.flags = SSPP_SYS_CACHE_EN_FLAG |
  2407. SSPP_SYS_CACHE_SCID;
  2408. pstate->sc_cfg.type = SDE_SYS_CACHE_NONE;
  2409. if (pstate->rotation & DRM_MODE_ROTATE_90) {
  2410. if (is_tp10 && sc_cfg[SDE_SYS_CACHE_ROT].has_sys_cache) {
  2411. pstate->sc_cfg.rd_en = true;
  2412. pstate->sc_cfg.rd_scid =
  2413. sc_cfg[SDE_SYS_CACHE_ROT].llcc_scid;
  2414. pstate->sc_cfg.flags = SSPP_SYS_CACHE_EN_FLAG |
  2415. SSPP_SYS_CACHE_SCID;
  2416. pstate->sc_cfg.type = SDE_SYS_CACHE_ROT;
  2417. }
  2418. } else if (pstate->static_cache_state == CACHE_STATE_FRAME_WRITE &&
  2419. sc_cfg[SDE_SYS_CACHE_DISP].has_sys_cache) {
  2420. pstate->sc_cfg.rd_en = true;
  2421. pstate->sc_cfg.rd_scid =
  2422. sc_cfg[SDE_SYS_CACHE_DISP].llcc_scid;
  2423. pstate->sc_cfg.rd_noallocate = false;
  2424. pstate->sc_cfg.flags = SSPP_SYS_CACHE_EN_FLAG |
  2425. SSPP_SYS_CACHE_SCID | SSPP_SYS_CACHE_NO_ALLOC;
  2426. pstate->sc_cfg.type = SDE_SYS_CACHE_DISP;
  2427. } else if (pstate->static_cache_state == CACHE_STATE_FRAME_READ &&
  2428. sc_cfg[SDE_SYS_CACHE_DISP].has_sys_cache) {
  2429. pstate->sc_cfg.rd_en = true;
  2430. pstate->sc_cfg.rd_scid =
  2431. sc_cfg[SDE_SYS_CACHE_DISP].llcc_scid;
  2432. pstate->sc_cfg.rd_noallocate = true;
  2433. pstate->sc_cfg.flags = SSPP_SYS_CACHE_EN_FLAG |
  2434. SSPP_SYS_CACHE_SCID | SSPP_SYS_CACHE_NO_ALLOC;
  2435. pstate->sc_cfg.type = SDE_SYS_CACHE_DISP;
  2436. }
  2437. SDE_EVT32(DRMID(&psde->base), pstate->sc_cfg.rd_scid,
  2438. pstate->sc_cfg.rd_en, pstate->sc_cfg.rd_noallocate);
  2439. psde->pipe_hw->ops.setup_sys_cache(
  2440. psde->pipe_hw, &pstate->sc_cfg);
  2441. }
  2442. void sde_plane_static_img_control(struct drm_plane *plane,
  2443. enum sde_crtc_cache_state state)
  2444. {
  2445. struct sde_plane *psde;
  2446. struct sde_plane_state *pstate;
  2447. if (!plane || !plane->state) {
  2448. SDE_ERROR("invalid plane\n");
  2449. return;
  2450. }
  2451. psde = to_sde_plane(plane);
  2452. pstate = to_sde_plane_state(plane->state);
  2453. pstate->static_cache_state = state;
  2454. if (state == CACHE_STATE_FRAME_WRITE || state == CACHE_STATE_FRAME_READ)
  2455. _sde_plane_sspp_setup_sys_cache(psde, pstate, false);
  2456. }
  2457. static void _sde_plane_map_prop_to_dirty_bits(void)
  2458. {
  2459. plane_prop_array[PLANE_PROP_SCALER_V1] =
  2460. plane_prop_array[PLANE_PROP_SCALER_V2] =
  2461. plane_prop_array[PLANE_PROP_SCALER_LUT_ED] =
  2462. plane_prop_array[PLANE_PROP_SCALER_LUT_CIR] =
  2463. plane_prop_array[PLANE_PROP_SCALER_LUT_SEP] =
  2464. plane_prop_array[PLANE_PROP_H_DECIMATE] =
  2465. plane_prop_array[PLANE_PROP_V_DECIMATE] =
  2466. plane_prop_array[PLANE_PROP_SRC_CONFIG] =
  2467. plane_prop_array[PLANE_PROP_ZPOS] =
  2468. plane_prop_array[PLANE_PROP_EXCL_RECT_V1] =
  2469. SDE_PLANE_DIRTY_RECTS;
  2470. plane_prop_array[PLANE_PROP_CSC_V1] =
  2471. plane_prop_array[PLANE_PROP_CSC_DMA_V1] =
  2472. plane_prop_array[PLANE_PROP_INVERSE_PMA] =
  2473. SDE_PLANE_DIRTY_FORMAT;
  2474. plane_prop_array[PLANE_PROP_MULTIRECT_MODE] =
  2475. plane_prop_array[PLANE_PROP_COLOR_FILL] =
  2476. SDE_PLANE_DIRTY_ALL;
  2477. /* no special action required */
  2478. plane_prop_array[PLANE_PROP_INFO] =
  2479. plane_prop_array[PLANE_PROP_ALPHA] =
  2480. plane_prop_array[PLANE_PROP_INPUT_FENCE] =
  2481. plane_prop_array[PLANE_PROP_BLEND_OP] = 0;
  2482. plane_prop_array[PLANE_PROP_FB_TRANSLATION_MODE] =
  2483. SDE_PLANE_DIRTY_FB_TRANSLATION_MODE;
  2484. plane_prop_array[PLANE_PROP_PREFILL_SIZE] =
  2485. plane_prop_array[PLANE_PROP_PREFILL_TIME] =
  2486. SDE_PLANE_DIRTY_PERF;
  2487. plane_prop_array[PLANE_PROP_VIG_GAMUT] = SDE_PLANE_DIRTY_VIG_GAMUT;
  2488. plane_prop_array[PLANE_PROP_VIG_IGC] = SDE_PLANE_DIRTY_VIG_IGC;
  2489. plane_prop_array[PLANE_PROP_DMA_IGC] = SDE_PLANE_DIRTY_DMA_IGC;
  2490. plane_prop_array[PLANE_PROP_DMA_GC] = SDE_PLANE_DIRTY_DMA_GC;
  2491. plane_prop_array[PLANE_PROP_SKIN_COLOR] =
  2492. plane_prop_array[PLANE_PROP_SKY_COLOR] =
  2493. plane_prop_array[PLANE_PROP_FOLIAGE_COLOR] =
  2494. plane_prop_array[PLANE_PROP_HUE_ADJUST] =
  2495. plane_prop_array[PLANE_PROP_SATURATION_ADJUST] =
  2496. plane_prop_array[PLANE_PROP_VALUE_ADJUST] =
  2497. plane_prop_array[PLANE_PROP_CONTRAST_ADJUST] =
  2498. SDE_PLANE_DIRTY_ALL;
  2499. }
  2500. static inline bool _sde_plane_allow_uidle(struct sde_plane *psde,
  2501. struct sde_rect *src, struct sde_rect *dst)
  2502. {
  2503. u32 max_downscale = psde->catalog->uidle_cfg.max_dwnscale;
  2504. u32 downscale = (src->h * 1000)/dst->h;
  2505. return (downscale > max_downscale) ? false : true;
  2506. }
  2507. static void _sde_plane_setup_uidle(struct drm_crtc *crtc,
  2508. struct sde_plane *psde, struct sde_plane_state *pstate,
  2509. struct sde_rect *src, struct sde_rect *dst)
  2510. {
  2511. struct sde_hw_pipe_uidle_cfg cfg;
  2512. struct sde_crtc *sde_crtc = to_sde_crtc(crtc);
  2513. u32 line_time = sde_get_linetime(&crtc->mode,
  2514. sde_crtc->src_bpp, sde_crtc->target_bpp); /* nS */
  2515. u32 fal1_target_idle_time_ns =
  2516. psde->catalog->uidle_cfg.fal1_target_idle_time * 1000; /* nS */
  2517. u32 fal10_target_idle_time_ns =
  2518. psde->catalog->uidle_cfg.fal10_target_idle_time * 1000; /* nS */
  2519. u32 fal10_threshold =
  2520. psde->catalog->uidle_cfg.fal10_threshold; /* uS */
  2521. if (line_time && fal10_threshold && fal10_target_idle_time_ns &&
  2522. fal1_target_idle_time_ns) {
  2523. cfg.enable = _sde_plane_allow_uidle(psde, src, dst);
  2524. cfg.fal10_threshold = fal10_threshold;
  2525. cfg.fal10_exit_threshold = fal10_threshold + 2;
  2526. cfg.fal1_threshold = 1 +
  2527. (fal1_target_idle_time_ns*1000/line_time*2)/1000;
  2528. cfg.fal_allowed_threshold = fal10_threshold +
  2529. (fal10_target_idle_time_ns*1000/line_time*2)/1000;
  2530. } else {
  2531. SDE_ERROR("invalid settings, will disable UIDLE %d %d %d %d\n",
  2532. line_time, fal10_threshold, fal10_target_idle_time_ns,
  2533. fal1_target_idle_time_ns);
  2534. memset(&cfg, 0, sizeof(struct sde_hw_pipe_uidle_cfg));
  2535. }
  2536. SDE_DEBUG_PLANE(psde,
  2537. "tholds: fal10=%d fal10_exit=%d fal1=%d fal_allowed=%d\n",
  2538. cfg.fal10_threshold, cfg.fal10_exit_threshold,
  2539. cfg.fal1_threshold, cfg.fal_allowed_threshold);
  2540. SDE_DEBUG_PLANE(psde,
  2541. "times: line:%d fal1_idle:%d fal10_idle:%d dwnscale:%d\n",
  2542. line_time, fal1_target_idle_time_ns,
  2543. fal10_target_idle_time_ns,
  2544. psde->catalog->uidle_cfg.max_dwnscale);
  2545. SDE_EVT32_VERBOSE(cfg.enable,
  2546. cfg.fal10_threshold, cfg.fal10_exit_threshold,
  2547. cfg.fal1_threshold, cfg.fal_allowed_threshold,
  2548. psde->catalog->uidle_cfg.max_dwnscale);
  2549. psde->pipe_hw->ops.setup_uidle(
  2550. psde->pipe_hw, &cfg,
  2551. pstate->multirect_index);
  2552. }
  2553. static void _sde_plane_update_secure_session(struct sde_plane *psde,
  2554. struct sde_plane_state *pstate)
  2555. {
  2556. bool enable = false;
  2557. int mode = sde_plane_get_property(pstate,
  2558. PLANE_PROP_FB_TRANSLATION_MODE);
  2559. if ((mode == SDE_DRM_FB_SEC) ||
  2560. (mode == SDE_DRM_FB_SEC_DIR_TRANS))
  2561. enable = true;
  2562. /* update secure session flag */
  2563. psde->pipe_hw->ops.setup_secure_address(psde->pipe_hw,
  2564. pstate->multirect_index,
  2565. enable);
  2566. }
  2567. static void _sde_plane_update_roi_config(struct drm_plane *plane,
  2568. struct drm_crtc *crtc, struct drm_framebuffer *fb)
  2569. {
  2570. const struct sde_format *fmt;
  2571. const struct msm_format *msm_fmt;
  2572. struct sde_plane *psde;
  2573. struct drm_plane_state *state;
  2574. struct sde_plane_state *pstate;
  2575. struct sde_rect src, dst;
  2576. const struct sde_rect *crtc_roi;
  2577. bool q16_data = true;
  2578. int idx;
  2579. psde = to_sde_plane(plane);
  2580. state = plane->state;
  2581. pstate = to_sde_plane_state(state);
  2582. msm_fmt = msm_framebuffer_format(fb);
  2583. if (!msm_fmt) {
  2584. SDE_ERROR("crtc%d plane%d: null format\n",
  2585. DRMID(crtc), DRMID(plane));
  2586. return;
  2587. }
  2588. fmt = to_sde_format(msm_fmt);
  2589. POPULATE_RECT(&src, state->src_x, state->src_y,
  2590. state->src_w, state->src_h, q16_data);
  2591. POPULATE_RECT(&dst, state->crtc_x, state->crtc_y,
  2592. state->crtc_w, state->crtc_h, !q16_data);
  2593. SDE_DEBUG_PLANE(psde,
  2594. "FB[%u] %u,%u,%ux%u->crtc%u %d,%d,%ux%u, %4.4s ubwc %d\n",
  2595. fb->base.id, src.x, src.y, src.w, src.h,
  2596. crtc->base.id, dst.x, dst.y, dst.w, dst.h,
  2597. (char *)&fmt->base.pixel_format,
  2598. SDE_FORMAT_IS_UBWC(fmt));
  2599. if (sde_plane_get_property(pstate, PLANE_PROP_SRC_CONFIG) &
  2600. BIT(SDE_DRM_DEINTERLACE)) {
  2601. SDE_DEBUG_PLANE(psde, "deinterlace\n");
  2602. for (idx = 0; idx < SDE_MAX_PLANES; ++idx)
  2603. psde->pipe_cfg.layout.plane_pitch[idx] <<= 1;
  2604. src.h /= 2;
  2605. src.y = DIV_ROUND_UP(src.y, 2);
  2606. src.y &= ~0x1;
  2607. }
  2608. /*
  2609. * adjust layer mixer position of the sspp in the presence
  2610. * of a partial update to the active lm origin
  2611. */
  2612. sde_crtc_get_crtc_roi(crtc->state, &crtc_roi);
  2613. dst.x -= crtc_roi->x;
  2614. dst.y -= crtc_roi->y;
  2615. /* check for UIDLE */
  2616. if (psde->pipe_hw->ops.setup_uidle)
  2617. _sde_plane_setup_uidle(crtc, psde, pstate, &src, &dst);
  2618. psde->pipe_cfg.src_rect = src;
  2619. psde->pipe_cfg.dst_rect = dst;
  2620. _sde_plane_setup_scaler(psde, pstate, fmt, false);
  2621. /* check for color fill */
  2622. psde->color_fill = (uint32_t)sde_plane_get_property(pstate,
  2623. PLANE_PROP_COLOR_FILL);
  2624. if (psde->color_fill & SDE_PLANE_COLOR_FILL_FLAG) {
  2625. /* skip remaining processing on color fill */
  2626. pstate->dirty = 0x0;
  2627. } else if (psde->pipe_hw->ops.setup_rects) {
  2628. psde->pipe_hw->ops.setup_rects(psde->pipe_hw,
  2629. &psde->pipe_cfg,
  2630. pstate->multirect_index);
  2631. }
  2632. if (psde->pipe_hw->ops.setup_pe &&
  2633. (pstate->multirect_index != SDE_SSPP_RECT_1))
  2634. psde->pipe_hw->ops.setup_pe(psde->pipe_hw,
  2635. &pstate->pixel_ext);
  2636. /**
  2637. * when programmed in multirect mode, scalar block will be
  2638. * bypassed. Still we need to update alpha and bitwidth
  2639. * ONLY for RECT0
  2640. */
  2641. if (psde->pipe_hw->ops.setup_scaler &&
  2642. pstate->multirect_index != SDE_SSPP_RECT_1) {
  2643. psde->pipe_hw->ctl = _sde_plane_get_hw_ctl(plane);
  2644. psde->pipe_hw->ops.setup_scaler(psde->pipe_hw,
  2645. &psde->pipe_cfg, &pstate->pixel_ext,
  2646. &pstate->scaler3_cfg);
  2647. }
  2648. /* update excl rect */
  2649. if (psde->pipe_hw->ops.setup_excl_rect)
  2650. psde->pipe_hw->ops.setup_excl_rect(psde->pipe_hw,
  2651. &pstate->excl_rect,
  2652. pstate->multirect_index);
  2653. if (psde->pipe_hw->ops.setup_multirect)
  2654. psde->pipe_hw->ops.setup_multirect(
  2655. psde->pipe_hw,
  2656. pstate->multirect_index,
  2657. pstate->multirect_mode);
  2658. }
  2659. static void _sde_plane_update_format_and_rects(struct sde_plane *psde,
  2660. struct sde_plane_state *pstate, const struct sde_format *fmt)
  2661. {
  2662. uint32_t src_flags = 0;
  2663. SDE_DEBUG_PLANE(psde, "rotation 0x%X\n", pstate->rotation);
  2664. if (pstate->rotation & DRM_MODE_REFLECT_X)
  2665. src_flags |= SDE_SSPP_FLIP_LR;
  2666. if (pstate->rotation & DRM_MODE_REFLECT_Y)
  2667. src_flags |= SDE_SSPP_FLIP_UD;
  2668. if (pstate->rotation & DRM_MODE_ROTATE_90)
  2669. src_flags |= SDE_SSPP_ROT_90;
  2670. /* update format */
  2671. psde->pipe_hw->ops.setup_format(psde->pipe_hw, fmt,
  2672. pstate->const_alpha_en, src_flags,
  2673. pstate->multirect_index);
  2674. if (psde->pipe_hw->ops.setup_cdp) {
  2675. struct sde_hw_pipe_cdp_cfg *cdp_cfg = &pstate->cdp_cfg;
  2676. memset(cdp_cfg, 0, sizeof(struct sde_hw_pipe_cdp_cfg));
  2677. cdp_cfg->enable = psde->catalog->perf.cdp_cfg
  2678. [SDE_PERF_CDP_USAGE_RT].rd_enable;
  2679. cdp_cfg->ubwc_meta_enable =
  2680. SDE_FORMAT_IS_UBWC(fmt);
  2681. cdp_cfg->tile_amortize_enable =
  2682. SDE_FORMAT_IS_UBWC(fmt) ||
  2683. SDE_FORMAT_IS_TILE(fmt);
  2684. cdp_cfg->preload_ahead = SDE_WB_CDP_PRELOAD_AHEAD_64;
  2685. psde->pipe_hw->ops.setup_cdp(psde->pipe_hw, cdp_cfg,
  2686. pstate->multirect_index);
  2687. }
  2688. _sde_plane_sspp_setup_sys_cache(psde, pstate,
  2689. sde_format_is_tp10_ubwc(fmt));
  2690. /* update csc */
  2691. if (SDE_FORMAT_IS_YUV(fmt))
  2692. _sde_plane_setup_csc(psde);
  2693. else
  2694. psde->csc_ptr = 0;
  2695. if (psde->pipe_hw->ops.setup_inverse_pma) {
  2696. uint32_t pma_mode = 0;
  2697. if (fmt->alpha_enable)
  2698. pma_mode = (uint32_t) sde_plane_get_property(
  2699. pstate, PLANE_PROP_INVERSE_PMA);
  2700. psde->pipe_hw->ops.setup_inverse_pma(psde->pipe_hw,
  2701. pstate->multirect_index, pma_mode);
  2702. }
  2703. if (psde->pipe_hw->ops.setup_dgm_csc)
  2704. psde->pipe_hw->ops.setup_dgm_csc(psde->pipe_hw,
  2705. pstate->multirect_index, psde->csc_usr_ptr);
  2706. }
  2707. static void _sde_plane_update_sharpening(struct sde_plane *psde)
  2708. {
  2709. psde->sharp_cfg.strength = SHARP_STRENGTH_DEFAULT;
  2710. psde->sharp_cfg.edge_thr = SHARP_EDGE_THR_DEFAULT;
  2711. psde->sharp_cfg.smooth_thr = SHARP_SMOOTH_THR_DEFAULT;
  2712. psde->sharp_cfg.noise_thr = SHARP_NOISE_THR_DEFAULT;
  2713. psde->pipe_hw->ops.setup_sharpening(psde->pipe_hw,
  2714. &psde->sharp_cfg);
  2715. }
  2716. static void _sde_plane_update_properties(struct drm_plane *plane,
  2717. struct drm_crtc *crtc, struct drm_framebuffer *fb)
  2718. {
  2719. uint32_t nplanes;
  2720. const struct msm_format *msm_fmt;
  2721. const struct sde_format *fmt;
  2722. struct sde_plane *psde;
  2723. struct drm_plane_state *state;
  2724. struct sde_plane_state *pstate;
  2725. psde = to_sde_plane(plane);
  2726. state = plane->state;
  2727. pstate = to_sde_plane_state(state);
  2728. if (!pstate) {
  2729. SDE_ERROR("invalid plane state for plane%d\n", DRMID(plane));
  2730. return;
  2731. }
  2732. msm_fmt = msm_framebuffer_format(fb);
  2733. if (!msm_fmt) {
  2734. SDE_ERROR("crtc%d plane%d: null format\n",
  2735. DRMID(crtc), DRMID(plane));
  2736. return;
  2737. }
  2738. fmt = to_sde_format(msm_fmt);
  2739. nplanes = fmt->num_planes;
  2740. /* update secure session flag */
  2741. if (pstate->dirty & SDE_PLANE_DIRTY_FB_TRANSLATION_MODE)
  2742. _sde_plane_update_secure_session(psde, pstate);
  2743. /* update roi config */
  2744. if (pstate->dirty & SDE_PLANE_DIRTY_RECTS)
  2745. _sde_plane_update_roi_config(plane, crtc, fb);
  2746. if ((pstate->dirty & SDE_PLANE_DIRTY_FORMAT ||
  2747. pstate->dirty & SDE_PLANE_DIRTY_RECTS) &&
  2748. psde->pipe_hw->ops.setup_format)
  2749. _sde_plane_update_format_and_rects(psde, pstate, fmt);
  2750. sde_color_process_plane_setup(plane);
  2751. /* update sharpening */
  2752. if ((pstate->dirty & SDE_PLANE_DIRTY_SHARPEN) &&
  2753. psde->pipe_hw->ops.setup_sharpening)
  2754. _sde_plane_update_sharpening(psde);
  2755. if (pstate->dirty & (SDE_PLANE_DIRTY_QOS | SDE_PLANE_DIRTY_RECTS |
  2756. SDE_PLANE_DIRTY_FORMAT))
  2757. _sde_plane_set_qos_lut(plane, crtc, fb);
  2758. if (plane->type != DRM_PLANE_TYPE_CURSOR) {
  2759. _sde_plane_set_qos_ctrl(plane, true, SDE_PLANE_QOS_PANIC_CTRL);
  2760. _sde_plane_set_ot_limit(plane, crtc);
  2761. if (pstate->dirty & SDE_PLANE_DIRTY_PERF)
  2762. _sde_plane_set_ts_prefill(plane, pstate);
  2763. }
  2764. if (pstate->dirty & SDE_PLANE_DIRTY_QOS)
  2765. _sde_plane_set_qos_remap(plane);
  2766. /* clear dirty */
  2767. pstate->dirty = 0x0;
  2768. }
  2769. static int sde_plane_sspp_atomic_update(struct drm_plane *plane,
  2770. struct drm_plane_state *old_state)
  2771. {
  2772. struct sde_plane *psde;
  2773. struct drm_plane_state *state;
  2774. struct sde_plane_state *pstate;
  2775. struct sde_plane_state *old_pstate;
  2776. struct drm_crtc *crtc;
  2777. struct drm_framebuffer *fb;
  2778. int idx;
  2779. int dirty_prop_flag;
  2780. bool is_rt;
  2781. if (!plane) {
  2782. SDE_ERROR("invalid plane\n");
  2783. return -EINVAL;
  2784. } else if (!plane->state) {
  2785. SDE_ERROR("invalid plane state\n");
  2786. return -EINVAL;
  2787. } else if (!old_state) {
  2788. SDE_ERROR("invalid old state\n");
  2789. return -EINVAL;
  2790. }
  2791. psde = to_sde_plane(plane);
  2792. state = plane->state;
  2793. pstate = to_sde_plane_state(state);
  2794. old_pstate = to_sde_plane_state(old_state);
  2795. crtc = state->crtc;
  2796. fb = state->fb;
  2797. if (!crtc || !fb) {
  2798. SDE_ERROR_PLANE(psde, "invalid crtc %d or fb %d\n",
  2799. !crtc, !fb);
  2800. return -EINVAL;
  2801. }
  2802. SDE_DEBUG(
  2803. "plane%d sspp:%dx%d/%4.4s/%llx/%dx%d+%d+%d/%x crtc:%dx%d+%d+%d\n",
  2804. plane->base.id,
  2805. state->fb->width, state->fb->height,
  2806. (char *) &state->fb->format->format,
  2807. state->fb->modifier,
  2808. state->src_w >> 16, state->src_h >> 16,
  2809. state->src_x >> 16, state->src_y >> 16,
  2810. pstate->rotation,
  2811. state->crtc_w, state->crtc_h,
  2812. state->crtc_x, state->crtc_y);
  2813. /* force reprogramming of all the parameters, if the flag is set */
  2814. if (psde->revalidate) {
  2815. SDE_DEBUG("plane:%d - reconfigure all the parameters\n",
  2816. plane->base.id);
  2817. pstate->dirty = SDE_PLANE_DIRTY_ALL | SDE_PLANE_DIRTY_CP;
  2818. psde->revalidate = false;
  2819. }
  2820. /* determine what needs to be refreshed */
  2821. mutex_lock(&psde->property_info.property_lock);
  2822. while ((idx = msm_property_pop_dirty(&psde->property_info,
  2823. &pstate->property_state)) >= 0) {
  2824. dirty_prop_flag = plane_prop_array[idx];
  2825. pstate->dirty |= dirty_prop_flag;
  2826. }
  2827. mutex_unlock(&psde->property_info.property_lock);
  2828. /**
  2829. * since plane_atomic_check is invoked before crtc_atomic_check
  2830. * in the commit sequence, all the parameters for updating the
  2831. * plane dirty flag will not be available during
  2832. * plane_atomic_check as some features params are updated
  2833. * in crtc_atomic_check (eg.:sDMA). So check for mode_change
  2834. * before sspp update.
  2835. */
  2836. _sde_plane_sspp_atomic_check_mode_changed(psde, state,
  2837. old_state);
  2838. /* re-program the output rects always if partial update roi changed */
  2839. if (sde_crtc_is_crtc_roi_dirty(crtc->state))
  2840. pstate->dirty |= SDE_PLANE_DIRTY_RECTS;
  2841. if (pstate->dirty & SDE_PLANE_DIRTY_RECTS)
  2842. memset(&(psde->pipe_cfg), 0, sizeof(struct sde_hw_pipe_cfg));
  2843. _sde_plane_set_scanout(plane, pstate, &psde->pipe_cfg, fb);
  2844. is_rt = sde_crtc_is_rt_client(crtc, crtc->state);
  2845. if (is_rt != psde->is_rt_pipe) {
  2846. psde->is_rt_pipe = is_rt;
  2847. pstate->dirty |= SDE_PLANE_DIRTY_QOS;
  2848. }
  2849. /* early out if nothing dirty */
  2850. if (!pstate->dirty)
  2851. return 0;
  2852. pstate->pending = true;
  2853. _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);
  2854. _sde_plane_update_properties(plane, crtc, fb);
  2855. return 0;
  2856. }
  2857. static void _sde_plane_atomic_disable(struct drm_plane *plane,
  2858. struct drm_plane_state *old_state)
  2859. {
  2860. struct sde_plane *psde;
  2861. struct drm_plane_state *state;
  2862. struct sde_plane_state *pstate;
  2863. if (!plane) {
  2864. SDE_ERROR("invalid plane\n");
  2865. return;
  2866. } else if (!plane->state) {
  2867. SDE_ERROR("invalid plane state\n");
  2868. return;
  2869. } else if (!old_state) {
  2870. SDE_ERROR("invalid old state\n");
  2871. return;
  2872. }
  2873. psde = to_sde_plane(plane);
  2874. state = plane->state;
  2875. pstate = to_sde_plane_state(state);
  2876. SDE_EVT32(DRMID(plane), is_sde_plane_virtual(plane),
  2877. pstate->multirect_mode);
  2878. pstate->pending = true;
  2879. if (is_sde_plane_virtual(plane) &&
  2880. psde->pipe_hw && psde->pipe_hw->ops.setup_multirect)
  2881. psde->pipe_hw->ops.setup_multirect(psde->pipe_hw,
  2882. SDE_SSPP_RECT_SOLO, SDE_SSPP_MULTIRECT_NONE);
  2883. }
  2884. static void sde_plane_atomic_update(struct drm_plane *plane,
  2885. struct drm_plane_state *old_state)
  2886. {
  2887. struct sde_plane *psde;
  2888. struct drm_plane_state *state;
  2889. if (!plane) {
  2890. SDE_ERROR("invalid plane\n");
  2891. return;
  2892. } else if (!plane->state) {
  2893. SDE_ERROR("invalid plane state\n");
  2894. return;
  2895. }
  2896. psde = to_sde_plane(plane);
  2897. psde->is_error = false;
  2898. state = plane->state;
  2899. SDE_DEBUG_PLANE(psde, "\n");
  2900. if (!sde_plane_enabled(state)) {
  2901. _sde_plane_atomic_disable(plane, old_state);
  2902. } else {
  2903. int ret;
  2904. ret = sde_plane_sspp_atomic_update(plane, old_state);
  2905. /* atomic_check should have ensured that this doesn't fail */
  2906. WARN_ON(ret < 0);
  2907. }
  2908. }
  2909. void sde_plane_restore(struct drm_plane *plane)
  2910. {
  2911. struct sde_plane *psde;
  2912. if (!plane || !plane->state) {
  2913. SDE_ERROR("invalid plane\n");
  2914. return;
  2915. }
  2916. psde = to_sde_plane(plane);
  2917. /*
  2918. * Revalidate is only true here if idle PC occurred and
  2919. * there is no plane state update in current commit cycle.
  2920. */
  2921. if (!psde->revalidate)
  2922. return;
  2923. SDE_DEBUG_PLANE(psde, "\n");
  2924. /* last plane state is same as current state */
  2925. sde_plane_atomic_update(plane, plane->state);
  2926. }
  2927. bool sde_plane_is_cache_required(struct drm_plane *plane,
  2928. enum sde_sys_cache_type type)
  2929. {
  2930. struct sde_plane_state *pstate;
  2931. if (!plane || !plane->state) {
  2932. SDE_ERROR("invalid plane\n");
  2933. return false;
  2934. }
  2935. pstate = to_sde_plane_state(plane->state);
  2936. /* check if llcc is required for the plane */
  2937. if (pstate->sc_cfg.rd_en && (pstate->sc_cfg.type == type))
  2938. return true;
  2939. else
  2940. return false;
  2941. }
  2942. static void _sde_plane_install_master_only_properties(struct sde_plane *psde)
  2943. {
  2944. char feature_name[256];
  2945. if (psde->pipe_sblk->maxhdeciexp) {
  2946. msm_property_install_range(&psde->property_info,
  2947. "h_decimate", 0x0, 0,
  2948. psde->pipe_sblk->maxhdeciexp, 0,
  2949. PLANE_PROP_H_DECIMATE);
  2950. }
  2951. if (psde->pipe_sblk->maxvdeciexp) {
  2952. msm_property_install_range(&psde->property_info,
  2953. "v_decimate", 0x0, 0,
  2954. psde->pipe_sblk->maxvdeciexp, 0,
  2955. PLANE_PROP_V_DECIMATE);
  2956. }
  2957. if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3)) {
  2958. msm_property_install_range(
  2959. &psde->property_info, "scaler_v2",
  2960. 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V2);
  2961. msm_property_install_blob(&psde->property_info,
  2962. "lut_ed", 0, PLANE_PROP_SCALER_LUT_ED);
  2963. msm_property_install_blob(&psde->property_info,
  2964. "lut_cir", 0,
  2965. PLANE_PROP_SCALER_LUT_CIR);
  2966. msm_property_install_blob(&psde->property_info,
  2967. "lut_sep", 0,
  2968. PLANE_PROP_SCALER_LUT_SEP);
  2969. } else if (psde->features & BIT(SDE_SSPP_SCALER_QSEED3LITE)) {
  2970. msm_property_install_range(
  2971. &psde->property_info, "scaler_v2",
  2972. 0x0, 0, ~0, 0, PLANE_PROP_SCALER_V2);
  2973. msm_property_install_blob(&psde->property_info,
  2974. "lut_sep", 0,
  2975. PLANE_PROP_SCALER_LUT_SEP);
  2976. } else if (psde->features & SDE_SSPP_SCALER) {
  2977. msm_property_install_range(
  2978. &psde->property_info, "scaler_v1", 0x0,
  2979. 0, ~0, 0, PLANE_PROP_SCALER_V1);
  2980. }
  2981. if (psde->features & BIT(SDE_SSPP_CSC) ||
  2982. psde->features & BIT(SDE_SSPP_CSC_10BIT))
  2983. msm_property_install_volatile_range(
  2984. &psde->property_info, "csc_v1", 0x0,
  2985. 0, ~0, 0, PLANE_PROP_CSC_V1);
  2986. if (psde->features & BIT(SDE_SSPP_HSIC)) {
  2987. snprintf(feature_name, sizeof(feature_name), "%s%d",
  2988. "SDE_SSPP_HUE_V",
  2989. psde->pipe_sblk->hsic_blk.version >> 16);
  2990. msm_property_install_range(&psde->property_info,
  2991. feature_name, 0, 0, 0xFFFFFFFF, 0,
  2992. PLANE_PROP_HUE_ADJUST);
  2993. snprintf(feature_name, sizeof(feature_name), "%s%d",
  2994. "SDE_SSPP_SATURATION_V",
  2995. psde->pipe_sblk->hsic_blk.version >> 16);
  2996. msm_property_install_range(&psde->property_info,
  2997. feature_name, 0, 0, 0xFFFFFFFF, 0,
  2998. PLANE_PROP_SATURATION_ADJUST);
  2999. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3000. "SDE_SSPP_VALUE_V",
  3001. psde->pipe_sblk->hsic_blk.version >> 16);
  3002. msm_property_install_range(&psde->property_info,
  3003. feature_name, 0, 0, 0xFFFFFFFF, 0,
  3004. PLANE_PROP_VALUE_ADJUST);
  3005. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3006. "SDE_SSPP_CONTRAST_V",
  3007. psde->pipe_sblk->hsic_blk.version >> 16);
  3008. msm_property_install_range(&psde->property_info,
  3009. feature_name, 0, 0, 0xFFFFFFFF, 0,
  3010. PLANE_PROP_CONTRAST_ADJUST);
  3011. }
  3012. }
  3013. static void _sde_plane_install_colorproc_properties(struct sde_plane *psde,
  3014. struct sde_kms_info *info)
  3015. {
  3016. char feature_name[256];
  3017. bool is_master = !psde->is_virtual;
  3018. if ((is_master &&
  3019. (psde->features & BIT(SDE_SSPP_INVERSE_PMA))) ||
  3020. (psde->features & BIT(SDE_SSPP_DGM_INVERSE_PMA))) {
  3021. msm_property_install_range(&psde->property_info,
  3022. "inverse_pma", 0x0, 0, 1, 0, PLANE_PROP_INVERSE_PMA);
  3023. sde_kms_info_add_keyint(info, "inverse_pma", 1);
  3024. }
  3025. if (psde->features & BIT(SDE_SSPP_DGM_CSC)) {
  3026. msm_property_install_volatile_range(
  3027. &psde->property_info, "csc_dma_v1", 0x0,
  3028. 0, ~0, 0, PLANE_PROP_CSC_DMA_V1);
  3029. sde_kms_info_add_keyint(info, "csc_dma_v1", 1);
  3030. }
  3031. if (psde->features & BIT(SDE_SSPP_MEMCOLOR)) {
  3032. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3033. "SDE_SSPP_SKIN_COLOR_V",
  3034. psde->pipe_sblk->memcolor_blk.version >> 16);
  3035. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3036. PLANE_PROP_SKIN_COLOR);
  3037. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3038. "SDE_SSPP_SKY_COLOR_V",
  3039. psde->pipe_sblk->memcolor_blk.version >> 16);
  3040. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3041. PLANE_PROP_SKY_COLOR);
  3042. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3043. "SDE_SSPP_FOLIAGE_COLOR_V",
  3044. psde->pipe_sblk->memcolor_blk.version >> 16);
  3045. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3046. PLANE_PROP_FOLIAGE_COLOR);
  3047. }
  3048. if (psde->features & BIT(SDE_SSPP_VIG_GAMUT)) {
  3049. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3050. "SDE_VIG_3D_LUT_GAMUT_V",
  3051. psde->pipe_sblk->gamut_blk.version >> 16);
  3052. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3053. PLANE_PROP_VIG_GAMUT);
  3054. }
  3055. if (psde->features & BIT(SDE_SSPP_VIG_IGC)) {
  3056. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3057. "SDE_VIG_1D_LUT_IGC_V",
  3058. psde->pipe_sblk->igc_blk[0].version >> 16);
  3059. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3060. PLANE_PROP_VIG_IGC);
  3061. }
  3062. if (psde->features & BIT(SDE_SSPP_DMA_IGC)) {
  3063. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3064. "SDE_DGM_1D_LUT_IGC_V",
  3065. psde->pipe_sblk->igc_blk[0].version >> 16);
  3066. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3067. PLANE_PROP_DMA_IGC);
  3068. }
  3069. if (psde->features & BIT(SDE_SSPP_DMA_GC)) {
  3070. snprintf(feature_name, sizeof(feature_name), "%s%d",
  3071. "SDE_DGM_1D_LUT_GC_V",
  3072. psde->pipe_sblk->gc_blk[0].version >> 16);
  3073. msm_property_install_blob(&psde->property_info, feature_name, 0,
  3074. PLANE_PROP_DMA_GC);
  3075. }
  3076. }
  3077. static void _sde_plane_setup_capabilities_blob(struct sde_plane *psde,
  3078. u32 master_plane_id, struct sde_kms_info *info,
  3079. struct sde_mdss_cfg *catalog)
  3080. {
  3081. bool is_master = !psde->is_virtual;
  3082. const struct sde_format_extended *format_list;
  3083. u32 index;
  3084. if (is_master) {
  3085. format_list = psde->pipe_sblk->format_list;
  3086. } else {
  3087. format_list = psde->pipe_sblk->virt_format_list;
  3088. sde_kms_info_add_keyint(info, "primary_smart_plane_id",
  3089. master_plane_id);
  3090. }
  3091. if (format_list) {
  3092. sde_kms_info_start(info, "pixel_formats");
  3093. while (format_list->fourcc_format) {
  3094. sde_kms_info_append_format(info,
  3095. format_list->fourcc_format,
  3096. format_list->modifier);
  3097. ++format_list;
  3098. }
  3099. sde_kms_info_stop(info);
  3100. }
  3101. if (psde->pipe_hw && psde->pipe_hw->ops.get_scaler_ver)
  3102. sde_kms_info_add_keyint(info, "scaler_step_ver",
  3103. psde->pipe_hw->ops.get_scaler_ver(psde->pipe_hw));
  3104. sde_kms_info_add_keyint(info, "max_linewidth",
  3105. psde->pipe_sblk->maxlinewidth);
  3106. sde_kms_info_add_keyint(info, "max_upscale",
  3107. psde->pipe_sblk->maxupscale);
  3108. sde_kms_info_add_keyint(info, "max_downscale",
  3109. psde->pipe_sblk->maxdwnscale);
  3110. sde_kms_info_add_keyint(info, "max_horizontal_deci",
  3111. psde->pipe_sblk->maxhdeciexp);
  3112. sde_kms_info_add_keyint(info, "max_vertical_deci",
  3113. psde->pipe_sblk->maxvdeciexp);
  3114. sde_kms_info_add_keyint(info, "max_per_pipe_bw",
  3115. psde->pipe_sblk->max_per_pipe_bw * 1000LL);
  3116. sde_kms_info_add_keyint(info, "max_per_pipe_bw_high",
  3117. psde->pipe_sblk->max_per_pipe_bw_high * 1000LL);
  3118. index = (master_plane_id == 0) ? 0 : 1;
  3119. if (catalog->has_demura &&
  3120. catalog->demura_supported[psde->pipe][index] != ~0x0) {
  3121. sde_kms_info_add_keyint(info, "demura_block", index);
  3122. sde_kms_info_add_keyint(info, "demura_pipe_id",
  3123. psde->pipe - SSPP_DMA0);
  3124. }
  3125. if (psde->features & BIT(SDE_SSPP_SEC_UI_ALLOWED))
  3126. sde_kms_info_add_keyint(info, "sec_ui_allowed", 1);
  3127. if (psde->features & BIT(SDE_SSPP_BLOCK_SEC_UI))
  3128. sde_kms_info_add_keyint(info, "block_sec_ui", 1);
  3129. if (psde->features & BIT(SDE_SSPP_TRUE_INLINE_ROT)) {
  3130. const struct sde_format_extended *inline_rot_fmt_list;
  3131. sde_kms_info_add_keyint(info, "true_inline_rot_rev",
  3132. catalog->true_inline_rot_rev);
  3133. sde_kms_info_add_keyint(info,
  3134. "true_inline_dwnscale_rt",
  3135. (int) (psde->pipe_sblk->in_rot_maxdwnscale_rt_num /
  3136. psde->pipe_sblk->in_rot_maxdwnscale_rt_denom));
  3137. sde_kms_info_add_keyint(info,
  3138. "true_inline_dwnscale_rt_numerator",
  3139. psde->pipe_sblk->in_rot_maxdwnscale_rt_num);
  3140. sde_kms_info_add_keyint(info,
  3141. "true_inline_dwnscale_rt_denominator",
  3142. psde->pipe_sblk->in_rot_maxdwnscale_rt_denom);
  3143. sde_kms_info_add_keyint(info, "true_inline_dwnscale_nrt",
  3144. psde->pipe_sblk->in_rot_maxdwnscale_nrt);
  3145. sde_kms_info_add_keyint(info, "true_inline_max_height",
  3146. psde->pipe_sblk->in_rot_maxheight);
  3147. inline_rot_fmt_list = psde->pipe_sblk->in_rot_format_list;
  3148. if (inline_rot_fmt_list) {
  3149. sde_kms_info_start(info, "inline_rot_pixel_formats");
  3150. while (inline_rot_fmt_list->fourcc_format) {
  3151. sde_kms_info_append_format(info,
  3152. inline_rot_fmt_list->fourcc_format,
  3153. inline_rot_fmt_list->modifier);
  3154. ++inline_rot_fmt_list;
  3155. }
  3156. sde_kms_info_stop(info);
  3157. }
  3158. }
  3159. }
  3160. /* helper to install properties which are common to planes and crtcs */
  3161. static void _sde_plane_install_properties(struct drm_plane *plane,
  3162. struct sde_mdss_cfg *catalog, u32 master_plane_id)
  3163. {
  3164. static const struct drm_prop_enum_list e_blend_op[] = {
  3165. {SDE_DRM_BLEND_OP_NOT_DEFINED, "not_defined"},
  3166. {SDE_DRM_BLEND_OP_OPAQUE, "opaque"},
  3167. {SDE_DRM_BLEND_OP_PREMULTIPLIED, "premultiplied"},
  3168. {SDE_DRM_BLEND_OP_COVERAGE, "coverage"},
  3169. {SDE_DRM_BLEND_OP_SKIP, "skip_blending"},
  3170. };
  3171. static const struct drm_prop_enum_list e_src_config[] = {
  3172. {SDE_DRM_DEINTERLACE, "deinterlace"}
  3173. };
  3174. static const struct drm_prop_enum_list e_fb_translation_mode[] = {
  3175. {SDE_DRM_FB_NON_SEC, "non_sec"},
  3176. {SDE_DRM_FB_SEC, "sec"},
  3177. {SDE_DRM_FB_NON_SEC_DIR_TRANS, "non_sec_direct_translation"},
  3178. {SDE_DRM_FB_SEC_DIR_TRANS, "sec_direct_translation"},
  3179. };
  3180. static const struct drm_prop_enum_list e_multirect_mode[] = {
  3181. {SDE_SSPP_MULTIRECT_NONE, "none"},
  3182. {SDE_SSPP_MULTIRECT_PARALLEL, "parallel"},
  3183. {SDE_SSPP_MULTIRECT_TIME_MX, "serial"},
  3184. };
  3185. struct sde_kms_info *info;
  3186. struct sde_plane *psde = to_sde_plane(plane);
  3187. bool is_master;
  3188. int zpos_max = 255;
  3189. int zpos_def = 0;
  3190. if (!plane || !psde) {
  3191. SDE_ERROR("invalid plane\n");
  3192. return;
  3193. } else if (!psde->pipe_hw || !psde->pipe_sblk) {
  3194. SDE_ERROR("invalid plane, pipe_hw %d pipe_sblk %d\n",
  3195. !psde->pipe_hw, !psde->pipe_sblk);
  3196. return;
  3197. } else if (!catalog) {
  3198. SDE_ERROR("invalid catalog\n");
  3199. return;
  3200. }
  3201. psde->catalog = catalog;
  3202. is_master = !psde->is_virtual;
  3203. info = kzalloc(sizeof(struct sde_kms_info), GFP_KERNEL);
  3204. if (!info) {
  3205. SDE_ERROR("failed to allocate info memory\n");
  3206. return;
  3207. }
  3208. if (sde_is_custom_client()) {
  3209. if (catalog->mixer_count &&
  3210. catalog->mixer[0].sblk->maxblendstages) {
  3211. zpos_max = catalog->mixer[0].sblk->maxblendstages - 1;
  3212. if (catalog->has_base_layer &&
  3213. (zpos_max > SDE_STAGE_MAX - 1))
  3214. zpos_max = SDE_STAGE_MAX - 1;
  3215. else if (zpos_max > SDE_STAGE_MAX - SDE_STAGE_0 - 1)
  3216. zpos_max = SDE_STAGE_MAX - SDE_STAGE_0 - 1;
  3217. }
  3218. } else if (plane->type != DRM_PLANE_TYPE_PRIMARY) {
  3219. /* reserve zpos == 0 for primary planes */
  3220. zpos_def = drm_plane_index(plane) + 1;
  3221. }
  3222. msm_property_install_range(&psde->property_info, "zpos",
  3223. 0x0, 0, zpos_max, zpos_def, PLANE_PROP_ZPOS);
  3224. msm_property_install_range(&psde->property_info, "alpha",
  3225. 0x0, 0, 255, 255, PLANE_PROP_ALPHA);
  3226. /* linux default file descriptor range on each process */
  3227. msm_property_install_range(&psde->property_info, "input_fence",
  3228. 0x0, 0, INR_OPEN_MAX, 0, PLANE_PROP_INPUT_FENCE);
  3229. if (is_master)
  3230. _sde_plane_install_master_only_properties(psde);
  3231. else
  3232. msm_property_install_enum(&psde->property_info,
  3233. "multirect_mode", 0x0, 0, e_multirect_mode,
  3234. ARRAY_SIZE(e_multirect_mode),
  3235. PLANE_PROP_MULTIRECT_MODE);
  3236. if (psde->features & BIT(SDE_SSPP_EXCL_RECT))
  3237. msm_property_install_volatile_range(&psde->property_info,
  3238. "excl_rect_v1", 0x0, 0, ~0, 0, PLANE_PROP_EXCL_RECT_V1);
  3239. sde_plane_rot_install_properties(plane, catalog);
  3240. msm_property_install_enum(&psde->property_info, "blend_op", 0x0, 0,
  3241. e_blend_op, ARRAY_SIZE(e_blend_op), PLANE_PROP_BLEND_OP);
  3242. msm_property_install_enum(&psde->property_info, "src_config", 0x0, 1,
  3243. e_src_config, ARRAY_SIZE(e_src_config), PLANE_PROP_SRC_CONFIG);
  3244. if (psde->pipe_hw->ops.setup_solidfill)
  3245. msm_property_install_range(&psde->property_info, "color_fill",
  3246. 0, 0, 0xFFFFFFFF, 0, PLANE_PROP_COLOR_FILL);
  3247. msm_property_install_range(&psde->property_info, "prefill_size", 0x0,
  3248. 0, ~0, 0, PLANE_PROP_PREFILL_SIZE);
  3249. msm_property_install_range(&psde->property_info, "prefill_time", 0x0,
  3250. 0, ~0, 0, PLANE_PROP_PREFILL_TIME);
  3251. msm_property_install_blob(&psde->property_info, "capabilities",
  3252. DRM_MODE_PROP_IMMUTABLE, PLANE_PROP_INFO);
  3253. sde_kms_info_reset(info);
  3254. _sde_plane_setup_capabilities_blob(psde, master_plane_id, info,
  3255. catalog);
  3256. _sde_plane_install_colorproc_properties(psde, info);
  3257. msm_property_set_blob(&psde->property_info, &psde->blob_info,
  3258. info->data, SDE_KMS_INFO_DATALEN(info),
  3259. PLANE_PROP_INFO);
  3260. msm_property_install_enum(&psde->property_info, "fb_translation_mode",
  3261. 0x0, 0, e_fb_translation_mode,
  3262. ARRAY_SIZE(e_fb_translation_mode),
  3263. PLANE_PROP_FB_TRANSLATION_MODE);
  3264. kfree(info);
  3265. }
  3266. static inline void _sde_plane_set_csc_v1(struct sde_plane *psde,
  3267. void __user *usr_ptr)
  3268. {
  3269. struct sde_drm_csc_v1 csc_v1;
  3270. int i;
  3271. if (!psde) {
  3272. SDE_ERROR("invalid plane\n");
  3273. return;
  3274. }
  3275. psde->csc_usr_ptr = NULL;
  3276. if (!usr_ptr) {
  3277. SDE_DEBUG_PLANE(psde, "csc data removed\n");
  3278. return;
  3279. }
  3280. if (copy_from_user(&csc_v1, usr_ptr, sizeof(csc_v1))) {
  3281. SDE_ERROR_PLANE(psde, "failed to copy csc data\n");
  3282. return;
  3283. }
  3284. /* populate from user space */
  3285. for (i = 0; i < SDE_CSC_MATRIX_COEFF_SIZE; ++i)
  3286. psde->csc_cfg.csc_mv[i] = csc_v1.ctm_coeff[i] >> 16;
  3287. for (i = 0; i < SDE_CSC_BIAS_SIZE; ++i) {
  3288. psde->csc_cfg.csc_pre_bv[i] = csc_v1.pre_bias[i];
  3289. psde->csc_cfg.csc_post_bv[i] = csc_v1.post_bias[i];
  3290. }
  3291. for (i = 0; i < SDE_CSC_CLAMP_SIZE; ++i) {
  3292. psde->csc_cfg.csc_pre_lv[i] = csc_v1.pre_clamp[i];
  3293. psde->csc_cfg.csc_post_lv[i] = csc_v1.post_clamp[i];
  3294. }
  3295. psde->csc_usr_ptr = &psde->csc_cfg;
  3296. }
  3297. static inline void _sde_plane_set_scaler_v1(struct sde_plane *psde,
  3298. struct sde_plane_state *pstate, void __user *usr)
  3299. {
  3300. struct sde_drm_scaler_v1 scale_v1;
  3301. struct sde_hw_pixel_ext *pe;
  3302. int i;
  3303. if (!psde || !pstate) {
  3304. SDE_ERROR("invalid argument(s)\n");
  3305. return;
  3306. }
  3307. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_NONE;
  3308. if (!usr) {
  3309. SDE_DEBUG_PLANE(psde, "scale data removed\n");
  3310. return;
  3311. }
  3312. if (copy_from_user(&scale_v1, usr, sizeof(scale_v1))) {
  3313. SDE_ERROR_PLANE(psde, "failed to copy scale data\n");
  3314. return;
  3315. }
  3316. /* force property to be dirty, even if the pointer didn't change */
  3317. msm_property_set_dirty(&psde->property_info,
  3318. &pstate->property_state, PLANE_PROP_SCALER_V1);
  3319. /* populate from user space */
  3320. pe = &pstate->pixel_ext;
  3321. memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
  3322. for (i = 0; i < SDE_MAX_PLANES; i++) {
  3323. pe->init_phase_x[i] = scale_v1.init_phase_x[i];
  3324. pe->phase_step_x[i] = scale_v1.phase_step_x[i];
  3325. pe->init_phase_y[i] = scale_v1.init_phase_y[i];
  3326. pe->phase_step_y[i] = scale_v1.phase_step_y[i];
  3327. pe->horz_filter[i] = scale_v1.horz_filter[i];
  3328. pe->vert_filter[i] = scale_v1.vert_filter[i];
  3329. }
  3330. for (i = 0; i < SDE_MAX_PLANES; i++) {
  3331. pe->left_ftch[i] = scale_v1.pe.left_ftch[i];
  3332. pe->right_ftch[i] = scale_v1.pe.right_ftch[i];
  3333. pe->left_rpt[i] = scale_v1.pe.left_rpt[i];
  3334. pe->right_rpt[i] = scale_v1.pe.right_rpt[i];
  3335. pe->roi_w[i] = scale_v1.pe.num_ext_pxls_lr[i];
  3336. pe->top_ftch[i] = scale_v1.pe.top_ftch[i];
  3337. pe->btm_ftch[i] = scale_v1.pe.btm_ftch[i];
  3338. pe->top_rpt[i] = scale_v1.pe.top_rpt[i];
  3339. pe->btm_rpt[i] = scale_v1.pe.btm_rpt[i];
  3340. pe->roi_h[i] = scale_v1.pe.num_ext_pxls_tb[i];
  3341. }
  3342. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_SCALER_V1;
  3343. SDE_EVT32_VERBOSE(DRMID(&psde->base));
  3344. SDE_DEBUG_PLANE(psde, "user property data copied\n");
  3345. }
  3346. static void _sde_plane_clear_predownscale_settings(
  3347. struct sde_plane_state *pstate)
  3348. {
  3349. pstate->pre_down.pre_downscale_x_0 = 0;
  3350. pstate->pre_down.pre_downscale_x_1 = 0;
  3351. pstate->pre_down.pre_downscale_y_0 = 0;
  3352. pstate->pre_down.pre_downscale_y_1 = 0;
  3353. }
  3354. static inline void _sde_plane_set_scaler_v2(struct sde_plane *psde,
  3355. struct sde_plane_state *pstate, void __user *usr)
  3356. {
  3357. struct sde_drm_scaler_v2 scale_v2;
  3358. struct sde_hw_pixel_ext *pe;
  3359. int i;
  3360. struct sde_hw_scaler3_cfg *cfg;
  3361. struct sde_hw_inline_pre_downscale_cfg *pd_cfg;
  3362. if (!psde || !pstate) {
  3363. SDE_ERROR("invalid argument(s)\n");
  3364. return;
  3365. }
  3366. cfg = &pstate->scaler3_cfg;
  3367. pd_cfg = &pstate->pre_down;
  3368. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_NONE;
  3369. if (!usr) {
  3370. SDE_DEBUG_PLANE(psde, "scale data removed\n");
  3371. cfg->enable = 0;
  3372. _sde_plane_clear_predownscale_settings(pstate);
  3373. goto end;
  3374. }
  3375. if (copy_from_user(&scale_v2, usr, sizeof(scale_v2))) {
  3376. SDE_ERROR_PLANE(psde, "failed to copy scale data\n");
  3377. return;
  3378. }
  3379. /* detach/ignore user data if 'disabled' */
  3380. if (!scale_v2.enable) {
  3381. SDE_DEBUG_PLANE(psde, "scale data removed\n");
  3382. cfg->enable = 0;
  3383. _sde_plane_clear_predownscale_settings(pstate);
  3384. goto end;
  3385. }
  3386. /* populate from user space */
  3387. sde_set_scaler_v2(cfg, &scale_v2);
  3388. if (_sde_plane_has_pre_downscale(psde)) {
  3389. pd_cfg->pre_downscale_x_0 = scale_v2.pre_downscale_x_0;
  3390. pd_cfg->pre_downscale_x_1 = scale_v2.pre_downscale_x_1;
  3391. pd_cfg->pre_downscale_y_0 = scale_v2.pre_downscale_y_0;
  3392. pd_cfg->pre_downscale_y_1 = scale_v2.pre_downscale_y_1;
  3393. }
  3394. pe = &pstate->pixel_ext;
  3395. memset(pe, 0, sizeof(struct sde_hw_pixel_ext));
  3396. for (i = 0; i < SDE_MAX_PLANES; i++) {
  3397. pe->left_ftch[i] = scale_v2.pe.left_ftch[i];
  3398. pe->right_ftch[i] = scale_v2.pe.right_ftch[i];
  3399. pe->left_rpt[i] = scale_v2.pe.left_rpt[i];
  3400. pe->right_rpt[i] = scale_v2.pe.right_rpt[i];
  3401. pe->roi_w[i] = scale_v2.pe.num_ext_pxls_lr[i];
  3402. pe->top_ftch[i] = scale_v2.pe.top_ftch[i];
  3403. pe->btm_ftch[i] = scale_v2.pe.btm_ftch[i];
  3404. pe->top_rpt[i] = scale_v2.pe.top_rpt[i];
  3405. pe->btm_rpt[i] = scale_v2.pe.btm_rpt[i];
  3406. pe->roi_h[i] = scale_v2.pe.num_ext_pxls_tb[i];
  3407. }
  3408. pstate->scaler_check_state = SDE_PLANE_SCLCHECK_SCALER_V2_CHECK;
  3409. end:
  3410. /* force property to be dirty, even if the pointer didn't change */
  3411. msm_property_set_dirty(&psde->property_info,
  3412. &pstate->property_state, PLANE_PROP_SCALER_V2);
  3413. SDE_EVT32_VERBOSE(DRMID(&psde->base), cfg->enable, cfg->de.enable,
  3414. cfg->src_width[0], cfg->src_height[0],
  3415. cfg->dst_width, cfg->dst_height);
  3416. SDE_DEBUG_PLANE(psde, "user property data copied\n");
  3417. }
  3418. static void _sde_plane_set_excl_rect_v1(struct sde_plane *psde,
  3419. struct sde_plane_state *pstate, void __user *usr_ptr)
  3420. {
  3421. struct drm_clip_rect excl_rect_v1;
  3422. if (!psde || !pstate) {
  3423. SDE_ERROR("invalid argument(s)\n");
  3424. return;
  3425. }
  3426. if (!usr_ptr) {
  3427. memset(&pstate->excl_rect, 0, sizeof(pstate->excl_rect));
  3428. SDE_DEBUG_PLANE(psde, "excl_rect data cleared\n");
  3429. return;
  3430. }
  3431. if (copy_from_user(&excl_rect_v1, usr_ptr, sizeof(excl_rect_v1))) {
  3432. SDE_ERROR_PLANE(psde, "failed to copy excl_rect data\n");
  3433. return;
  3434. }
  3435. /* populate from user space */
  3436. pstate->excl_rect.x = excl_rect_v1.x1;
  3437. pstate->excl_rect.y = excl_rect_v1.y1;
  3438. pstate->excl_rect.w = excl_rect_v1.x2 - excl_rect_v1.x1;
  3439. pstate->excl_rect.h = excl_rect_v1.y2 - excl_rect_v1.y1;
  3440. SDE_DEBUG_PLANE(psde, "excl_rect: {%d,%d,%d,%d}\n",
  3441. pstate->excl_rect.x, pstate->excl_rect.y,
  3442. pstate->excl_rect.w, pstate->excl_rect.h);
  3443. }
  3444. static int sde_plane_atomic_set_property(struct drm_plane *plane,
  3445. struct drm_plane_state *state, struct drm_property *property,
  3446. uint64_t val)
  3447. {
  3448. struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
  3449. struct sde_plane_state *pstate;
  3450. int idx, ret = -EINVAL;
  3451. SDE_DEBUG_PLANE(psde, "\n");
  3452. if (!plane) {
  3453. SDE_ERROR("invalid plane\n");
  3454. } else if (!state) {
  3455. SDE_ERROR_PLANE(psde, "invalid state\n");
  3456. } else {
  3457. pstate = to_sde_plane_state(state);
  3458. ret = msm_property_atomic_set(&psde->property_info,
  3459. &pstate->property_state, property, val);
  3460. if (!ret) {
  3461. idx = msm_property_index(&psde->property_info,
  3462. property);
  3463. switch (idx) {
  3464. case PLANE_PROP_INPUT_FENCE:
  3465. _sde_plane_set_input_fence(psde, pstate, val);
  3466. break;
  3467. case PLANE_PROP_CSC_V1:
  3468. case PLANE_PROP_CSC_DMA_V1:
  3469. _sde_plane_set_csc_v1(psde, (void __user *)val);
  3470. break;
  3471. case PLANE_PROP_SCALER_V1:
  3472. _sde_plane_set_scaler_v1(psde, pstate,
  3473. (void *)(uintptr_t)val);
  3474. break;
  3475. case PLANE_PROP_SCALER_V2:
  3476. _sde_plane_set_scaler_v2(psde, pstate,
  3477. (void *)(uintptr_t)val);
  3478. break;
  3479. case PLANE_PROP_EXCL_RECT_V1:
  3480. _sde_plane_set_excl_rect_v1(psde, pstate,
  3481. (void *)(uintptr_t)val);
  3482. break;
  3483. default:
  3484. /* nothing to do */
  3485. break;
  3486. }
  3487. }
  3488. }
  3489. SDE_DEBUG_PLANE(psde, "%s[%d] <= 0x%llx ret=%d\n",
  3490. property->name, property->base.id, val, ret);
  3491. return ret;
  3492. }
  3493. static int sde_plane_atomic_get_property(struct drm_plane *plane,
  3494. const struct drm_plane_state *state,
  3495. struct drm_property *property, uint64_t *val)
  3496. {
  3497. struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
  3498. struct sde_plane_state *pstate;
  3499. int ret = -EINVAL;
  3500. if (!plane) {
  3501. SDE_ERROR("invalid plane\n");
  3502. } else if (!state) {
  3503. SDE_ERROR("invalid state\n");
  3504. } else {
  3505. SDE_DEBUG_PLANE(psde, "\n");
  3506. pstate = to_sde_plane_state(state);
  3507. ret = msm_property_atomic_get(&psde->property_info,
  3508. &pstate->property_state, property, val);
  3509. }
  3510. return ret;
  3511. }
  3512. int sde_plane_helper_reset_custom_properties(struct drm_plane *plane,
  3513. struct drm_plane_state *plane_state)
  3514. {
  3515. struct sde_plane *psde;
  3516. struct sde_plane_state *pstate;
  3517. struct drm_property *drm_prop;
  3518. enum msm_mdp_plane_property prop_idx;
  3519. if (!plane || !plane_state) {
  3520. SDE_ERROR("invalid params\n");
  3521. return -EINVAL;
  3522. }
  3523. psde = to_sde_plane(plane);
  3524. pstate = to_sde_plane_state(plane_state);
  3525. for (prop_idx = 0; prop_idx < PLANE_PROP_COUNT; prop_idx++) {
  3526. uint64_t val = pstate->property_values[prop_idx].value;
  3527. uint64_t def;
  3528. int ret;
  3529. drm_prop = msm_property_index_to_drm_property(
  3530. &psde->property_info, prop_idx);
  3531. if (!drm_prop) {
  3532. /* not all props will be installed, based on caps */
  3533. SDE_DEBUG_PLANE(psde, "invalid property index %d\n",
  3534. prop_idx);
  3535. continue;
  3536. }
  3537. def = msm_property_get_default(&psde->property_info, prop_idx);
  3538. if (val == def)
  3539. continue;
  3540. SDE_DEBUG_PLANE(psde, "set prop %s idx %d from %llu to %llu\n",
  3541. drm_prop->name, prop_idx, val, def);
  3542. ret = sde_plane_atomic_set_property(plane, plane_state,
  3543. drm_prop, def);
  3544. if (ret) {
  3545. SDE_ERROR_PLANE(psde,
  3546. "set property failed, idx %d ret %d\n",
  3547. prop_idx, ret);
  3548. continue;
  3549. }
  3550. }
  3551. return 0;
  3552. }
  3553. static void sde_plane_destroy(struct drm_plane *plane)
  3554. {
  3555. struct sde_plane *psde = plane ? to_sde_plane(plane) : NULL;
  3556. SDE_DEBUG_PLANE(psde, "\n");
  3557. if (psde) {
  3558. _sde_plane_set_qos_ctrl(plane, false, SDE_PLANE_QOS_PANIC_CTRL);
  3559. if (psde->blob_info)
  3560. drm_property_blob_put(psde->blob_info);
  3561. msm_property_destroy(&psde->property_info);
  3562. mutex_destroy(&psde->lock);
  3563. /* this will destroy the states as well */
  3564. drm_plane_cleanup(plane);
  3565. if (psde->pipe_hw)
  3566. sde_hw_sspp_destroy(psde->pipe_hw);
  3567. kfree(psde);
  3568. }
  3569. }
  3570. void sde_plane_destroy_fb(struct drm_plane_state *state)
  3571. {
  3572. struct sde_plane_state *pstate;
  3573. if (!state) {
  3574. SDE_ERROR("invalid arg state %d\n", !state);
  3575. return;
  3576. }
  3577. pstate = to_sde_plane_state(state);
  3578. if (sde_plane_get_property(pstate, PLANE_PROP_FB_TRANSLATION_MODE) ==
  3579. SDE_DRM_FB_SEC) {
  3580. /* remove ref count for frame buffers */
  3581. if (state->fb) {
  3582. drm_framebuffer_put(state->fb);
  3583. state->fb = NULL;
  3584. }
  3585. }
  3586. }
  3587. static void sde_plane_destroy_state(struct drm_plane *plane,
  3588. struct drm_plane_state *state)
  3589. {
  3590. struct sde_plane *psde;
  3591. struct sde_plane_state *pstate;
  3592. if (!plane || !state) {
  3593. SDE_ERROR("invalid arg(s), plane %d state %d\n",
  3594. !plane, !state);
  3595. return;
  3596. }
  3597. psde = to_sde_plane(plane);
  3598. pstate = to_sde_plane_state(state);
  3599. SDE_DEBUG_PLANE(psde, "\n");
  3600. /* remove ref count for frame buffers */
  3601. if (state->fb)
  3602. drm_framebuffer_put(state->fb);
  3603. /* remove ref count for fence */
  3604. if (pstate->input_fence)
  3605. sde_sync_put(pstate->input_fence);
  3606. /* destroy value helper */
  3607. msm_property_destroy_state(&psde->property_info, pstate,
  3608. &pstate->property_state);
  3609. }
  3610. static struct drm_plane_state *
  3611. sde_plane_duplicate_state(struct drm_plane *plane)
  3612. {
  3613. struct sde_plane *psde;
  3614. struct sde_plane_state *pstate;
  3615. struct sde_plane_state *old_state;
  3616. struct drm_property *drm_prop;
  3617. uint64_t input_fence_default;
  3618. if (!plane) {
  3619. SDE_ERROR("invalid plane\n");
  3620. return NULL;
  3621. } else if (!plane->state) {
  3622. SDE_ERROR("invalid plane state\n");
  3623. return NULL;
  3624. }
  3625. old_state = to_sde_plane_state(plane->state);
  3626. psde = to_sde_plane(plane);
  3627. pstate = msm_property_alloc_state(&psde->property_info);
  3628. if (!pstate) {
  3629. SDE_ERROR_PLANE(psde, "failed to allocate state\n");
  3630. return NULL;
  3631. }
  3632. SDE_DEBUG_PLANE(psde, "\n");
  3633. /* duplicate value helper */
  3634. msm_property_duplicate_state(&psde->property_info, old_state, pstate,
  3635. &pstate->property_state, pstate->property_values);
  3636. /* clear out any input fence */
  3637. pstate->input_fence = 0;
  3638. input_fence_default = msm_property_get_default(
  3639. &psde->property_info, PLANE_PROP_INPUT_FENCE);
  3640. drm_prop = msm_property_index_to_drm_property(
  3641. &psde->property_info, PLANE_PROP_INPUT_FENCE);
  3642. if (msm_property_atomic_set(&psde->property_info,
  3643. &pstate->property_state, drm_prop,
  3644. input_fence_default))
  3645. SDE_DEBUG_PLANE(psde,
  3646. "error clearing duplicated input fence\n");
  3647. pstate->dirty = 0x0;
  3648. pstate->pending = false;
  3649. __drm_atomic_helper_plane_duplicate_state(plane, &pstate->base);
  3650. /* reset layout offset */
  3651. if (pstate->layout_offset) {
  3652. if (pstate->layout_offset > 0)
  3653. pstate->base.crtc_x += pstate->layout_offset;
  3654. pstate->layout = SDE_LAYOUT_NONE;
  3655. pstate->layout_offset = 0;
  3656. }
  3657. return &pstate->base;
  3658. }
  3659. static void sde_plane_reset(struct drm_plane *plane)
  3660. {
  3661. struct sde_plane *psde;
  3662. struct sde_plane_state *pstate;
  3663. if (!plane) {
  3664. SDE_ERROR("invalid plane\n");
  3665. return;
  3666. }
  3667. psde = to_sde_plane(plane);
  3668. SDE_DEBUG_PLANE(psde, "\n");
  3669. if (plane->state && !sde_crtc_is_reset_required(plane->state->crtc)) {
  3670. SDE_DEBUG_PLANE(psde, "avoid reset for plane\n");
  3671. return;
  3672. }
  3673. /* remove previous state, if present */
  3674. if (plane->state) {
  3675. sde_plane_destroy_state(plane, plane->state);
  3676. plane->state = 0;
  3677. }
  3678. pstate = msm_property_alloc_state(&psde->property_info);
  3679. if (!pstate) {
  3680. SDE_ERROR_PLANE(psde, "failed to allocate state\n");
  3681. return;
  3682. }
  3683. /* reset value helper */
  3684. msm_property_reset_state(&psde->property_info, pstate,
  3685. &pstate->property_state,
  3686. pstate->property_values);
  3687. pstate->base.plane = plane;
  3688. plane->state = &pstate->base;
  3689. }
  3690. u32 sde_plane_get_ubwc_error(struct drm_plane *plane)
  3691. {
  3692. u32 ubwc_error = 0;
  3693. struct sde_plane *psde;
  3694. if (!plane) {
  3695. SDE_ERROR("invalid plane\n");
  3696. return 0;
  3697. }
  3698. psde = to_sde_plane(plane);
  3699. if (!psde->is_virtual && psde->pipe_hw->ops.get_ubwc_error)
  3700. ubwc_error = psde->pipe_hw->ops.get_ubwc_error(psde->pipe_hw);
  3701. return ubwc_error;
  3702. }
  3703. void sde_plane_clear_ubwc_error(struct drm_plane *plane)
  3704. {
  3705. struct sde_plane *psde;
  3706. if (!plane) {
  3707. SDE_ERROR("invalid plane\n");
  3708. return;
  3709. }
  3710. psde = to_sde_plane(plane);
  3711. if (psde->pipe_hw->ops.clear_ubwc_error)
  3712. psde->pipe_hw->ops.clear_ubwc_error(psde->pipe_hw);
  3713. }
  3714. #ifdef CONFIG_DEBUG_FS
  3715. static ssize_t _sde_plane_danger_read(struct file *file,
  3716. char __user *buff, size_t count, loff_t *ppos)
  3717. {
  3718. struct sde_kms *kms = file->private_data;
  3719. struct sde_mdss_cfg *cfg = kms->catalog;
  3720. int len = 0;
  3721. char buf[40] = {'\0'};
  3722. if (!cfg)
  3723. return -ENODEV;
  3724. if (*ppos)
  3725. return 0; /* the end */
  3726. len = snprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl);
  3727. if (len < 0 || len >= sizeof(buf))
  3728. return 0;
  3729. if ((count < sizeof(buf)) || copy_to_user(buff, buf, len))
  3730. return -EFAULT;
  3731. *ppos += len; /* increase offset */
  3732. return len;
  3733. }
  3734. static void _sde_plane_set_danger_state(struct sde_kms *kms, bool enable)
  3735. {
  3736. struct drm_plane *plane;
  3737. drm_for_each_plane(plane, kms->dev) {
  3738. if (plane->fb && plane->state) {
  3739. sde_plane_danger_signal_ctrl(plane, enable);
  3740. SDE_DEBUG("plane:%d img:%dx%d ",
  3741. plane->base.id, plane->fb->width,
  3742. plane->fb->height);
  3743. SDE_DEBUG("src[%d,%d,%d,%d] dst[%d,%d,%d,%d]\n",
  3744. plane->state->src_x >> 16,
  3745. plane->state->src_y >> 16,
  3746. plane->state->src_w >> 16,
  3747. plane->state->src_h >> 16,
  3748. plane->state->crtc_x, plane->state->crtc_y,
  3749. plane->state->crtc_w, plane->state->crtc_h);
  3750. } else {
  3751. SDE_DEBUG("Inactive plane:%d\n", plane->base.id);
  3752. }
  3753. }
  3754. }
  3755. static ssize_t _sde_plane_danger_write(struct file *file,
  3756. const char __user *user_buf, size_t count, loff_t *ppos)
  3757. {
  3758. struct sde_kms *kms = file->private_data;
  3759. struct sde_mdss_cfg *cfg = kms->catalog;
  3760. int disable_panic;
  3761. char buf[10];
  3762. if (!cfg)
  3763. return -EFAULT;
  3764. if (count >= sizeof(buf))
  3765. return -EFAULT;
  3766. if (copy_from_user(buf, user_buf, count))
  3767. return -EFAULT;
  3768. buf[count] = 0; /* end of string */
  3769. if (kstrtoint(buf, 0, &disable_panic))
  3770. return -EFAULT;
  3771. if (disable_panic) {
  3772. /* Disable panic signal for all active pipes */
  3773. SDE_DEBUG("Disabling danger:\n");
  3774. _sde_plane_set_danger_state(kms, false);
  3775. kms->has_danger_ctrl = false;
  3776. } else {
  3777. /* Enable panic signal for all active pipes */
  3778. SDE_DEBUG("Enabling danger:\n");
  3779. kms->has_danger_ctrl = true;
  3780. _sde_plane_set_danger_state(kms, true);
  3781. }
  3782. return count;
  3783. }
  3784. static const struct file_operations sde_plane_danger_enable = {
  3785. .open = simple_open,
  3786. .read = _sde_plane_danger_read,
  3787. .write = _sde_plane_danger_write,
  3788. };
  3789. static int _sde_plane_init_debugfs(struct drm_plane *plane)
  3790. {
  3791. struct sde_plane *psde;
  3792. struct sde_kms *kms;
  3793. struct msm_drm_private *priv;
  3794. const struct sde_sspp_sub_blks *sblk = 0;
  3795. const struct sde_sspp_cfg *cfg = 0;
  3796. if (!plane || !plane->dev) {
  3797. SDE_ERROR("invalid arguments\n");
  3798. return -EINVAL;
  3799. }
  3800. priv = plane->dev->dev_private;
  3801. if (!priv || !priv->kms) {
  3802. SDE_ERROR("invalid KMS reference\n");
  3803. return -EINVAL;
  3804. }
  3805. kms = to_sde_kms(priv->kms);
  3806. psde = to_sde_plane(plane);
  3807. if (psde && psde->pipe_hw)
  3808. cfg = psde->pipe_hw->cap;
  3809. if (cfg)
  3810. sblk = cfg->sblk;
  3811. if (!sblk)
  3812. return 0;
  3813. /* create overall sub-directory for the pipe */
  3814. psde->debugfs_root =
  3815. debugfs_create_dir(psde->pipe_name,
  3816. plane->dev->primary->debugfs_root);
  3817. if (!psde->debugfs_root)
  3818. return -ENOMEM;
  3819. /* don't error check these */
  3820. debugfs_create_x32("features", 0400,
  3821. psde->debugfs_root, &psde->features);
  3822. if (cfg->features & BIT(SDE_SSPP_SCALER_QSEED3) ||
  3823. cfg->features & BIT(SDE_SSPP_SCALER_QSEED3LITE) ||
  3824. cfg->features & BIT(SDE_SSPP_SCALER_QSEED2))
  3825. debugfs_create_bool("default_scaling",
  3826. 0600,
  3827. psde->debugfs_root,
  3828. &psde->debugfs_default_scale);
  3829. if (cfg->features & BIT(SDE_SSPP_TRUE_INLINE_ROT)) {
  3830. debugfs_create_u32("in_rot_max_downscale_rt_num",
  3831. 0600,
  3832. psde->debugfs_root,
  3833. (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_rt_num);
  3834. debugfs_create_u32("in_rot_max_downscale_rt_denom",
  3835. 0600,
  3836. psde->debugfs_root,
  3837. (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_rt_denom);
  3838. debugfs_create_u32("in_rot_max_downscale_nrt",
  3839. 0600,
  3840. psde->debugfs_root,
  3841. (u32 *) &psde->pipe_sblk->in_rot_maxdwnscale_nrt);
  3842. debugfs_create_u32("in_rot_max_height",
  3843. 0600,
  3844. psde->debugfs_root,
  3845. (u32 *) &psde->pipe_sblk->in_rot_maxheight);
  3846. }
  3847. debugfs_create_u32("xin_id",
  3848. 0400,
  3849. psde->debugfs_root,
  3850. (u32 *) &cfg->xin_id);
  3851. debugfs_create_x32("creq_vblank",
  3852. 0600,
  3853. psde->debugfs_root,
  3854. (u32 *) &sblk->creq_vblank);
  3855. debugfs_create_x32("danger_vblank",
  3856. 0600,
  3857. psde->debugfs_root,
  3858. (u32 *) &sblk->danger_vblank);
  3859. debugfs_create_file("disable_danger",
  3860. 0600,
  3861. psde->debugfs_root,
  3862. kms, &sde_plane_danger_enable);
  3863. return 0;
  3864. }
  3865. static void _sde_plane_destroy_debugfs(struct drm_plane *plane)
  3866. {
  3867. struct sde_plane *psde;
  3868. if (!plane)
  3869. return;
  3870. psde = to_sde_plane(plane);
  3871. debugfs_remove_recursive(psde->debugfs_root);
  3872. }
  3873. #else
  3874. static int _sde_plane_init_debugfs(struct drm_plane *plane)
  3875. {
  3876. return 0;
  3877. }
  3878. static void _sde_plane_destroy_debugfs(struct drm_plane *plane)
  3879. {
  3880. }
  3881. #endif
  3882. static int sde_plane_late_register(struct drm_plane *plane)
  3883. {
  3884. return _sde_plane_init_debugfs(plane);
  3885. }
  3886. static void sde_plane_early_unregister(struct drm_plane *plane)
  3887. {
  3888. _sde_plane_destroy_debugfs(plane);
  3889. }
  3890. static const struct drm_plane_funcs sde_plane_funcs = {
  3891. .update_plane = drm_atomic_helper_update_plane,
  3892. .disable_plane = drm_atomic_helper_disable_plane,
  3893. .destroy = sde_plane_destroy,
  3894. .atomic_set_property = sde_plane_atomic_set_property,
  3895. .atomic_get_property = sde_plane_atomic_get_property,
  3896. .reset = sde_plane_reset,
  3897. .atomic_duplicate_state = sde_plane_duplicate_state,
  3898. .atomic_destroy_state = sde_plane_destroy_state,
  3899. .late_register = sde_plane_late_register,
  3900. .early_unregister = sde_plane_early_unregister,
  3901. };
  3902. static const struct drm_plane_helper_funcs sde_plane_helper_funcs = {
  3903. .prepare_fb = sde_plane_prepare_fb,
  3904. .cleanup_fb = sde_plane_cleanup_fb,
  3905. .atomic_check = sde_plane_atomic_check,
  3906. .atomic_update = sde_plane_atomic_update,
  3907. };
  3908. enum sde_sspp sde_plane_pipe(struct drm_plane *plane)
  3909. {
  3910. return plane ? to_sde_plane(plane)->pipe : SSPP_NONE;
  3911. }
  3912. bool is_sde_plane_virtual(struct drm_plane *plane)
  3913. {
  3914. return plane ? to_sde_plane(plane)->is_virtual : false;
  3915. }
  3916. /* initialize plane */
  3917. struct drm_plane *sde_plane_init(struct drm_device *dev,
  3918. uint32_t pipe, bool primary_plane,
  3919. unsigned long possible_crtcs, u32 master_plane_id)
  3920. {
  3921. struct drm_plane *plane = NULL, *master_plane = NULL;
  3922. const struct sde_format_extended *format_list;
  3923. struct sde_plane *psde;
  3924. struct msm_drm_private *priv;
  3925. struct sde_kms *kms;
  3926. enum drm_plane_type type;
  3927. int ret = -EINVAL;
  3928. if (!dev) {
  3929. SDE_ERROR("[%u]device is NULL\n", pipe);
  3930. goto exit;
  3931. }
  3932. priv = dev->dev_private;
  3933. if (!priv) {
  3934. SDE_ERROR("[%u]private data is NULL\n", pipe);
  3935. goto exit;
  3936. }
  3937. if (!priv->kms) {
  3938. SDE_ERROR("[%u]invalid KMS reference\n", pipe);
  3939. goto exit;
  3940. }
  3941. kms = to_sde_kms(priv->kms);
  3942. if (!kms->catalog) {
  3943. SDE_ERROR("[%u]invalid catalog reference\n", pipe);
  3944. goto exit;
  3945. }
  3946. /* create and zero local structure */
  3947. psde = kzalloc(sizeof(*psde), GFP_KERNEL);
  3948. if (!psde) {
  3949. SDE_ERROR("[%u]failed to allocate local plane struct\n", pipe);
  3950. ret = -ENOMEM;
  3951. goto exit;
  3952. }
  3953. /* cache local stuff for later */
  3954. plane = &psde->base;
  3955. psde->pipe = pipe;
  3956. psde->is_virtual = (master_plane_id != 0);
  3957. INIT_LIST_HEAD(&psde->mplane_list);
  3958. master_plane = drm_plane_find(dev, NULL, master_plane_id);
  3959. if (master_plane) {
  3960. struct sde_plane *mpsde = to_sde_plane(master_plane);
  3961. list_add_tail(&psde->mplane_list, &mpsde->mplane_list);
  3962. }
  3963. /* initialize underlying h/w driver */
  3964. psde->pipe_hw = sde_hw_sspp_init(pipe, kms->mmio, kms->catalog,
  3965. psde->is_virtual);
  3966. if (IS_ERR(psde->pipe_hw)) {
  3967. SDE_ERROR("[%u]SSPP init failed\n", pipe);
  3968. ret = PTR_ERR(psde->pipe_hw);
  3969. goto clean_plane;
  3970. } else if (!psde->pipe_hw->cap || !psde->pipe_hw->cap->sblk) {
  3971. SDE_ERROR("[%u]SSPP init returned invalid cfg\n", pipe);
  3972. goto clean_sspp;
  3973. }
  3974. /* cache features mask for later */
  3975. psde->features = psde->pipe_hw->cap->features;
  3976. psde->perf_features = psde->pipe_hw->cap->perf_features;
  3977. psde->pipe_sblk = psde->pipe_hw->cap->sblk;
  3978. if (!psde->pipe_sblk) {
  3979. SDE_ERROR("[%u]invalid sblk\n", pipe);
  3980. goto clean_sspp;
  3981. }
  3982. if (psde->is_virtual)
  3983. format_list = psde->pipe_sblk->virt_format_list;
  3984. else
  3985. format_list = psde->pipe_sblk->format_list;
  3986. psde->nformats = sde_populate_formats(format_list,
  3987. psde->formats,
  3988. 0,
  3989. ARRAY_SIZE(psde->formats));
  3990. if (!psde->nformats) {
  3991. SDE_ERROR("[%u]no valid formats for plane\n", pipe);
  3992. goto clean_sspp;
  3993. }
  3994. if (psde->features & BIT(SDE_SSPP_CURSOR))
  3995. type = DRM_PLANE_TYPE_CURSOR;
  3996. else if (primary_plane)
  3997. type = DRM_PLANE_TYPE_PRIMARY;
  3998. else
  3999. type = DRM_PLANE_TYPE_OVERLAY;
  4000. ret = drm_universal_plane_init(dev, plane, 0xff, &sde_plane_funcs,
  4001. psde->formats, psde->nformats,
  4002. NULL, type, NULL);
  4003. if (ret)
  4004. goto clean_sspp;
  4005. /* Populate static array of plane property flags */
  4006. _sde_plane_map_prop_to_dirty_bits();
  4007. /* success! finalize initialization */
  4008. drm_plane_helper_add(plane, &sde_plane_helper_funcs);
  4009. msm_property_init(&psde->property_info, &plane->base, dev,
  4010. priv->plane_property, psde->property_data,
  4011. PLANE_PROP_COUNT, PLANE_PROP_BLOBCOUNT,
  4012. sizeof(struct sde_plane_state));
  4013. _sde_plane_install_properties(plane, kms->catalog, master_plane_id);
  4014. /* save user friendly pipe name for later */
  4015. snprintf(psde->pipe_name, SDE_NAME_SIZE, "plane%u", plane->base.id);
  4016. mutex_init(&psde->lock);
  4017. SDE_DEBUG("%s created for pipe:%u id:%u master:%u\n", psde->pipe_name,
  4018. pipe, plane->base.id, master_plane_id);
  4019. return plane;
  4020. clean_sspp:
  4021. if (psde && psde->pipe_hw)
  4022. sde_hw_sspp_destroy(psde->pipe_hw);
  4023. clean_plane:
  4024. kfree(psde);
  4025. exit:
  4026. return ERR_PTR(ret);
  4027. }