hal_rx.h 98 KB

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  1. /*
  2. * Copyright (c) 2016-2020 The Linux Foundation. All rights reserved.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for
  5. * any purpose with or without fee is hereby granted, provided that the
  6. * above copyright notice and this permission notice appear in all
  7. * copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
  10. * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
  11. * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
  12. * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
  13. * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
  14. * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
  15. * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
  16. * PERFORMANCE OF THIS SOFTWARE.
  17. */
  18. #ifndef _HAL_RX_H_
  19. #define _HAL_RX_H_
  20. #include <hal_api.h>
  21. #define HAL_RX_OFFSET(block, field) block##_##field##_OFFSET
  22. #define HAL_RX_LSB(block, field) block##_##field##_LSB
  23. #define HAL_RX_MASk(block, field) block##_##field##_MASK
  24. #define HAL_RX_GET(_ptr, block, field) \
  25. (((*((volatile uint32_t *)_ptr + (HAL_RX_OFFSET(block, field)>>2))) & \
  26. HAL_RX_MASk(block, field)) >> \
  27. HAL_RX_LSB(block, field))
  28. #ifdef NO_RX_PKT_HDR_TLV
  29. /* RX_BUFFER_SIZE = 1536 data bytes + 256 RX TLV bytes. We are avoiding
  30. * 128 bytes of RX_PKT_HEADER_TLV.
  31. */
  32. #define RX_BUFFER_SIZE 1792
  33. #else
  34. /* RX_BUFFER_SIZE = 1536 data bytes + 384 RX TLV bytes + some spare bytes */
  35. #define RX_BUFFER_SIZE 2048
  36. #endif
  37. /* HAL_RX_NON_QOS_TID = NON_QOS_TID which is 16 */
  38. #define HAL_RX_NON_QOS_TID 16
  39. enum {
  40. HAL_HW_RX_DECAP_FORMAT_RAW = 0,
  41. HAL_HW_RX_DECAP_FORMAT_NWIFI,
  42. HAL_HW_RX_DECAP_FORMAT_ETH2,
  43. HAL_HW_RX_DECAP_FORMAT_8023,
  44. };
  45. /**
  46. * struct hal_wbm_err_desc_info: structure to hold wbm error codes and reasons
  47. *
  48. * @reo_psh_rsn: REO push reason
  49. * @reo_err_code: REO Error code
  50. * @rxdma_psh_rsn: RXDMA push reason
  51. * @rxdma_err_code: RXDMA Error code
  52. * @reserved_1: Reserved bits
  53. * @wbm_err_src: WBM error source
  54. * @pool_id: pool ID, indicates which rxdma pool
  55. * @reserved_2: Reserved bits
  56. */
  57. struct hal_wbm_err_desc_info {
  58. uint16_t reo_psh_rsn:2,
  59. reo_err_code:5,
  60. rxdma_psh_rsn:2,
  61. rxdma_err_code:5,
  62. reserved_1:2;
  63. uint8_t wbm_err_src:3,
  64. pool_id:2,
  65. reserved_2:3;
  66. };
  67. /**
  68. * enum hal_reo_error_code: Enum which encapsulates "reo_push_reason"
  69. *
  70. * @ HAL_REO_ERROR_DETECTED: Packets arrived because of an error detected
  71. * @ HAL_REO_ROUTING_INSTRUCTION: Packets arrived because of REO routing
  72. */
  73. enum hal_reo_error_status {
  74. HAL_REO_ERROR_DETECTED = 0,
  75. HAL_REO_ROUTING_INSTRUCTION = 1,
  76. };
  77. /**
  78. * @msdu_flags: [0] first_msdu_in_mpdu
  79. * [1] last_msdu_in_mpdu
  80. * [2] msdu_continuation - MSDU spread across buffers
  81. * [23] sa_is_valid - SA match in peer table
  82. * [24] sa_idx_timeout - Timeout while searching for SA match
  83. * [25] da_is_valid - Used to identtify intra-bss forwarding
  84. * [26] da_is_MCBC
  85. * [27] da_idx_timeout - Timeout while searching for DA match
  86. *
  87. */
  88. struct hal_rx_msdu_desc_info {
  89. uint32_t msdu_flags;
  90. uint16_t msdu_len; /* 14 bits for length */
  91. };
  92. /**
  93. * enum hal_rx_msdu_desc_flags: Enum for flags in MSDU_DESC_INFO
  94. *
  95. * @ HAL_MSDU_F_FIRST_MSDU_IN_MPDU: First MSDU in MPDU
  96. * @ HAL_MSDU_F_LAST_MSDU_IN_MPDU: Last MSDU in MPDU
  97. * @ HAL_MSDU_F_MSDU_CONTINUATION: MSDU continuation
  98. * @ HAL_MSDU_F_SA_IS_VALID: Found match for SA in AST
  99. * @ HAL_MSDU_F_SA_IDX_TIMEOUT: AST search for SA timed out
  100. * @ HAL_MSDU_F_DA_IS_VALID: Found match for DA in AST
  101. * @ HAL_MSDU_F_DA_IS_MCBC: DA is MC/BC address
  102. * @ HAL_MSDU_F_DA_IDX_TIMEOUT: AST search for DA timed out
  103. */
  104. enum hal_rx_msdu_desc_flags {
  105. HAL_MSDU_F_FIRST_MSDU_IN_MPDU = (0x1 << 0),
  106. HAL_MSDU_F_LAST_MSDU_IN_MPDU = (0x1 << 1),
  107. HAL_MSDU_F_MSDU_CONTINUATION = (0x1 << 2),
  108. HAL_MSDU_F_SA_IS_VALID = (0x1 << 23),
  109. HAL_MSDU_F_SA_IDX_TIMEOUT = (0x1 << 24),
  110. HAL_MSDU_F_DA_IS_VALID = (0x1 << 25),
  111. HAL_MSDU_F_DA_IS_MCBC = (0x1 << 26),
  112. HAL_MSDU_F_DA_IDX_TIMEOUT = (0x1 << 27)
  113. };
  114. /*
  115. * @msdu_count: no. of msdus in the MPDU
  116. * @mpdu_seq: MPDU sequence number
  117. * @mpdu_flags [0] Fragment flag
  118. * [1] MPDU_retry_bit
  119. * [2] AMPDU flag
  120. * [3] raw_ampdu
  121. * @peer_meta_data: Upper bits containing peer id, vdev id
  122. */
  123. struct hal_rx_mpdu_desc_info {
  124. uint16_t msdu_count;
  125. uint16_t mpdu_seq; /* 12 bits for length */
  126. uint32_t mpdu_flags;
  127. uint32_t peer_meta_data; /* sw progamed meta-data:MAC Id & peer Id */
  128. };
  129. /**
  130. * enum hal_rx_mpdu_desc_flags: Enum for flags in MPDU_DESC_INFO
  131. *
  132. * @ HAL_MPDU_F_FRAGMENT: Fragmented MPDU (802.11 fragemtation)
  133. * @ HAL_MPDU_F_RETRY_BIT: Retry bit is set in FC of MPDU
  134. * @ HAL_MPDU_F_AMPDU_FLAG: MPDU received as part of A-MPDU
  135. * @ HAL_MPDU_F_RAW_AMPDU: MPDU is a Raw MDPU
  136. */
  137. enum hal_rx_mpdu_desc_flags {
  138. HAL_MPDU_F_FRAGMENT = (0x1 << 20),
  139. HAL_MPDU_F_RETRY_BIT = (0x1 << 21),
  140. HAL_MPDU_F_AMPDU_FLAG = (0x1 << 22),
  141. HAL_MPDU_F_RAW_AMPDU = (0x1 << 30)
  142. };
  143. /**
  144. * enum hal_rx_ret_buf_manager: Enum for return_buffer_manager field in
  145. * BUFFER_ADDR_INFO structure
  146. *
  147. * @ HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST: Buffer returned to WBM idle buffer list
  148. * @ HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST: Descriptor returned to WBM idle
  149. * descriptor list
  150. * @ HAL_RX_BUF_RBM_FW_BM: Buffer returned to FW
  151. * @ HAL_RX_BUF_RBM_SW0_BM: For Tx completion -- returned to host
  152. * @ HAL_RX_BUF_RBM_SW1_BM: For Tx completion -- returned to host
  153. * @ HAL_RX_BUF_RBM_SW2_BM: For Tx completion -- returned to host
  154. * @ HAL_RX_BUF_RBM_SW3_BM: For Rx release -- returned to host
  155. */
  156. enum hal_rx_ret_buf_manager {
  157. HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST = 0,
  158. HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST = 1,
  159. HAL_RX_BUF_RBM_FW_BM = 2,
  160. HAL_RX_BUF_RBM_SW0_BM = 3,
  161. HAL_RX_BUF_RBM_SW1_BM = 4,
  162. HAL_RX_BUF_RBM_SW2_BM = 5,
  163. HAL_RX_BUF_RBM_SW3_BM = 6,
  164. };
  165. /*
  166. * Given the offset of a field in bytes, returns uint8_t *
  167. */
  168. #define _OFFSET_TO_BYTE_PTR(_ptr, _off_in_bytes) \
  169. (((uint8_t *)(_ptr)) + (_off_in_bytes))
  170. /*
  171. * Given the offset of a field in bytes, returns uint32_t *
  172. */
  173. #define _OFFSET_TO_WORD_PTR(_ptr, _off_in_bytes) \
  174. (((uint32_t *)(_ptr)) + ((_off_in_bytes) >> 2))
  175. #define _HAL_MS(_word, _mask, _shift) \
  176. (((_word) & (_mask)) >> (_shift))
  177. /*
  178. * macro to set the LSW of the nbuf data physical address
  179. * to the rxdma ring entry
  180. */
  181. #define HAL_RXDMA_PADDR_LO_SET(buff_addr_info, paddr_lo) \
  182. ((*(((unsigned int *) buff_addr_info) + \
  183. (BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET >> 2))) = \
  184. (paddr_lo << BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB) & \
  185. BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK)
  186. /*
  187. * macro to set the LSB of MSW of the nbuf data physical address
  188. * to the rxdma ring entry
  189. */
  190. #define HAL_RXDMA_PADDR_HI_SET(buff_addr_info, paddr_hi) \
  191. ((*(((unsigned int *) buff_addr_info) + \
  192. (BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET >> 2))) = \
  193. (paddr_hi << BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB) & \
  194. BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK)
  195. /*
  196. * macro to set the cookie into the rxdma ring entry
  197. */
  198. #define HAL_RXDMA_COOKIE_SET(buff_addr_info, cookie) \
  199. ((*(((unsigned int *) buff_addr_info) + \
  200. (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) &= \
  201. ~BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK); \
  202. ((*(((unsigned int *) buff_addr_info) + \
  203. (BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET >> 2))) |= \
  204. (cookie << BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB) & \
  205. BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK)
  206. /*
  207. * macro to set the manager into the rxdma ring entry
  208. */
  209. #define HAL_RXDMA_MANAGER_SET(buff_addr_info, manager) \
  210. ((*(((unsigned int *) buff_addr_info) + \
  211. (BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET >> 2))) &= \
  212. ~BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK); \
  213. ((*(((unsigned int *) buff_addr_info) + \
  214. (BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET >> 2))) |= \
  215. (manager << BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB) & \
  216. BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK)
  217. #define HAL_RX_ERROR_STATUS_GET(reo_desc) \
  218. (_HAL_MS((*_OFFSET_TO_WORD_PTR(reo_desc, \
  219. REO_DESTINATION_RING_7_REO_PUSH_REASON_OFFSET)),\
  220. REO_DESTINATION_RING_7_REO_PUSH_REASON_MASK, \
  221. REO_DESTINATION_RING_7_REO_PUSH_REASON_LSB))
  222. #define HAL_RX_BUF_COOKIE_GET(buff_addr_info) \
  223. (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \
  224. BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_OFFSET)), \
  225. BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK, \
  226. BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB))
  227. #define HAL_RX_BUFFER_ADDR_39_32_GET(buff_addr_info) \
  228. (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \
  229. BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET)), \
  230. BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK, \
  231. BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB))
  232. #define HAL_RX_BUFFER_ADDR_31_0_GET(buff_addr_info) \
  233. (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \
  234. BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET)), \
  235. BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK, \
  236. BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB))
  237. #define HAL_RX_BUF_RBM_GET(buff_addr_info) \
  238. (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \
  239. BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_OFFSET)),\
  240. BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK, \
  241. BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB))
  242. /* TODO: Convert the following structure fields accesseses to offsets */
  243. #define HAL_RX_REO_BUFFER_ADDR_39_32_GET(reo_desc) \
  244. (HAL_RX_BUFFER_ADDR_39_32_GET(& \
  245. (((struct reo_destination_ring *) \
  246. reo_desc)->buf_or_link_desc_addr_info)))
  247. #define HAL_RX_REO_BUFFER_ADDR_31_0_GET(reo_desc) \
  248. (HAL_RX_BUFFER_ADDR_31_0_GET(& \
  249. (((struct reo_destination_ring *) \
  250. reo_desc)->buf_or_link_desc_addr_info)))
  251. #define HAL_RX_REO_BUF_COOKIE_GET(reo_desc) \
  252. (HAL_RX_BUF_COOKIE_GET(& \
  253. (((struct reo_destination_ring *) \
  254. reo_desc)->buf_or_link_desc_addr_info)))
  255. #define HAL_RX_MPDU_SEQUENCE_NUMBER_GET(mpdu_info_ptr) \
  256. ((mpdu_info_ptr \
  257. [RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_OFFSET >> 2] & \
  258. RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_MASK) >> \
  259. RX_MPDU_DESC_INFO_0_MPDU_SEQUENCE_NUMBER_LSB)
  260. #define HAL_RX_MPDU_DESC_PEER_META_DATA_GET(mpdu_info_ptr) \
  261. ((mpdu_info_ptr \
  262. [RX_MPDU_DESC_INFO_1_PEER_META_DATA_OFFSET >> 2] & \
  263. RX_MPDU_DESC_INFO_1_PEER_META_DATA_MASK) >> \
  264. RX_MPDU_DESC_INFO_1_PEER_META_DATA_LSB)
  265. #define HAL_RX_MPDU_MSDU_COUNT_GET(mpdu_info_ptr) \
  266. ((mpdu_info_ptr[RX_MPDU_DESC_INFO_0_MSDU_COUNT_OFFSET >> 2] & \
  267. RX_MPDU_DESC_INFO_0_MSDU_COUNT_MASK) >> \
  268. RX_MPDU_DESC_INFO_0_MSDU_COUNT_LSB)
  269. #define HAL_RX_MPDU_FRAGMENT_FLAG_GET(mpdu_info_ptr) \
  270. (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_OFFSET >> 2] & \
  271. RX_MPDU_DESC_INFO_0_FRAGMENT_FLAG_MASK)
  272. #define HAL_RX_MPDU_RETRY_BIT_GET(mpdu_info_ptr) \
  273. (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_OFFSET >> 2] & \
  274. RX_MPDU_DESC_INFO_0_MPDU_RETRY_BIT_MASK)
  275. #define HAL_RX_MPDU_AMPDU_FLAG_GET(mpdu_info_ptr) \
  276. (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_AMPDU_FLAG_OFFSET >> 2] & \
  277. RX_MPDU_DESC_INFO_0_AMPDU_FLAG_MASK)
  278. #define HAL_RX_MPDU_RAW_MPDU_GET(mpdu_info_ptr) \
  279. (mpdu_info_ptr[RX_MPDU_DESC_INFO_0_RAW_MPDU_OFFSET >> 2] & \
  280. RX_MPDU_DESC_INFO_0_RAW_MPDU_MASK)
  281. #define HAL_RX_MPDU_FLAGS_GET(mpdu_info_ptr) \
  282. (HAL_RX_MPDU_FRAGMENT_FLAG_GET(mpdu_info_ptr) | \
  283. HAL_RX_MPDU_RETRY_BIT_GET(mpdu_info_ptr) | \
  284. HAL_RX_MPDU_AMPDU_FLAG_GET(mpdu_info_ptr) | \
  285. HAL_RX_MPDU_RAW_MPDU_GET(mpdu_info_ptr))
  286. #define HAL_RX_MSDU_PKT_LENGTH_GET(msdu_info_ptr) \
  287. (_HAL_MS((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  288. RX_MSDU_DESC_INFO_0_MSDU_LENGTH_OFFSET)), \
  289. RX_MSDU_DESC_INFO_0_MSDU_LENGTH_MASK, \
  290. RX_MSDU_DESC_INFO_0_MSDU_LENGTH_LSB))
  291. /*
  292. * NOTE: None of the following _GET macros need a right
  293. * shift by the corresponding _LSB. This is because, they are
  294. * finally taken and "OR'ed" into a single word again.
  295. */
  296. #define HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_SET(msdu_info_ptr, val) \
  297. ((*(((uint32_t *)msdu_info_ptr) + \
  298. (RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_OFFSET >> 2))) |= \
  299. (val << RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_LSB) & \
  300. RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_MASK)
  301. #define HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_info_ptr, val) \
  302. ((*(((uint32_t *)msdu_info_ptr) + \
  303. (RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_OFFSET >> 2))) |= \
  304. (val << RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_LSB) & \
  305. RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_MASK)
  306. #define HAL_RX_MSDU_CONTINUATION_FLAG_SET(msdu_info_ptr, val) \
  307. ((*(((uint32_t *)msdu_info_ptr) + \
  308. (RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_OFFSET >> 2))) |= \
  309. (val << RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_LSB) & \
  310. RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK)
  311. #define HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) \
  312. ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  313. RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_OFFSET)) & \
  314. RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_MASK)
  315. #define HAL_RX_LAST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) \
  316. ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  317. RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_OFFSET)) & \
  318. RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_MASK)
  319. #define HAL_RX_MSDU_CONTINUATION_FLAG_GET(msdu_info_ptr) \
  320. ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  321. RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_OFFSET)) & \
  322. RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK)
  323. #define HAL_RX_MSDU_REO_DST_IND_GET(msdu_info_ptr) \
  324. (_HAL_MS((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  325. RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_OFFSET)), \
  326. RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_MASK, \
  327. RX_MSDU_DESC_INFO_0_REO_DESTINATION_INDICATION_LSB))
  328. #define HAL_RX_MSDU_SA_IS_VALID_FLAG_GET(msdu_info_ptr) \
  329. ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  330. RX_MSDU_DESC_INFO_0_SA_IS_VALID_OFFSET)) & \
  331. RX_MSDU_DESC_INFO_0_SA_IS_VALID_MASK)
  332. #define HAL_RX_MSDU_SA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr) \
  333. ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  334. RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_OFFSET)) & \
  335. RX_MSDU_DESC_INFO_0_SA_IDX_TIMEOUT_MASK)
  336. #define HAL_RX_MSDU_DA_IS_VALID_FLAG_GET(msdu_info_ptr) \
  337. ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  338. RX_MSDU_DESC_INFO_0_DA_IS_VALID_OFFSET)) & \
  339. RX_MSDU_DESC_INFO_0_DA_IS_VALID_MASK)
  340. #define HAL_RX_MSDU_DA_IS_MCBC_FLAG_GET(msdu_info_ptr) \
  341. ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  342. RX_MSDU_DESC_INFO_0_DA_IS_MCBC_OFFSET)) & \
  343. RX_MSDU_DESC_INFO_0_DA_IS_MCBC_MASK)
  344. #define HAL_RX_MSDU_DA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr) \
  345. ((*_OFFSET_TO_WORD_PTR(msdu_info_ptr, \
  346. RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_OFFSET)) & \
  347. RX_MSDU_DESC_INFO_0_DA_IDX_TIMEOUT_MASK)
  348. #define HAL_RX_MSDU_FLAGS_GET(msdu_info_ptr) \
  349. (HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) | \
  350. HAL_RX_LAST_MSDU_IN_MPDU_FLAG_GET(msdu_info_ptr) | \
  351. HAL_RX_MSDU_CONTINUATION_FLAG_GET(msdu_info_ptr) | \
  352. HAL_RX_MSDU_SA_IS_VALID_FLAG_GET(msdu_info_ptr) | \
  353. HAL_RX_MSDU_SA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr) | \
  354. HAL_RX_MSDU_DA_IS_VALID_FLAG_GET(msdu_info_ptr) | \
  355. HAL_RX_MSDU_DA_IS_MCBC_FLAG_GET(msdu_info_ptr) | \
  356. HAL_RX_MSDU_DA_IDX_TIMEOUT_FLAG_GET(msdu_info_ptr))
  357. #define HAL_RX_MPDU_ENCRYPT_TYPE_GET(_rx_mpdu_info) \
  358. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  359. RX_MPDU_INFO_3_ENCRYPT_TYPE_OFFSET)), \
  360. RX_MPDU_INFO_3_ENCRYPT_TYPE_MASK, \
  361. RX_MPDU_INFO_3_ENCRYPT_TYPE_LSB))
  362. #define HAL_RX_FLD_SET(_ptr, _wrd, _field, _val) \
  363. (*(uint32_t *)(((uint8_t *)_ptr) + \
  364. _wrd ## _ ## _field ## _OFFSET) |= \
  365. ((_val << _wrd ## _ ## _field ## _LSB) & \
  366. _wrd ## _ ## _field ## _MASK))
  367. #define HAL_RX_UNIFORM_HDR_SET(_rx_msdu_link, _field, _val) \
  368. HAL_RX_FLD_SET(_rx_msdu_link, UNIFORM_DESCRIPTOR_HEADER_0, \
  369. _field, _val)
  370. #define HAL_RX_MSDU_DESC_INFO_SET(_msdu_info_ptr, _field, _val) \
  371. HAL_RX_FLD_SET(_msdu_info_ptr, RX_MSDU_DESC_INFO_0, \
  372. _field, _val)
  373. #define HAL_RX_MPDU_DESC_INFO_SET(_mpdu_info_ptr, _field, _val) \
  374. HAL_RX_FLD_SET(_mpdu_info_ptr, RX_MPDU_DESC_INFO_0, \
  375. _field, _val)
  376. static inline void hal_rx_mpdu_desc_info_get(void *desc_addr,
  377. struct hal_rx_mpdu_desc_info *mpdu_desc_info)
  378. {
  379. struct reo_destination_ring *reo_dst_ring;
  380. uint32_t *mpdu_info;
  381. reo_dst_ring = (struct reo_destination_ring *) desc_addr;
  382. mpdu_info = (uint32_t *)&reo_dst_ring->rx_mpdu_desc_info_details;
  383. mpdu_desc_info->msdu_count = HAL_RX_MPDU_MSDU_COUNT_GET(mpdu_info);
  384. mpdu_desc_info->mpdu_seq = HAL_RX_MPDU_SEQUENCE_NUMBER_GET(mpdu_info);
  385. mpdu_desc_info->mpdu_flags = HAL_RX_MPDU_FLAGS_GET(mpdu_info);
  386. mpdu_desc_info->peer_meta_data =
  387. HAL_RX_MPDU_DESC_PEER_META_DATA_GET(mpdu_info);
  388. }
  389. /*
  390. * @ hal_rx_msdu_desc_info_get: Gets the flags related to MSDU desciptor.
  391. * @ Specifically flags needed are:
  392. * @ first_msdu_in_mpdu, last_msdu_in_mpdu,
  393. * @ msdu_continuation, sa_is_valid,
  394. * @ sa_idx_timeout, da_is_valid, da_idx_timeout,
  395. * @ da_is_MCBC
  396. *
  397. * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to the current
  398. * @ descriptor
  399. * @ msdu_desc_info: Holds MSDU descriptor info from HAL Rx descriptor
  400. * @ Return: void
  401. */
  402. static inline void hal_rx_msdu_desc_info_get(void *desc_addr,
  403. struct hal_rx_msdu_desc_info *msdu_desc_info)
  404. {
  405. struct reo_destination_ring *reo_dst_ring;
  406. uint32_t *msdu_info;
  407. reo_dst_ring = (struct reo_destination_ring *) desc_addr;
  408. msdu_info = (uint32_t *)&reo_dst_ring->rx_msdu_desc_info_details;
  409. msdu_desc_info->msdu_flags = HAL_RX_MSDU_FLAGS_GET(msdu_info);
  410. msdu_desc_info->msdu_len = HAL_RX_MSDU_PKT_LENGTH_GET(msdu_info);
  411. }
  412. /*
  413. * hal_rxdma_buff_addr_info_set() - set the buffer_addr_info of the
  414. * rxdma ring entry.
  415. * @rxdma_entry: descriptor entry
  416. * @paddr: physical address of nbuf data pointer.
  417. * @cookie: SW cookie used as a index to SW rx desc.
  418. * @manager: who owns the nbuf (host, NSS, etc...).
  419. *
  420. */
  421. static inline void hal_rxdma_buff_addr_info_set(void *rxdma_entry,
  422. qdf_dma_addr_t paddr, uint32_t cookie, uint8_t manager)
  423. {
  424. uint32_t paddr_lo = ((u64)paddr & 0x00000000ffffffff);
  425. uint32_t paddr_hi = ((u64)paddr & 0xffffffff00000000) >> 32;
  426. HAL_RXDMA_PADDR_LO_SET(rxdma_entry, paddr_lo);
  427. HAL_RXDMA_PADDR_HI_SET(rxdma_entry, paddr_hi);
  428. HAL_RXDMA_COOKIE_SET(rxdma_entry, cookie);
  429. HAL_RXDMA_MANAGER_SET(rxdma_entry, manager);
  430. }
  431. /*
  432. * Structures & Macros to obtain fields from the TLV's in the Rx packet
  433. * pre-header.
  434. */
  435. /*
  436. * Every Rx packet starts at an offset from the top of the buffer.
  437. * If the host hasn't subscribed to any specific TLV, there is
  438. * still space reserved for the following TLV's from the start of
  439. * the buffer:
  440. * -- RX ATTENTION
  441. * -- RX MPDU START
  442. * -- RX MSDU START
  443. * -- RX MSDU END
  444. * -- RX MPDU END
  445. * -- RX PACKET HEADER (802.11)
  446. * If the host subscribes to any of the TLV's above, that TLV
  447. * if populated by the HW
  448. */
  449. #define NUM_DWORDS_TAG 1
  450. /* By default the packet header TLV is 128 bytes */
  451. #define NUM_OF_BYTES_RX_802_11_HDR_TLV 128
  452. #define NUM_OF_DWORDS_RX_802_11_HDR_TLV \
  453. (NUM_OF_BYTES_RX_802_11_HDR_TLV >> 2)
  454. #define RX_PKT_OFFSET_WORDS \
  455. ( \
  456. NUM_OF_DWORDS_RX_ATTENTION + NUM_DWORDS_TAG \
  457. NUM_OF_DWORDS_RX_MPDU_START + NUM_DWORDS_TAG \
  458. NUM_OF_DWORDS_RX_MSDU_START + NUM_DWORDS_TAG \
  459. NUM_OF_DWORDS_RX_MSDU_END + NUM_DWORDS_TAG \
  460. NUM_OF_DWORDS_RX_MPDU_END + NUM_DWORDS_TAG \
  461. NUM_OF_DWORDS_RX_802_11_HDR_TLV + NUM_DWORDS_TAG \
  462. )
  463. #define RX_PKT_OFFSET_BYTES \
  464. (RX_PKT_OFFSET_WORDS << 2)
  465. #define RX_PKT_HDR_TLV_LEN 120
  466. /*
  467. * Each RX descriptor TLV is preceded by 1 DWORD "tag"
  468. */
  469. struct rx_attention_tlv {
  470. uint32_t tag;
  471. struct rx_attention rx_attn;
  472. };
  473. struct rx_mpdu_start_tlv {
  474. uint32_t tag;
  475. struct rx_mpdu_start rx_mpdu_start;
  476. };
  477. struct rx_msdu_start_tlv {
  478. uint32_t tag;
  479. struct rx_msdu_start rx_msdu_start;
  480. };
  481. struct rx_msdu_end_tlv {
  482. uint32_t tag;
  483. struct rx_msdu_end rx_msdu_end;
  484. };
  485. struct rx_mpdu_end_tlv {
  486. uint32_t tag;
  487. struct rx_mpdu_end rx_mpdu_end;
  488. };
  489. struct rx_pkt_hdr_tlv {
  490. uint32_t tag; /* 4 B */
  491. uint32_t phy_ppdu_id; /* 4 B */
  492. char rx_pkt_hdr[RX_PKT_HDR_TLV_LEN]; /* 120 B */
  493. };
  494. #define RXDMA_OPTIMIZATION
  495. #ifdef RXDMA_OPTIMIZATION
  496. /*
  497. * The RX_PADDING_BYTES is required so that the TLV's don't
  498. * spread across the 128 byte boundary
  499. * RXDMA optimization requires:
  500. * 1) MSDU_END & ATTENTION TLV's follow in that order
  501. * 2) TLV's don't span across 128 byte lines
  502. * 3) Rx Buffer is nicely aligned on the 128 byte boundary
  503. */
  504. #define RX_PADDING0_BYTES 4
  505. #define RX_PADDING1_BYTES 16
  506. struct rx_pkt_tlvs {
  507. struct rx_msdu_end_tlv msdu_end_tlv; /* 72 bytes */
  508. struct rx_attention_tlv attn_tlv; /* 16 bytes */
  509. struct rx_msdu_start_tlv msdu_start_tlv;/* 40 bytes */
  510. uint8_t rx_padding0[RX_PADDING0_BYTES]; /* 4 bytes */
  511. struct rx_mpdu_start_tlv mpdu_start_tlv;/* 96 bytes */
  512. struct rx_mpdu_end_tlv mpdu_end_tlv; /* 12 bytes */
  513. uint8_t rx_padding1[RX_PADDING1_BYTES]; /* 16 bytes */
  514. #ifndef NO_RX_PKT_HDR_TLV
  515. struct rx_pkt_hdr_tlv pkt_hdr_tlv; /* 128 bytes */
  516. #endif
  517. };
  518. #else /* RXDMA_OPTIMIZATION */
  519. struct rx_pkt_tlvs {
  520. struct rx_attention_tlv attn_tlv;
  521. struct rx_mpdu_start_tlv mpdu_start_tlv;
  522. struct rx_msdu_start_tlv msdu_start_tlv;
  523. struct rx_msdu_end_tlv msdu_end_tlv;
  524. struct rx_mpdu_end_tlv mpdu_end_tlv;
  525. struct rx_pkt_hdr_tlv pkt_hdr_tlv;
  526. };
  527. #endif /* RXDMA_OPTIMIZATION */
  528. #define RX_PKT_TLVS_LEN (sizeof(struct rx_pkt_tlvs))
  529. #ifdef NO_RX_PKT_HDR_TLV
  530. static inline uint8_t
  531. *hal_rx_pkt_hdr_get(uint8_t *buf)
  532. {
  533. return buf + RX_PKT_TLVS_LEN;
  534. }
  535. #else
  536. static inline uint8_t
  537. *hal_rx_pkt_hdr_get(uint8_t *buf)
  538. {
  539. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  540. return pkt_tlvs->pkt_hdr_tlv.rx_pkt_hdr;
  541. }
  542. #endif
  543. #define RX_PKT_TLV_OFFSET(field) qdf_offsetof(struct rx_pkt_tlvs, field)
  544. #define HAL_RX_PKT_TLV_MPDU_START_OFFSET(hal_soc) \
  545. RX_PKT_TLV_OFFSET(mpdu_start_tlv)
  546. #define HAL_RX_PKT_TLV_MPDU_END_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(mpdu_end_tlv)
  547. #define HAL_RX_PKT_TLV_MSDU_START_OFFSET(hal_soc) \
  548. RX_PKT_TLV_OFFSET(msdu_start_tlv)
  549. #define HAL_RX_PKT_TLV_MSDU_END_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(msdu_end_tlv)
  550. #define HAL_RX_PKT_TLV_ATTN_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(attn_tlv)
  551. #define HAL_RX_PKT_TLV_PKT_HDR_OFFSET(hal_soc) RX_PKT_TLV_OFFSET(pkt_hdr_tlv)
  552. static inline uint8_t
  553. *hal_rx_padding0_get(uint8_t *buf)
  554. {
  555. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  556. return pkt_tlvs->rx_padding0;
  557. }
  558. /*
  559. * hal_rx_encryption_info_valid(): Returns encryption type.
  560. *
  561. * @hal_soc_hdl: hal soc handle
  562. * @buf: rx_tlv_hdr of the received packet
  563. *
  564. * Return: encryption type
  565. */
  566. static inline uint32_t
  567. hal_rx_encryption_info_valid(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  568. {
  569. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  570. return hal_soc->ops->hal_rx_encryption_info_valid(buf);
  571. }
  572. /*
  573. * hal_rx_print_pn: Prints the PN of rx packet.
  574. * @hal_soc_hdl: hal soc handle
  575. * @buf: rx_tlv_hdr of the received packet
  576. *
  577. * Return: void
  578. */
  579. static inline void
  580. hal_rx_print_pn(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  581. {
  582. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  583. hal_soc->ops->hal_rx_print_pn(buf);
  584. }
  585. /*
  586. * Get msdu_done bit from the RX_ATTENTION TLV
  587. */
  588. #define HAL_RX_ATTN_MSDU_DONE_GET(_rx_attn) \
  589. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \
  590. RX_ATTENTION_2_MSDU_DONE_OFFSET)), \
  591. RX_ATTENTION_2_MSDU_DONE_MASK, \
  592. RX_ATTENTION_2_MSDU_DONE_LSB))
  593. static inline uint32_t
  594. hal_rx_attn_msdu_done_get(uint8_t *buf)
  595. {
  596. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  597. struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
  598. uint32_t msdu_done;
  599. msdu_done = HAL_RX_ATTN_MSDU_DONE_GET(rx_attn);
  600. return msdu_done;
  601. }
  602. #define HAL_RX_ATTN_FIRST_MPDU_GET(_rx_attn) \
  603. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \
  604. RX_ATTENTION_1_FIRST_MPDU_OFFSET)), \
  605. RX_ATTENTION_1_FIRST_MPDU_MASK, \
  606. RX_ATTENTION_1_FIRST_MPDU_LSB))
  607. /*
  608. * hal_rx_attn_first_mpdu_get(): get fist_mpdu bit from rx attention
  609. * @buf: pointer to rx_pkt_tlvs
  610. *
  611. * reutm: uint32_t(first_msdu)
  612. */
  613. static inline uint32_t
  614. hal_rx_attn_first_mpdu_get(uint8_t *buf)
  615. {
  616. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  617. struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
  618. uint32_t first_mpdu;
  619. first_mpdu = HAL_RX_ATTN_FIRST_MPDU_GET(rx_attn);
  620. return first_mpdu;
  621. }
  622. #define HAL_RX_ATTN_TCP_UDP_CKSUM_FAIL_GET(_rx_attn) \
  623. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \
  624. RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_OFFSET)), \
  625. RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_MASK, \
  626. RX_ATTENTION_1_TCP_UDP_CHKSUM_FAIL_LSB))
  627. /*
  628. * hal_rx_attn_tcp_udp_cksum_fail_get(): get tcp_udp cksum fail bit
  629. * from rx attention
  630. * @buf: pointer to rx_pkt_tlvs
  631. *
  632. * Return: tcp_udp_cksum_fail
  633. */
  634. static inline bool
  635. hal_rx_attn_tcp_udp_cksum_fail_get(uint8_t *buf)
  636. {
  637. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  638. struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
  639. bool tcp_udp_cksum_fail;
  640. tcp_udp_cksum_fail = HAL_RX_ATTN_TCP_UDP_CKSUM_FAIL_GET(rx_attn);
  641. return tcp_udp_cksum_fail;
  642. }
  643. #define HAL_RX_ATTN_IP_CKSUM_FAIL_GET(_rx_attn) \
  644. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \
  645. RX_ATTENTION_1_IP_CHKSUM_FAIL_OFFSET)), \
  646. RX_ATTENTION_1_IP_CHKSUM_FAIL_MASK, \
  647. RX_ATTENTION_1_IP_CHKSUM_FAIL_LSB))
  648. /*
  649. * hal_rx_attn_ip_cksum_fail_get(): get ip cksum fail bit
  650. * from rx attention
  651. * @buf: pointer to rx_pkt_tlvs
  652. *
  653. * Return: ip_cksum_fail
  654. */
  655. static inline bool
  656. hal_rx_attn_ip_cksum_fail_get(uint8_t *buf)
  657. {
  658. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  659. struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
  660. bool ip_cksum_fail;
  661. ip_cksum_fail = HAL_RX_ATTN_IP_CKSUM_FAIL_GET(rx_attn);
  662. return ip_cksum_fail;
  663. }
  664. #define HAL_RX_ATTN_PHY_PPDU_ID_GET(_rx_attn) \
  665. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \
  666. RX_ATTENTION_0_PHY_PPDU_ID_OFFSET)), \
  667. RX_ATTENTION_0_PHY_PPDU_ID_MASK, \
  668. RX_ATTENTION_0_PHY_PPDU_ID_LSB))
  669. /*
  670. * hal_rx_attn_phy_ppdu_id_get(): get phy_ppdu_id value
  671. * from rx attention
  672. * @buf: pointer to rx_pkt_tlvs
  673. *
  674. * Return: phy_ppdu_id
  675. */
  676. static inline uint16_t
  677. hal_rx_attn_phy_ppdu_id_get(uint8_t *buf)
  678. {
  679. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  680. struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
  681. uint16_t phy_ppdu_id;
  682. phy_ppdu_id = HAL_RX_ATTN_PHY_PPDU_ID_GET(rx_attn);
  683. return phy_ppdu_id;
  684. }
  685. #define HAL_RX_ATTN_CCE_MATCH_GET(_rx_attn) \
  686. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \
  687. RX_ATTENTION_1_CCE_MATCH_OFFSET)), \
  688. RX_ATTENTION_1_CCE_MATCH_MASK, \
  689. RX_ATTENTION_1_CCE_MATCH_LSB))
  690. /*
  691. * hal_rx_msdu_cce_match_get(): get CCE match bit
  692. * from rx attention
  693. * @buf: pointer to rx_pkt_tlvs
  694. * Return: CCE match value
  695. */
  696. static inline bool
  697. hal_rx_msdu_cce_match_get(uint8_t *buf)
  698. {
  699. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  700. struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
  701. bool cce_match_val;
  702. cce_match_val = HAL_RX_ATTN_CCE_MATCH_GET(rx_attn);
  703. return cce_match_val;
  704. }
  705. /*
  706. * Get peer_meta_data from RX_MPDU_INFO within RX_MPDU_START
  707. */
  708. #define HAL_RX_MPDU_PEER_META_DATA_GET(_rx_mpdu_info) \
  709. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  710. RX_MPDU_INFO_8_PEER_META_DATA_OFFSET)), \
  711. RX_MPDU_INFO_8_PEER_META_DATA_MASK, \
  712. RX_MPDU_INFO_8_PEER_META_DATA_LSB))
  713. static inline uint32_t
  714. hal_rx_mpdu_peer_meta_data_get(uint8_t *buf)
  715. {
  716. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  717. struct rx_mpdu_start *mpdu_start =
  718. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  719. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  720. uint32_t peer_meta_data;
  721. peer_meta_data = HAL_RX_MPDU_PEER_META_DATA_GET(mpdu_info);
  722. return peer_meta_data;
  723. }
  724. #define HAL_RX_MPDU_INFO_AMPDU_FLAG_GET(_rx_mpdu_info) \
  725. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  726. RX_MPDU_INFO_12_AMPDU_FLAG_OFFSET)), \
  727. RX_MPDU_INFO_12_AMPDU_FLAG_MASK, \
  728. RX_MPDU_INFO_12_AMPDU_FLAG_LSB))
  729. /**
  730. * hal_rx_mpdu_info_ampdu_flag_get(): get ampdu flag bit
  731. * from rx mpdu info
  732. * @buf: pointer to rx_pkt_tlvs
  733. *
  734. * Return: ampdu flag
  735. */
  736. static inline bool
  737. hal_rx_mpdu_info_ampdu_flag_get(uint8_t *buf)
  738. {
  739. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  740. struct rx_mpdu_start *mpdu_start =
  741. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  742. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  743. bool ampdu_flag;
  744. ampdu_flag = HAL_RX_MPDU_INFO_AMPDU_FLAG_GET(mpdu_info);
  745. return ampdu_flag;
  746. }
  747. #define HAL_RX_MPDU_PEER_META_DATA_SET(_rx_mpdu_info, peer_mdata) \
  748. ((*(((uint32_t *)_rx_mpdu_info) + \
  749. (RX_MPDU_INFO_8_PEER_META_DATA_OFFSET >> 2))) = \
  750. (peer_mdata << RX_MPDU_INFO_8_PEER_META_DATA_LSB) & \
  751. RX_MPDU_INFO_8_PEER_META_DATA_MASK)
  752. /*
  753. * @ hal_rx_mpdu_peer_meta_data_set: set peer meta data in RX mpdu start tlv
  754. *
  755. * @ buf: rx_tlv_hdr of the received packet
  756. * @ peer_mdata: peer meta data to be set.
  757. * @ Return: void
  758. */
  759. static inline void
  760. hal_rx_mpdu_peer_meta_data_set(uint8_t *buf, uint32_t peer_mdata)
  761. {
  762. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  763. struct rx_mpdu_start *mpdu_start =
  764. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  765. struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
  766. HAL_RX_MPDU_PEER_META_DATA_SET(mpdu_info, peer_mdata);
  767. }
  768. /**
  769. * LRO information needed from the TLVs
  770. */
  771. #define HAL_RX_TLV_GET_LRO_ELIGIBLE(buf) \
  772. (_HAL_MS( \
  773. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  774. msdu_end_tlv.rx_msdu_end), \
  775. RX_MSDU_END_9_LRO_ELIGIBLE_OFFSET)), \
  776. RX_MSDU_END_9_LRO_ELIGIBLE_MASK, \
  777. RX_MSDU_END_9_LRO_ELIGIBLE_LSB))
  778. #define HAL_RX_TLV_GET_TCP_ACK(buf) \
  779. (_HAL_MS( \
  780. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  781. msdu_end_tlv.rx_msdu_end), \
  782. RX_MSDU_END_8_TCP_ACK_NUMBER_OFFSET)), \
  783. RX_MSDU_END_8_TCP_ACK_NUMBER_MASK, \
  784. RX_MSDU_END_8_TCP_ACK_NUMBER_LSB))
  785. #define HAL_RX_TLV_GET_TCP_SEQ(buf) \
  786. (_HAL_MS( \
  787. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  788. msdu_end_tlv.rx_msdu_end), \
  789. RX_MSDU_END_7_TCP_SEQ_NUMBER_OFFSET)), \
  790. RX_MSDU_END_7_TCP_SEQ_NUMBER_MASK, \
  791. RX_MSDU_END_7_TCP_SEQ_NUMBER_LSB))
  792. #define HAL_RX_TLV_GET_TCP_WIN(buf) \
  793. (_HAL_MS( \
  794. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  795. msdu_end_tlv.rx_msdu_end), \
  796. RX_MSDU_END_9_WINDOW_SIZE_OFFSET)), \
  797. RX_MSDU_END_9_WINDOW_SIZE_MASK, \
  798. RX_MSDU_END_9_WINDOW_SIZE_LSB))
  799. #define HAL_RX_TLV_GET_TCP_PURE_ACK(buf) \
  800. (_HAL_MS( \
  801. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  802. msdu_start_tlv.rx_msdu_start), \
  803. RX_MSDU_START_2_TCP_ONLY_ACK_OFFSET)), \
  804. RX_MSDU_START_2_TCP_ONLY_ACK_MASK, \
  805. RX_MSDU_START_2_TCP_ONLY_ACK_LSB))
  806. #define HAL_RX_TLV_GET_TCP_PROTO(buf) \
  807. (_HAL_MS( \
  808. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  809. msdu_start_tlv.rx_msdu_start), \
  810. RX_MSDU_START_2_TCP_PROTO_OFFSET)), \
  811. RX_MSDU_START_2_TCP_PROTO_MASK, \
  812. RX_MSDU_START_2_TCP_PROTO_LSB))
  813. #define HAL_RX_TLV_GET_IPV6(buf) \
  814. (_HAL_MS( \
  815. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  816. msdu_start_tlv.rx_msdu_start), \
  817. RX_MSDU_START_2_IPV6_PROTO_OFFSET)), \
  818. RX_MSDU_START_2_IPV6_PROTO_MASK, \
  819. RX_MSDU_START_2_IPV6_PROTO_LSB))
  820. #define HAL_RX_TLV_GET_IP_OFFSET(buf) \
  821. (_HAL_MS( \
  822. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  823. msdu_start_tlv.rx_msdu_start), \
  824. RX_MSDU_START_1_L3_OFFSET_OFFSET)), \
  825. RX_MSDU_START_1_L3_OFFSET_MASK, \
  826. RX_MSDU_START_1_L3_OFFSET_LSB))
  827. #define HAL_RX_TLV_GET_TCP_OFFSET(buf) \
  828. (_HAL_MS( \
  829. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  830. msdu_start_tlv.rx_msdu_start), \
  831. RX_MSDU_START_1_L4_OFFSET_OFFSET)), \
  832. RX_MSDU_START_1_L4_OFFSET_MASK, \
  833. RX_MSDU_START_1_L4_OFFSET_LSB))
  834. #define HAL_RX_TLV_GET_FLOW_ID_TOEPLITZ(buf) \
  835. (_HAL_MS( \
  836. (*_OFFSET_TO_WORD_PTR(&(((struct rx_pkt_tlvs *)(buf))->\
  837. msdu_start_tlv.rx_msdu_start), \
  838. RX_MSDU_START_4_FLOW_ID_TOEPLITZ_OFFSET)), \
  839. RX_MSDU_START_4_FLOW_ID_TOEPLITZ_MASK, \
  840. RX_MSDU_START_4_FLOW_ID_TOEPLITZ_LSB))
  841. /**
  842. * hal_rx_msdu_end_l3_hdr_padding_get(): API to get the
  843. * l3_header padding from rx_msdu_end TLV
  844. *
  845. * @buf: pointer to the start of RX PKT TLV headers
  846. * Return: number of l3 header padding bytes
  847. */
  848. static inline uint32_t
  849. hal_rx_msdu_end_l3_hdr_padding_get(hal_soc_handle_t hal_soc_hdl,
  850. uint8_t *buf)
  851. {
  852. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  853. return hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get(buf);
  854. }
  855. /**
  856. * hal_rx_msdu_end_sa_idx_get(): API to get the
  857. * sa_idx from rx_msdu_end TLV
  858. *
  859. * @ buf: pointer to the start of RX PKT TLV headers
  860. * Return: sa_idx (SA AST index)
  861. */
  862. static inline uint16_t
  863. hal_rx_msdu_end_sa_idx_get(hal_soc_handle_t hal_soc_hdl,
  864. uint8_t *buf)
  865. {
  866. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  867. return hal_soc->ops->hal_rx_msdu_end_sa_idx_get(buf);
  868. }
  869. /**
  870. * hal_rx_msdu_end_sa_is_valid_get(): API to get the
  871. * sa_is_valid bit from rx_msdu_end TLV
  872. *
  873. * @ buf: pointer to the start of RX PKT TLV headers
  874. * Return: sa_is_valid bit
  875. */
  876. static inline uint8_t
  877. hal_rx_msdu_end_sa_is_valid_get(hal_soc_handle_t hal_soc_hdl,
  878. uint8_t *buf)
  879. {
  880. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  881. return hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get(buf);
  882. }
  883. #define HAL_RX_MSDU_START_MSDU_LEN_GET(_rx_msdu_start) \
  884. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \
  885. RX_MSDU_START_1_MSDU_LENGTH_OFFSET)), \
  886. RX_MSDU_START_1_MSDU_LENGTH_MASK, \
  887. RX_MSDU_START_1_MSDU_LENGTH_LSB))
  888. /**
  889. * hal_rx_msdu_start_msdu_len_get(): API to get the MSDU length
  890. * from rx_msdu_start TLV
  891. *
  892. * @ buf: pointer to the start of RX PKT TLV headers
  893. * Return: msdu length
  894. */
  895. static inline uint32_t
  896. hal_rx_msdu_start_msdu_len_get(uint8_t *buf)
  897. {
  898. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  899. struct rx_msdu_start *msdu_start =
  900. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  901. uint32_t msdu_len;
  902. msdu_len = HAL_RX_MSDU_START_MSDU_LEN_GET(msdu_start);
  903. return msdu_len;
  904. }
  905. /**
  906. * hal_rx_msdu_start_msdu_len_set(): API to set the MSDU length
  907. * from rx_msdu_start TLV
  908. *
  909. * @buf: pointer to the start of RX PKT TLV headers
  910. * @len: msdu length
  911. *
  912. * Return: none
  913. */
  914. static inline void
  915. hal_rx_msdu_start_msdu_len_set(uint8_t *buf, uint32_t len)
  916. {
  917. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  918. struct rx_msdu_start *msdu_start =
  919. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  920. void *wrd1;
  921. wrd1 = (uint8_t *)msdu_start + RX_MSDU_START_1_MSDU_LENGTH_OFFSET;
  922. *(uint32_t *)wrd1 &= (~RX_MSDU_START_1_MSDU_LENGTH_MASK);
  923. *(uint32_t *)wrd1 |= len;
  924. }
  925. #define HAL_RX_MSDU_START_BW_GET(_rx_msdu_start) \
  926. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\
  927. RX_MSDU_START_5_RECEIVE_BANDWIDTH_OFFSET)), \
  928. RX_MSDU_START_5_RECEIVE_BANDWIDTH_MASK, \
  929. RX_MSDU_START_5_RECEIVE_BANDWIDTH_LSB))
  930. /*
  931. * hal_rx_msdu_start_bw_get(): API to get the Bandwidth
  932. * Interval from rx_msdu_start
  933. *
  934. * @buf: pointer to the start of RX PKT TLV header
  935. * Return: uint32_t(bw)
  936. */
  937. static inline uint32_t
  938. hal_rx_msdu_start_bw_get(uint8_t *buf)
  939. {
  940. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  941. struct rx_msdu_start *msdu_start =
  942. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  943. uint32_t bw;
  944. bw = HAL_RX_MSDU_START_BW_GET(msdu_start);
  945. return bw;
  946. }
  947. #define HAL_RX_MSDU_START_FLOWID_TOEPLITZ_GET(_rx_msdu_start) \
  948. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \
  949. RX_MSDU_START_4_FLOW_ID_TOEPLITZ_OFFSET)), \
  950. RX_MSDU_START_4_FLOW_ID_TOEPLITZ_MASK, \
  951. RX_MSDU_START_4_FLOW_ID_TOEPLITZ_LSB))
  952. /**
  953. * hal_rx_msdu_start_toeplitz_get: API to get the toeplitz hash
  954. * from rx_msdu_start TLV
  955. *
  956. * @ buf: pointer to the start of RX PKT TLV headers
  957. * Return: toeplitz hash
  958. */
  959. static inline uint32_t
  960. hal_rx_msdu_start_toeplitz_get(uint8_t *buf)
  961. {
  962. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  963. struct rx_msdu_start *msdu_start =
  964. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  965. return HAL_RX_MSDU_START_FLOWID_TOEPLITZ_GET(msdu_start);
  966. }
  967. /**
  968. * enum hal_rx_mpdu_info_sw_frame_group_id_type: Enum for group id in MPDU_INFO
  969. *
  970. * @ HAL_MPDU_SW_FRAME_GROUP_NDP_FRAME: NDP frame
  971. * @ HAL_MPDU_SW_FRAME_GROUP_MULTICAST_DATA: multicast data frame
  972. * @ HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA: unicast data frame
  973. * @ HAL_MPDU_SW_FRAME_GROUP_NULL_DATA: NULL data frame
  974. * @ HAL_MPDU_SW_FRAME_GROUP_MGMT: management frame
  975. * @ HAL_MPDU_SW_FRAME_GROUP_CTRL: control frame
  976. * @ HAL_MPDU_SW_FRAME_GROUP_UNSUPPORTED: unsupported
  977. * @ HAL_MPDU_SW_FRAME_GROUP_MAX: max limit
  978. */
  979. enum hal_rx_mpdu_info_sw_frame_group_id_type {
  980. HAL_MPDU_SW_FRAME_GROUP_NDP_FRAME = 0,
  981. HAL_MPDU_SW_FRAME_GROUP_MULTICAST_DATA,
  982. HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA,
  983. HAL_MPDU_SW_FRAME_GROUP_NULL_DATA,
  984. HAL_MPDU_SW_FRAME_GROUP_MGMT,
  985. HAL_MPDU_SW_FRAME_GROUP_MGMT_BEACON = 12,
  986. HAL_MPDU_SW_FRAME_GROUP_CTRL = 20,
  987. HAL_MPDU_SW_FRAME_GROUP_UNSUPPORTED = 36,
  988. HAL_MPDU_SW_FRAME_GROUP_MAX = 37,
  989. };
  990. /**
  991. * hal_rx_mpdu_start_mpdu_qos_control_valid_get():
  992. * Retrieve qos control valid bit from the tlv.
  993. * @hal_soc_hdl: hal_soc handle
  994. * @buf: pointer to rx pkt TLV.
  995. *
  996. * Return: qos control value.
  997. */
  998. static inline uint32_t
  999. hal_rx_mpdu_start_mpdu_qos_control_valid_get(
  1000. hal_soc_handle_t hal_soc_hdl,
  1001. uint8_t *buf)
  1002. {
  1003. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1004. if ((!hal_soc) || (!hal_soc->ops)) {
  1005. hal_err("hal handle is NULL");
  1006. QDF_BUG(0);
  1007. return QDF_STATUS_E_INVAL;
  1008. }
  1009. if (hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get)
  1010. return hal_soc->ops->
  1011. hal_rx_mpdu_start_mpdu_qos_control_valid_get(buf);
  1012. return QDF_STATUS_E_INVAL;
  1013. }
  1014. /**
  1015. * hal_rx_is_unicast: check packet is unicast frame or not.
  1016. * @hal_soc_hdl: hal_soc handle
  1017. * @buf: pointer to rx pkt TLV.
  1018. *
  1019. * Return: true on unicast.
  1020. */
  1021. static inline bool
  1022. hal_rx_is_unicast(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  1023. {
  1024. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1025. return hal_soc->ops->hal_rx_is_unicast(buf);
  1026. }
  1027. /**
  1028. * hal_rx_tid_get: get tid based on qos control valid.
  1029. * @hal_soc_hdl: hal soc handle
  1030. * @buf: pointer to rx pkt TLV.
  1031. *
  1032. * Return: tid
  1033. */
  1034. static inline uint32_t
  1035. hal_rx_tid_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  1036. {
  1037. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1038. return hal_soc->ops->hal_rx_tid_get(hal_soc_hdl, buf);
  1039. }
  1040. /**
  1041. * hal_rx_mpdu_start_sw_peer_id_get() - Retrieve sw peer id
  1042. * @hal_soc_hdl: hal soc handle
  1043. * @buf: pointer to rx pkt TLV.
  1044. *
  1045. * Return: sw peer_id
  1046. */
  1047. static inline uint32_t
  1048. hal_rx_mpdu_start_sw_peer_id_get(hal_soc_handle_t hal_soc_hdl,
  1049. uint8_t *buf)
  1050. {
  1051. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1052. return hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get(buf);
  1053. }
  1054. #define HAL_RX_MSDU_START_SGI_GET(_rx_msdu_start) \
  1055. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\
  1056. RX_MSDU_START_5_SGI_OFFSET)), \
  1057. RX_MSDU_START_5_SGI_MASK, \
  1058. RX_MSDU_START_5_SGI_LSB))
  1059. /**
  1060. * hal_rx_msdu_start_msdu_sgi_get(): API to get the Short Gaurd
  1061. * Interval from rx_msdu_start TLV
  1062. *
  1063. * @buf: pointer to the start of RX PKT TLV headers
  1064. * Return: uint32_t(sgi)
  1065. */
  1066. static inline uint32_t
  1067. hal_rx_msdu_start_sgi_get(uint8_t *buf)
  1068. {
  1069. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1070. struct rx_msdu_start *msdu_start =
  1071. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  1072. uint32_t sgi;
  1073. sgi = HAL_RX_MSDU_START_SGI_GET(msdu_start);
  1074. return sgi;
  1075. }
  1076. #define HAL_RX_MSDU_START_RATE_MCS_GET(_rx_msdu_start) \
  1077. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start),\
  1078. RX_MSDU_START_5_RATE_MCS_OFFSET)), \
  1079. RX_MSDU_START_5_RATE_MCS_MASK, \
  1080. RX_MSDU_START_5_RATE_MCS_LSB))
  1081. /**
  1082. * hal_rx_msdu_start_msdu_rate_mcs_get(): API to get the MCS rate
  1083. * from rx_msdu_start TLV
  1084. *
  1085. * @buf: pointer to the start of RX PKT TLV headers
  1086. * Return: uint32_t(rate_mcs)
  1087. */
  1088. static inline uint32_t
  1089. hal_rx_msdu_start_rate_mcs_get(uint8_t *buf)
  1090. {
  1091. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1092. struct rx_msdu_start *msdu_start =
  1093. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  1094. uint32_t rate_mcs;
  1095. rate_mcs = HAL_RX_MSDU_START_RATE_MCS_GET(msdu_start);
  1096. return rate_mcs;
  1097. }
  1098. #define HAL_RX_ATTN_DECRYPT_STATUS_GET(_rx_attn) \
  1099. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_attn, \
  1100. RX_ATTENTION_2_DECRYPT_STATUS_CODE_OFFSET)), \
  1101. RX_ATTENTION_2_DECRYPT_STATUS_CODE_MASK, \
  1102. RX_ATTENTION_2_DECRYPT_STATUS_CODE_LSB))
  1103. /*
  1104. * hal_rx_attn_msdu_get_is_decrypted(): API to get the decrypt status of the
  1105. * packet from rx_attention
  1106. *
  1107. * @buf: pointer to the start of RX PKT TLV header
  1108. * Return: uint32_t(decryt status)
  1109. */
  1110. static inline uint32_t
  1111. hal_rx_attn_msdu_get_is_decrypted(uint8_t *buf)
  1112. {
  1113. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1114. struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
  1115. uint32_t is_decrypt = 0;
  1116. uint32_t decrypt_status;
  1117. decrypt_status = HAL_RX_ATTN_DECRYPT_STATUS_GET(rx_attn);
  1118. if (!decrypt_status)
  1119. is_decrypt = 1;
  1120. return is_decrypt;
  1121. }
  1122. /*
  1123. * Get key index from RX_MSDU_END
  1124. */
  1125. #define HAL_RX_MSDU_END_KEYID_OCTET_GET(_rx_msdu_end) \
  1126. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_end, \
  1127. RX_MSDU_END_2_KEY_ID_OCTET_OFFSET)), \
  1128. RX_MSDU_END_2_KEY_ID_OCTET_MASK, \
  1129. RX_MSDU_END_2_KEY_ID_OCTET_LSB))
  1130. /*
  1131. * hal_rx_msdu_get_keyid(): API to get the key id if the decrypted packet
  1132. * from rx_msdu_end
  1133. *
  1134. * @buf: pointer to the start of RX PKT TLV header
  1135. * Return: uint32_t(key id)
  1136. */
  1137. static inline uint32_t
  1138. hal_rx_msdu_get_keyid(uint8_t *buf)
  1139. {
  1140. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1141. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  1142. uint32_t keyid_octet;
  1143. keyid_octet = HAL_RX_MSDU_END_KEYID_OCTET_GET(msdu_end);
  1144. return keyid_octet & 0x3;
  1145. }
  1146. #define HAL_RX_MSDU_START_RSSI_GET(_rx_msdu_start) \
  1147. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \
  1148. RX_MSDU_START_5_USER_RSSI_OFFSET)), \
  1149. RX_MSDU_START_5_USER_RSSI_MASK, \
  1150. RX_MSDU_START_5_USER_RSSI_LSB))
  1151. /*
  1152. * hal_rx_msdu_start_get_rssi(): API to get the rssi of received pkt
  1153. * from rx_msdu_start
  1154. *
  1155. * @buf: pointer to the start of RX PKT TLV header
  1156. * Return: uint32_t(rssi)
  1157. */
  1158. static inline uint32_t
  1159. hal_rx_msdu_start_get_rssi(uint8_t *buf)
  1160. {
  1161. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1162. struct rx_msdu_start *msdu_start = &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  1163. uint32_t rssi;
  1164. rssi = HAL_RX_MSDU_START_RSSI_GET(msdu_start);
  1165. return rssi;
  1166. }
  1167. #define HAL_RX_MSDU_START_FREQ_GET(_rx_msdu_start) \
  1168. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \
  1169. RX_MSDU_START_7_SW_PHY_META_DATA_OFFSET)), \
  1170. RX_MSDU_START_7_SW_PHY_META_DATA_MASK, \
  1171. RX_MSDU_START_7_SW_PHY_META_DATA_LSB))
  1172. /*
  1173. * hal_rx_msdu_start_get_freq(): API to get the frequency of operating channel
  1174. * from rx_msdu_start
  1175. *
  1176. * @buf: pointer to the start of RX PKT TLV header
  1177. * Return: uint32_t(frequency)
  1178. */
  1179. static inline uint32_t
  1180. hal_rx_msdu_start_get_freq(uint8_t *buf)
  1181. {
  1182. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1183. struct rx_msdu_start *msdu_start =
  1184. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  1185. uint32_t freq;
  1186. freq = HAL_RX_MSDU_START_FREQ_GET(msdu_start);
  1187. return freq;
  1188. }
  1189. #define HAL_RX_MSDU_START_PKT_TYPE_GET(_rx_msdu_start) \
  1190. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_msdu_start, \
  1191. RX_MSDU_START_5_PKT_TYPE_OFFSET)), \
  1192. RX_MSDU_START_5_PKT_TYPE_MASK, \
  1193. RX_MSDU_START_5_PKT_TYPE_LSB))
  1194. /*
  1195. * hal_rx_msdu_start_get_pkt_type(): API to get the pkt type
  1196. * from rx_msdu_start
  1197. *
  1198. * @buf: pointer to the start of RX PKT TLV header
  1199. * Return: uint32_t(pkt type)
  1200. */
  1201. static inline uint32_t
  1202. hal_rx_msdu_start_get_pkt_type(uint8_t *buf)
  1203. {
  1204. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1205. struct rx_msdu_start *msdu_start = &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  1206. uint32_t pkt_type;
  1207. pkt_type = HAL_RX_MSDU_START_PKT_TYPE_GET(msdu_start);
  1208. return pkt_type;
  1209. }
  1210. /*
  1211. * hal_rx_mpdu_get_tods(): API to get the tods info
  1212. * from rx_mpdu_start
  1213. *
  1214. * @buf: pointer to the start of RX PKT TLV header
  1215. * Return: uint32_t(to_ds)
  1216. */
  1217. static inline uint32_t
  1218. hal_rx_mpdu_get_to_ds(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  1219. {
  1220. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1221. return hal_soc->ops->hal_rx_mpdu_get_to_ds(buf);
  1222. }
  1223. /*
  1224. * hal_rx_mpdu_get_fr_ds(): API to get the from ds info
  1225. * from rx_mpdu_start
  1226. * @hal_soc_hdl: hal soc handle
  1227. * @buf: pointer to the start of RX PKT TLV header
  1228. *
  1229. * Return: uint32_t(fr_ds)
  1230. */
  1231. static inline uint32_t
  1232. hal_rx_mpdu_get_fr_ds(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  1233. {
  1234. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1235. return hal_soc->ops->hal_rx_mpdu_get_fr_ds(buf);
  1236. }
  1237. #define HAL_RX_MPDU_AD4_31_0_GET(_rx_mpdu_info) \
  1238. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  1239. RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_OFFSET)), \
  1240. RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_MASK, \
  1241. RX_MPDU_INFO_20_MAC_ADDR_AD4_31_0_LSB))
  1242. #define HAL_RX_MPDU_AD4_47_32_GET(_rx_mpdu_info) \
  1243. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  1244. RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_OFFSET)), \
  1245. RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_MASK, \
  1246. RX_MPDU_INFO_21_MAC_ADDR_AD4_47_32_LSB))
  1247. /*
  1248. * hal_rx_mpdu_get_addr1(): API to check get address1 of the mpdu
  1249. * @hal_soc_hdl: hal soc handle
  1250. * @buf: pointer to the start of RX PKT TLV headera
  1251. * @mac_addr: pointer to mac address
  1252. *
  1253. * Return: success/failure
  1254. */
  1255. static inline
  1256. QDF_STATUS hal_rx_mpdu_get_addr1(hal_soc_handle_t hal_soc_hdl,
  1257. uint8_t *buf, uint8_t *mac_addr)
  1258. {
  1259. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1260. return hal_soc->ops->hal_rx_mpdu_get_addr1(buf, mac_addr);
  1261. }
  1262. /*
  1263. * hal_rx_mpdu_get_addr2(): API to check get address2 of the mpdu
  1264. * in the packet
  1265. * @hal_soc_hdl: hal soc handle
  1266. * @buf: pointer to the start of RX PKT TLV header
  1267. * @mac_addr: pointer to mac address
  1268. *
  1269. * Return: success/failure
  1270. */
  1271. static inline
  1272. QDF_STATUS hal_rx_mpdu_get_addr2(hal_soc_handle_t hal_soc_hdl,
  1273. uint8_t *buf, uint8_t *mac_addr)
  1274. {
  1275. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1276. return hal_soc->ops->hal_rx_mpdu_get_addr2(buf, mac_addr);
  1277. }
  1278. /*
  1279. * hal_rx_mpdu_get_addr3(): API to get address3 of the mpdu
  1280. * in the packet
  1281. * @hal_soc_hdl: hal soc handle
  1282. * @buf: pointer to the start of RX PKT TLV header
  1283. * @mac_addr: pointer to mac address
  1284. *
  1285. * Return: success/failure
  1286. */
  1287. static inline
  1288. QDF_STATUS hal_rx_mpdu_get_addr3(hal_soc_handle_t hal_soc_hdl,
  1289. uint8_t *buf, uint8_t *mac_addr)
  1290. {
  1291. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1292. return hal_soc->ops->hal_rx_mpdu_get_addr3(buf, mac_addr);
  1293. }
  1294. /*
  1295. * hal_rx_mpdu_get_addr4(): API to get address4 of the mpdu
  1296. * in the packet
  1297. * @hal_soc_hdl: hal_soc handle
  1298. * @buf: pointer to the start of RX PKT TLV header
  1299. * @mac_addr: pointer to mac address
  1300. * Return: success/failure
  1301. */
  1302. static inline
  1303. QDF_STATUS hal_rx_mpdu_get_addr4(hal_soc_handle_t hal_soc_hdl,
  1304. uint8_t *buf, uint8_t *mac_addr)
  1305. {
  1306. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1307. return hal_soc->ops->hal_rx_mpdu_get_addr4(buf, mac_addr);
  1308. }
  1309. /**
  1310. * hal_rx_msdu_end_da_idx_get: API to get da_idx
  1311. * from rx_msdu_end TLV
  1312. *
  1313. * @ buf: pointer to the start of RX PKT TLV headers
  1314. * Return: da index
  1315. */
  1316. static inline uint16_t
  1317. hal_rx_msdu_end_da_idx_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  1318. {
  1319. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1320. return hal_soc->ops->hal_rx_msdu_end_da_idx_get(buf);
  1321. }
  1322. /**
  1323. * hal_rx_msdu_end_da_is_valid_get: API to check if da is valid
  1324. * from rx_msdu_end TLV
  1325. * @hal_soc_hdl: hal soc handle
  1326. * @ buf: pointer to the start of RX PKT TLV headers
  1327. *
  1328. * Return: da_is_valid
  1329. */
  1330. static inline uint8_t
  1331. hal_rx_msdu_end_da_is_valid_get(hal_soc_handle_t hal_soc_hdl,
  1332. uint8_t *buf)
  1333. {
  1334. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1335. return hal_soc->ops->hal_rx_msdu_end_da_is_valid_get(buf);
  1336. }
  1337. /**
  1338. * hal_rx_msdu_end_da_is_mcbc_get: API to check if pkt is MCBC
  1339. * from rx_msdu_end TLV
  1340. *
  1341. * @buf: pointer to the start of RX PKT TLV headers
  1342. *
  1343. * Return: da_is_mcbc
  1344. */
  1345. static inline uint8_t
  1346. hal_rx_msdu_end_da_is_mcbc_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  1347. {
  1348. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1349. return hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get(buf);
  1350. }
  1351. /**
  1352. * hal_rx_msdu_end_first_msdu_get: API to get first msdu status
  1353. * from rx_msdu_end TLV
  1354. * @hal_soc_hdl: hal soc handle
  1355. * @buf: pointer to the start of RX PKT TLV headers
  1356. *
  1357. * Return: first_msdu
  1358. */
  1359. static inline uint8_t
  1360. hal_rx_msdu_end_first_msdu_get(hal_soc_handle_t hal_soc_hdl,
  1361. uint8_t *buf)
  1362. {
  1363. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1364. return hal_soc->ops->hal_rx_msdu_end_first_msdu_get(buf);
  1365. }
  1366. /**
  1367. * hal_rx_msdu_end_last_msdu_get: API to get last msdu status
  1368. * from rx_msdu_end TLV
  1369. * @hal_soc_hdl: hal soc handle
  1370. * @buf: pointer to the start of RX PKT TLV headers
  1371. *
  1372. * Return: last_msdu
  1373. */
  1374. static inline uint8_t
  1375. hal_rx_msdu_end_last_msdu_get(hal_soc_handle_t hal_soc_hdl,
  1376. uint8_t *buf)
  1377. {
  1378. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1379. return hal_soc->ops->hal_rx_msdu_end_last_msdu_get(buf);
  1380. }
  1381. /**
  1382. * hal_rx_msdu_cce_metadata_get: API to get CCE metadata
  1383. * from rx_msdu_end TLV
  1384. * @buf: pointer to the start of RX PKT TLV headers
  1385. * Return: cce_meta_data
  1386. */
  1387. static inline uint16_t
  1388. hal_rx_msdu_cce_metadata_get(hal_soc_handle_t hal_soc_hdl,
  1389. uint8_t *buf)
  1390. {
  1391. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1392. return hal_soc->ops->hal_rx_msdu_cce_metadata_get(buf);
  1393. }
  1394. /*******************************************************************************
  1395. * RX ERROR APIS
  1396. ******************************************************************************/
  1397. #define HAL_RX_MPDU_END_DECRYPT_ERR_GET(_rx_mpdu_end) \
  1398. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_end),\
  1399. RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_OFFSET)), \
  1400. RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_MASK, \
  1401. RX_MPDU_END_1_RX_IN_TX_DECRYPT_BYP_LSB))
  1402. /**
  1403. * hal_rx_mpdu_end_decrypt_err_get(): API to get the Decrypt ERR
  1404. * from rx_mpdu_end TLV
  1405. *
  1406. * @buf: pointer to the start of RX PKT TLV headers
  1407. * Return: uint32_t(decrypt_err)
  1408. */
  1409. static inline uint32_t
  1410. hal_rx_mpdu_end_decrypt_err_get(uint8_t *buf)
  1411. {
  1412. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1413. struct rx_mpdu_end *mpdu_end =
  1414. &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end;
  1415. uint32_t decrypt_err;
  1416. decrypt_err = HAL_RX_MPDU_END_DECRYPT_ERR_GET(mpdu_end);
  1417. return decrypt_err;
  1418. }
  1419. #define HAL_RX_MPDU_END_MIC_ERR_GET(_rx_mpdu_end) \
  1420. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_mpdu_end),\
  1421. RX_MPDU_END_1_TKIP_MIC_ERR_OFFSET)), \
  1422. RX_MPDU_END_1_TKIP_MIC_ERR_MASK, \
  1423. RX_MPDU_END_1_TKIP_MIC_ERR_LSB))
  1424. /**
  1425. * hal_rx_mpdu_end_mic_err_get(): API to get the MIC ERR
  1426. * from rx_mpdu_end TLV
  1427. *
  1428. * @buf: pointer to the start of RX PKT TLV headers
  1429. * Return: uint32_t(mic_err)
  1430. */
  1431. static inline uint32_t
  1432. hal_rx_mpdu_end_mic_err_get(uint8_t *buf)
  1433. {
  1434. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  1435. struct rx_mpdu_end *mpdu_end =
  1436. &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end;
  1437. uint32_t mic_err;
  1438. mic_err = HAL_RX_MPDU_END_MIC_ERR_GET(mpdu_end);
  1439. return mic_err;
  1440. }
  1441. /*******************************************************************************
  1442. * RX REO ERROR APIS
  1443. ******************************************************************************/
  1444. #define HAL_RX_NUM_MSDU_DESC 6
  1445. #define HAL_RX_MAX_SAVED_RING_DESC 16
  1446. /* TODO: rework the structure */
  1447. struct hal_rx_msdu_list {
  1448. struct hal_rx_msdu_desc_info msdu_info[HAL_RX_NUM_MSDU_DESC];
  1449. uint32_t sw_cookie[HAL_RX_NUM_MSDU_DESC];
  1450. uint8_t rbm[HAL_RX_NUM_MSDU_DESC];
  1451. /* physical address of the msdu */
  1452. uint64_t paddr[HAL_RX_NUM_MSDU_DESC];
  1453. };
  1454. struct hal_buf_info {
  1455. uint64_t paddr;
  1456. uint32_t sw_cookie;
  1457. uint8_t rbm;
  1458. };
  1459. /**
  1460. * hal_rx_link_desc_msdu0_ptr - Get pointer to rx_msdu details
  1461. * @msdu_link_ptr - msdu link ptr
  1462. * @hal - pointer to hal_soc
  1463. * Return - Pointer to rx_msdu_details structure
  1464. *
  1465. */
  1466. static inline
  1467. void *hal_rx_link_desc_msdu0_ptr(void *msdu_link_ptr,
  1468. struct hal_soc *hal_soc)
  1469. {
  1470. return hal_soc->ops->hal_rx_link_desc_msdu0_ptr(msdu_link_ptr);
  1471. }
  1472. /**
  1473. * hal_rx_msdu_desc_info_get_ptr() - Get msdu desc info ptr
  1474. * @msdu_details_ptr - Pointer to msdu_details_ptr
  1475. * @hal - pointer to hal_soc
  1476. * Return - Pointer to rx_msdu_desc_info structure.
  1477. *
  1478. */
  1479. static inline
  1480. void *hal_rx_msdu_desc_info_get_ptr(void *msdu_details_ptr,
  1481. struct hal_soc *hal_soc)
  1482. {
  1483. return hal_soc->ops->hal_rx_msdu_desc_info_get_ptr(msdu_details_ptr);
  1484. }
  1485. /* This special cookie value will be used to indicate FW allocated buffers
  1486. * received through RXDMA2SW ring for RXDMA WARs
  1487. */
  1488. #define HAL_RX_COOKIE_SPECIAL 0x1fffff
  1489. /**
  1490. * hal_rx_msdu_link_desc_get(): API to get the MSDU information
  1491. * from the MSDU link descriptor
  1492. *
  1493. * @msdu_link_desc: Opaque pointer used by HAL to get to the
  1494. * MSDU link descriptor (struct rx_msdu_link)
  1495. *
  1496. * @msdu_list: Return the list of MSDUs contained in this link descriptor
  1497. *
  1498. * @num_msdus: Number of MSDUs in the MPDU
  1499. *
  1500. * Return: void
  1501. */
  1502. static inline void hal_rx_msdu_list_get(hal_soc_handle_t hal_soc_hdl,
  1503. void *msdu_link_desc,
  1504. struct hal_rx_msdu_list *msdu_list,
  1505. uint16_t *num_msdus)
  1506. {
  1507. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1508. struct rx_msdu_details *msdu_details;
  1509. struct rx_msdu_desc_info *msdu_desc_info;
  1510. struct rx_msdu_link *msdu_link = (struct rx_msdu_link *)msdu_link_desc;
  1511. int i;
  1512. msdu_details = hal_rx_link_desc_msdu0_ptr(msdu_link, hal_soc);
  1513. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1514. "[%s][%d] msdu_link=%pK msdu_details=%pK",
  1515. __func__, __LINE__, msdu_link, msdu_details);
  1516. for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) {
  1517. /* num_msdus received in mpdu descriptor may be incorrect
  1518. * sometimes due to HW issue. Check msdu buffer address also
  1519. */
  1520. if (HAL_RX_BUFFER_ADDR_31_0_GET(
  1521. &msdu_details[i].buffer_addr_info_details) == 0) {
  1522. /* set the last msdu bit in the prev msdu_desc_info */
  1523. msdu_desc_info =
  1524. hal_rx_msdu_desc_info_get_ptr(&msdu_details[i - 1], hal_soc);
  1525. HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1);
  1526. break;
  1527. }
  1528. msdu_desc_info = hal_rx_msdu_desc_info_get_ptr(&msdu_details[i],
  1529. hal_soc);
  1530. /* set first MSDU bit or the last MSDU bit */
  1531. if (!i)
  1532. HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1);
  1533. else if (i == (HAL_RX_NUM_MSDU_DESC - 1))
  1534. HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1);
  1535. msdu_list->msdu_info[i].msdu_flags =
  1536. HAL_RX_MSDU_FLAGS_GET(msdu_desc_info);
  1537. msdu_list->msdu_info[i].msdu_len =
  1538. HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info);
  1539. msdu_list->sw_cookie[i] =
  1540. HAL_RX_BUF_COOKIE_GET(
  1541. &msdu_details[i].buffer_addr_info_details);
  1542. msdu_list->rbm[i] = HAL_RX_BUF_RBM_GET(
  1543. &msdu_details[i].buffer_addr_info_details);
  1544. msdu_list->paddr[i] = HAL_RX_BUFFER_ADDR_31_0_GET(
  1545. &msdu_details[i].buffer_addr_info_details) |
  1546. (uint64_t)HAL_RX_BUFFER_ADDR_39_32_GET(
  1547. &msdu_details[i].buffer_addr_info_details) << 32;
  1548. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  1549. "[%s][%d] i=%d sw_cookie=%d",
  1550. __func__, __LINE__, i, msdu_list->sw_cookie[i]);
  1551. }
  1552. *num_msdus = i;
  1553. }
  1554. /**
  1555. * hal_rx_msdu_reo_dst_ind_get: Gets the REO
  1556. * destination ring ID from the msdu desc info
  1557. *
  1558. * @msdu_link_desc : Opaque cookie pointer used by HAL to get to
  1559. * the current descriptor
  1560. *
  1561. * Return: dst_ind (REO destination ring ID)
  1562. */
  1563. static inline uint32_t
  1564. hal_rx_msdu_reo_dst_ind_get(hal_soc_handle_t hal_soc_hdl, void *msdu_link_desc)
  1565. {
  1566. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  1567. struct rx_msdu_details *msdu_details;
  1568. struct rx_msdu_desc_info *msdu_desc_info;
  1569. struct rx_msdu_link *msdu_link = (struct rx_msdu_link *)msdu_link_desc;
  1570. uint32_t dst_ind;
  1571. msdu_details = hal_rx_link_desc_msdu0_ptr(msdu_link, hal_soc);
  1572. /* The first msdu in the link should exsist */
  1573. msdu_desc_info = hal_rx_msdu_desc_info_get_ptr(&msdu_details[0],
  1574. hal_soc);
  1575. dst_ind = HAL_RX_MSDU_REO_DST_IND_GET(msdu_desc_info);
  1576. return dst_ind;
  1577. }
  1578. /**
  1579. * hal_rx_reo_buf_paddr_get: Gets the physical address and
  1580. * cookie from the REO destination ring element
  1581. *
  1582. * @ hal_rx_desc_cookie: Opaque cookie pointer used by HAL to get to
  1583. * the current descriptor
  1584. * @ buf_info: structure to return the buffer information
  1585. * Return: void
  1586. */
  1587. static inline
  1588. void hal_rx_reo_buf_paddr_get(hal_ring_desc_t rx_desc,
  1589. struct hal_buf_info *buf_info)
  1590. {
  1591. struct reo_destination_ring *reo_ring =
  1592. (struct reo_destination_ring *)rx_desc;
  1593. buf_info->paddr =
  1594. (HAL_RX_REO_BUFFER_ADDR_31_0_GET(reo_ring) |
  1595. ((uint64_t)(HAL_RX_REO_BUFFER_ADDR_39_32_GET(reo_ring)) << 32));
  1596. buf_info->sw_cookie = HAL_RX_REO_BUF_COOKIE_GET(reo_ring);
  1597. }
  1598. /**
  1599. * enum hal_reo_error_code: Indicates that type of buffer or descriptor
  1600. *
  1601. * @ HAL_RX_MSDU_BUF_ADDR_TYPE : Reo buffer address points to the MSDU buffer
  1602. * @ HAL_RX_MSDU_LINK_DESC_TYPE: Reo buffer address points to the link
  1603. * descriptor
  1604. */
  1605. enum hal_rx_reo_buf_type {
  1606. HAL_RX_REO_MSDU_BUF_ADDR_TYPE = 0,
  1607. HAL_RX_REO_MSDU_LINK_DESC_TYPE,
  1608. };
  1609. #define HAL_RX_REO_BUF_TYPE_GET(reo_desc) (((*(((uint32_t *) reo_desc)+ \
  1610. (REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_OFFSET >> 2))) & \
  1611. REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_MASK) >> \
  1612. REO_DESTINATION_RING_7_REO_DEST_BUFFER_TYPE_LSB)
  1613. #define HAL_RX_REO_QUEUE_NUMBER_GET(reo_desc) (((*(((uint32_t *)reo_desc) + \
  1614. (REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_OFFSET >> 2))) & \
  1615. REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_MASK) >> \
  1616. REO_DESTINATION_RING_7_RECEIVE_QUEUE_NUMBER_LSB)
  1617. /**
  1618. * enum hal_reo_error_code: Error code describing the type of error detected
  1619. *
  1620. * @ HAL_REO_ERR_QUEUE_DESC_ADDR_0 : Reo queue descriptor provided in the
  1621. * REO_ENTRANCE ring is set to 0
  1622. * @ HAL_REO_ERR_QUEUE_DESC_INVALID: Reo queue descriptor valid bit is NOT set
  1623. * @ HAL_REO_ERR_AMPDU_IN_NON_BA : AMPDU frame received without BA session
  1624. * having been setup
  1625. * @ HAL_REO_ERR_NON_BA_DUPLICATE : Non-BA session, SN equal to SSN,
  1626. * Retry bit set: duplicate frame
  1627. * @ HAL_REO_ERR_BA_DUPLICATE : BA session, duplicate frame
  1628. * @ HAL_REO_ERR_REGULAR_FRAME_2K_JUMP : A normal (management/data frame)
  1629. * received with 2K jump in SN
  1630. * @ HAL_REO_ERR_BAR_FRAME_2K_JUMP : A bar received with 2K jump in SSN
  1631. * @ HAL_REO_ERR_REGULAR_FRAME_OOR : A normal (management/data frame) received
  1632. * with SN falling within the OOR window
  1633. * @ HAL_REO_ERR_BAR_FRAME_OOR : A bar received with SSN falling within the
  1634. * OOR window
  1635. * @ HAL_REO_ERR_BAR_FRAME_NO_BA_SESSION : A bar received without a BA session
  1636. * @ HAL_REO_ERR_BAR_FRAME_SN_EQUALS_SSN : A bar received with SSN equal to SN
  1637. * @ HAL_REO_ERR_PN_CHECK_FAILED : PN Check Failed packet
  1638. * @ HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET : Frame is forwarded as a result
  1639. * of the Seq_2k_error_detected_flag been set in the REO Queue descriptor
  1640. * @ HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET : Frame is forwarded as a result
  1641. * of the pn_error_detected_flag been set in the REO Queue descriptor
  1642. * @ HAL_REO_ERR_QUEUE_DESC_BLOCKED_SET : Frame is forwarded as a result of
  1643. * the queue descriptor(address) being blocked as SW/FW seems to be currently
  1644. * in the process of making updates to this descriptor
  1645. */
  1646. enum hal_reo_error_code {
  1647. HAL_REO_ERR_QUEUE_DESC_ADDR_0 = 0,
  1648. HAL_REO_ERR_QUEUE_DESC_INVALID,
  1649. HAL_REO_ERR_AMPDU_IN_NON_BA,
  1650. HAL_REO_ERR_NON_BA_DUPLICATE,
  1651. HAL_REO_ERR_BA_DUPLICATE,
  1652. HAL_REO_ERR_REGULAR_FRAME_2K_JUMP,
  1653. HAL_REO_ERR_BAR_FRAME_2K_JUMP,
  1654. HAL_REO_ERR_REGULAR_FRAME_OOR,
  1655. HAL_REO_ERR_BAR_FRAME_OOR,
  1656. HAL_REO_ERR_BAR_FRAME_NO_BA_SESSION,
  1657. HAL_REO_ERR_BAR_FRAME_SN_EQUALS_SSN,
  1658. HAL_REO_ERR_PN_CHECK_FAILED,
  1659. HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET,
  1660. HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET,
  1661. HAL_REO_ERR_QUEUE_DESC_BLOCKED_SET,
  1662. HAL_REO_ERR_MAX
  1663. };
  1664. /**
  1665. * enum hal_rxdma_error_code: Code describing the type of RxDMA error detected
  1666. *
  1667. * @HAL_RXDMA_ERR_OVERFLOW: MPDU frame is not complete due to a FIFO overflow
  1668. * @ HAL_RXDMA_ERR_OVERFLOW : MPDU frame is not complete due to a FIFO
  1669. * overflow
  1670. * @ HAL_RXDMA_ERR_MPDU_LENGTH : MPDU frame is not complete due to receiving
  1671. * incomplete
  1672. * MPDU from the PHY
  1673. * @ HAL_RXDMA_ERR_FCS : FCS check on the MPDU frame failed
  1674. * @ HAL_RXDMA_ERR_DECRYPT : Decryption error
  1675. * @ HAL_RXDMA_ERR_TKIP_MIC : TKIP MIC error
  1676. * @ HAL_RXDMA_ERR_UNENCRYPTED : Received a frame that was expected to be
  1677. * encrypted but wasn’t
  1678. * @ HAL_RXDMA_ERR_MSDU_LEN : MSDU related length error
  1679. * @ HAL_RXDMA_ERR_MSDU_LIMIT : Number of MSDUs in the MPDUs exceeded
  1680. * the max allowed
  1681. * @ HAL_RXDMA_ERR_WIFI_PARSE : wifi parsing error
  1682. * @ HAL_RXDMA_ERR_AMSDU_PARSE : Amsdu parsing error
  1683. * @ HAL_RXDMA_ERR_SA_TIMEOUT : Source Address search timeout
  1684. * @ HAL_RXDMA_ERR_DA_TIMEOUT : Destination Address search timeout
  1685. * @ HAL_RXDMA_ERR_FLOW_TIMEOUT : Flow Search Timeout
  1686. * @ HAL_RXDMA_ERR_FLUSH_REQUEST : RxDMA FIFO Flush request
  1687. * @ HAL_RXDMA_ERR_WAR : RxDMA WAR dummy errors
  1688. */
  1689. enum hal_rxdma_error_code {
  1690. HAL_RXDMA_ERR_OVERFLOW = 0,
  1691. HAL_RXDMA_ERR_MPDU_LENGTH,
  1692. HAL_RXDMA_ERR_FCS,
  1693. HAL_RXDMA_ERR_DECRYPT,
  1694. HAL_RXDMA_ERR_TKIP_MIC,
  1695. HAL_RXDMA_ERR_UNENCRYPTED,
  1696. HAL_RXDMA_ERR_MSDU_LEN,
  1697. HAL_RXDMA_ERR_MSDU_LIMIT,
  1698. HAL_RXDMA_ERR_WIFI_PARSE,
  1699. HAL_RXDMA_ERR_AMSDU_PARSE,
  1700. HAL_RXDMA_ERR_SA_TIMEOUT,
  1701. HAL_RXDMA_ERR_DA_TIMEOUT,
  1702. HAL_RXDMA_ERR_FLOW_TIMEOUT,
  1703. HAL_RXDMA_ERR_FLUSH_REQUEST,
  1704. HAL_RXDMA_ERR_WAR = 31,
  1705. HAL_RXDMA_ERR_MAX
  1706. };
  1707. /**
  1708. * HW BM action settings in WBM release ring
  1709. */
  1710. #define HAL_BM_ACTION_PUT_IN_IDLE_LIST 0
  1711. #define HAL_BM_ACTION_RELEASE_MSDU_LIST 1
  1712. /**
  1713. * enum hal_rx_wbm_error_source: Indicates which module initiated the
  1714. * release of this buffer or descriptor
  1715. *
  1716. * @ HAL_RX_WBM_ERR_SRC_TQM : TQM released this buffer or descriptor
  1717. * @ HAL_RX_WBM_ERR_SRC_RXDMA: RXDMA released this buffer or descriptor
  1718. * @ HAL_RX_WBM_ERR_SRC_REO: REO released this buffer or descriptor
  1719. * @ HAL_RX_WBM_ERR_SRC_FW: FW released this buffer or descriptor
  1720. * @ HAL_RX_WBM_ERR_SRC_SW: SW released this buffer or descriptor
  1721. */
  1722. enum hal_rx_wbm_error_source {
  1723. HAL_RX_WBM_ERR_SRC_TQM = 0,
  1724. HAL_RX_WBM_ERR_SRC_RXDMA,
  1725. HAL_RX_WBM_ERR_SRC_REO,
  1726. HAL_RX_WBM_ERR_SRC_FW,
  1727. HAL_RX_WBM_ERR_SRC_SW,
  1728. };
  1729. /**
  1730. * enum hal_rx_wbm_buf_type: Indicates that type of buffer or descriptor
  1731. * released
  1732. *
  1733. * @ HAL_RX_WBM_ERR_SRC_TQM : TQM released this buffer or descriptor
  1734. * @ HAL_RX_WBM_ERR_SRC_RXDMA: RXDMA released this buffer or descriptor
  1735. * @ HAL_RX_WBM_ERR_SRC_REO: REO released this buffer or descriptor
  1736. * @ HAL_RX_WBM_ERR_SRC_FW: FW released this buffer or descriptor
  1737. * @ HAL_RX_WBM_ERR_SRC_SW: SW released this buffer or descriptor
  1738. */
  1739. enum hal_rx_wbm_buf_type {
  1740. HAL_RX_WBM_BUF_TYPE_REL_BUF = 0,
  1741. HAL_RX_WBM_BUF_TYPE_MSDU_LINK_DESC,
  1742. HAL_RX_WBM_BUF_TYPE_MPDU_LINK_DESC,
  1743. HAL_RX_WBM_BUF_TYPE_MSDU_EXT_DESC,
  1744. HAL_RX_WBM_BUF_TYPE_Q_EXT_DESC,
  1745. };
  1746. #define HAL_RX_REO_ERROR_GET(reo_desc) (((*(((uint32_t *) reo_desc)+ \
  1747. (REO_DESTINATION_RING_7_REO_ERROR_CODE_OFFSET >> 2))) & \
  1748. REO_DESTINATION_RING_7_REO_ERROR_CODE_MASK) >> \
  1749. REO_DESTINATION_RING_7_REO_ERROR_CODE_LSB)
  1750. /**
  1751. * hal_rx_is_pn_error() - Indicate if this error was caused by a
  1752. * PN check failure
  1753. *
  1754. * @reo_desc: opaque pointer used by HAL to get the REO destination entry
  1755. *
  1756. * Return: true: error caused by PN check, false: other error
  1757. */
  1758. static inline bool hal_rx_reo_is_pn_error(hal_ring_desc_t rx_desc)
  1759. {
  1760. struct reo_destination_ring *reo_desc =
  1761. (struct reo_destination_ring *)rx_desc;
  1762. return ((HAL_RX_REO_ERROR_GET(reo_desc) ==
  1763. HAL_REO_ERR_PN_CHECK_FAILED) |
  1764. (HAL_RX_REO_ERROR_GET(reo_desc) ==
  1765. HAL_REO_ERR_PN_ERROR_HANDLING_FLAG_SET)) ?
  1766. true : false;
  1767. }
  1768. /**
  1769. * hal_rx_is_2k_jump() - Indicate if this error was caused by a 2K jump in
  1770. * the sequence number
  1771. *
  1772. * @ring_desc: opaque pointer used by HAL to get the REO destination entry
  1773. *
  1774. * Return: true: error caused by 2K jump, false: other error
  1775. */
  1776. static inline bool hal_rx_reo_is_2k_jump(hal_ring_desc_t rx_desc)
  1777. {
  1778. struct reo_destination_ring *reo_desc =
  1779. (struct reo_destination_ring *)rx_desc;
  1780. return ((HAL_RX_REO_ERROR_GET(reo_desc) ==
  1781. HAL_REO_ERR_REGULAR_FRAME_2K_JUMP) |
  1782. (HAL_RX_REO_ERROR_GET(reo_desc) ==
  1783. HAL_REO_ERR_2K_ERROR_HANDLING_FLAG_SET)) ?
  1784. true : false;
  1785. }
  1786. #define HAL_WBM_RELEASE_RING_DESC_LEN_DWORDS (NUM_OF_DWORDS_WBM_RELEASE_RING)
  1787. /**
  1788. * hal_dump_wbm_rel_desc() - dump wbm release descriptor
  1789. * @hal_desc: hardware descriptor pointer
  1790. *
  1791. * This function will print wbm release descriptor
  1792. *
  1793. * Return: none
  1794. */
  1795. static inline void hal_dump_wbm_rel_desc(void *src_srng_desc)
  1796. {
  1797. uint32_t *wbm_comp = (uint32_t *)src_srng_desc;
  1798. uint32_t i;
  1799. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL,
  1800. "Current Rx wbm release descriptor is");
  1801. for (i = 0; i < HAL_WBM_RELEASE_RING_DESC_LEN_DWORDS; i++) {
  1802. QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_FATAL,
  1803. "DWORD[i] = 0x%x", wbm_comp[i]);
  1804. }
  1805. }
  1806. /**
  1807. * hal_rx_msdu_link_desc_set: Retrieves MSDU Link Descriptor to WBM
  1808. *
  1809. * @ hal_soc_hdl : HAL version of the SOC pointer
  1810. * @ src_srng_desc : void pointer to the WBM Release Ring descriptor
  1811. * @ buf_addr_info : void pointer to the buffer_addr_info
  1812. * @ bm_action : put in IDLE list or release to MSDU_LIST
  1813. *
  1814. * Return: void
  1815. */
  1816. /* look at implementation at dp_hw_link_desc_pool_setup()*/
  1817. static inline
  1818. void hal_rx_msdu_link_desc_set(hal_soc_handle_t hal_soc_hdl,
  1819. void *src_srng_desc,
  1820. hal_buff_addrinfo_t buf_addr_info,
  1821. uint8_t bm_action)
  1822. {
  1823. struct wbm_release_ring *wbm_rel_srng =
  1824. (struct wbm_release_ring *)src_srng_desc;
  1825. uint32_t addr_31_0;
  1826. uint8_t addr_39_32;
  1827. /* Structure copy !!! */
  1828. wbm_rel_srng->released_buff_or_desc_addr_info =
  1829. *((struct buffer_addr_info *)buf_addr_info);
  1830. addr_31_0 =
  1831. wbm_rel_srng->released_buff_or_desc_addr_info.buffer_addr_31_0;
  1832. addr_39_32 =
  1833. wbm_rel_srng->released_buff_or_desc_addr_info.buffer_addr_39_32;
  1834. HAL_DESC_SET_FIELD(src_srng_desc, WBM_RELEASE_RING_2,
  1835. RELEASE_SOURCE_MODULE, HAL_RX_WBM_ERR_SRC_SW);
  1836. HAL_DESC_SET_FIELD(src_srng_desc, WBM_RELEASE_RING_2, BM_ACTION,
  1837. bm_action);
  1838. HAL_DESC_SET_FIELD(src_srng_desc, WBM_RELEASE_RING_2,
  1839. BUFFER_OR_DESC_TYPE, HAL_RX_WBM_BUF_TYPE_MSDU_LINK_DESC);
  1840. /* WBM error is indicated when any of the link descriptors given to
  1841. * WBM has a NULL address, and one those paths is the link descriptors
  1842. * released from host after processing RXDMA errors,
  1843. * or from Rx defrag path, and we want to add an assert here to ensure
  1844. * host is not releasing descriptors with NULL address.
  1845. */
  1846. if (qdf_unlikely(!addr_31_0 && !addr_39_32)) {
  1847. hal_dump_wbm_rel_desc(src_srng_desc);
  1848. qdf_assert_always(0);
  1849. }
  1850. }
  1851. /*
  1852. * hal_rx_msdu_link_desc_reinject: Re-injects the MSDU link descriptor to
  1853. * REO entrance ring
  1854. *
  1855. * @ soc: HAL version of the SOC pointer
  1856. * @ pa: Physical address of the MSDU Link Descriptor
  1857. * @ cookie: SW cookie to get to the virtual address
  1858. * @ error_enabled_reo_q: Argument to determine whether this needs to go
  1859. * to the error enabled REO queue
  1860. *
  1861. * Return: void
  1862. */
  1863. static inline void hal_rx_msdu_link_desc_reinject(struct hal_soc *soc,
  1864. uint64_t pa, uint32_t cookie, bool error_enabled_reo_q)
  1865. {
  1866. /* TODO */
  1867. }
  1868. /**
  1869. * HAL_RX_BUF_ADDR_INFO_GET: Returns the address of the
  1870. * BUFFER_ADDR_INFO, give the RX descriptor
  1871. * (Assumption -- BUFFER_ADDR_INFO is the
  1872. * first field in the descriptor structure)
  1873. */
  1874. #define HAL_RX_BUF_ADDR_INFO_GET(ring_desc) \
  1875. ((hal_link_desc_t)(ring_desc))
  1876. #define HAL_RX_REO_BUF_ADDR_INFO_GET HAL_RX_BUF_ADDR_INFO_GET
  1877. #define HAL_RX_WBM_BUF_ADDR_INFO_GET HAL_RX_BUF_ADDR_INFO_GET
  1878. /**
  1879. * hal_rx_ret_buf_manager_get: Returns the "return_buffer_manager"
  1880. * from the BUFFER_ADDR_INFO structure
  1881. * given a REO destination ring descriptor.
  1882. * @ ring_desc: RX(REO/WBM release) destination ring descriptor
  1883. *
  1884. * Return: uint8_t (value of the return_buffer_manager)
  1885. */
  1886. static inline
  1887. uint8_t hal_rx_ret_buf_manager_get(hal_ring_desc_t ring_desc)
  1888. {
  1889. /*
  1890. * The following macro takes buf_addr_info as argument,
  1891. * but since buf_addr_info is the first field in ring_desc
  1892. * Hence the following call is OK
  1893. */
  1894. return HAL_RX_BUF_RBM_GET(ring_desc);
  1895. }
  1896. /*******************************************************************************
  1897. * RX WBM ERROR APIS
  1898. ******************************************************************************/
  1899. #define HAL_RX_WBM_BUF_TYPE_GET(wbm_desc) (((*(((uint32_t *) wbm_desc)+ \
  1900. (WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_OFFSET >> 2))) & \
  1901. WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_MASK) >> \
  1902. WBM_RELEASE_RING_2_BUFFER_OR_DESC_TYPE_LSB)
  1903. /**
  1904. * enum - hal_rx_wbm_reo_push_reason: Indicates why REO pushed
  1905. * the frame to this release ring
  1906. *
  1907. * @ HAL_RX_WBM_REO_PSH_RSN_ERROR : Reo detected an error and pushed this
  1908. * frame to this queue
  1909. * @ HAL_RX_WBM_REO_PSH_RSN_ROUTE: Reo pushed the frame to this queue per
  1910. * received routing instructions. No error within REO was detected
  1911. */
  1912. enum hal_rx_wbm_reo_push_reason {
  1913. HAL_RX_WBM_REO_PSH_RSN_ERROR = 0,
  1914. HAL_RX_WBM_REO_PSH_RSN_ROUTE,
  1915. };
  1916. /**
  1917. * enum hal_rx_wbm_rxdma_push_reason: Indicates why REO pushed the frame to
  1918. * this release ring
  1919. *
  1920. * @ HAL_RX_WBM_RXDMA_PSH_RSN_ERROR : RXDMA detected an error and pushed
  1921. * this frame to this queue
  1922. * @ HAL_RX_WBM_RXDMA_PSH_RSN_ROUTE: RXDMA pushed the frame to this queue
  1923. * per received routing instructions. No error within RXDMA was detected
  1924. */
  1925. enum hal_rx_wbm_rxdma_push_reason {
  1926. HAL_RX_WBM_RXDMA_PSH_RSN_ERROR = 0,
  1927. HAL_RX_WBM_RXDMA_PSH_RSN_ROUTE,
  1928. };
  1929. #define HAL_RX_WBM_FIRST_MSDU_GET(wbm_desc) \
  1930. (((*(((uint32_t *) wbm_desc) + \
  1931. (WBM_RELEASE_RING_4_FIRST_MSDU_OFFSET >> 2))) & \
  1932. WBM_RELEASE_RING_4_FIRST_MSDU_MASK) >> \
  1933. WBM_RELEASE_RING_4_FIRST_MSDU_LSB)
  1934. #define HAL_RX_WBM_LAST_MSDU_GET(wbm_desc) \
  1935. (((*(((uint32_t *) wbm_desc) + \
  1936. (WBM_RELEASE_RING_4_LAST_MSDU_OFFSET >> 2))) & \
  1937. WBM_RELEASE_RING_4_LAST_MSDU_MASK) >> \
  1938. WBM_RELEASE_RING_4_LAST_MSDU_LSB)
  1939. #define HAL_RX_WBM_BUF_COOKIE_GET(wbm_desc) \
  1940. HAL_RX_BUF_COOKIE_GET(&((struct wbm_release_ring *) \
  1941. wbm_desc)->released_buff_or_desc_addr_info)
  1942. /**
  1943. * hal_rx_dump_rx_attention_tlv: dump RX attention TLV in structured
  1944. * humman readable format.
  1945. * @ rx_attn: pointer the rx_attention TLV in pkt.
  1946. * @ dbg_level: log level.
  1947. *
  1948. * Return: void
  1949. */
  1950. static inline void hal_rx_dump_rx_attention_tlv(struct rx_attention *rx_attn,
  1951. uint8_t dbg_level)
  1952. {
  1953. hal_verbose_debug(
  1954. "rx_attention tlv (1/2) - "
  1955. "rxpcu_mpdu_filter_in_category: %x "
  1956. "sw_frame_group_id: %x "
  1957. "reserved_0: %x "
  1958. "phy_ppdu_id: %x "
  1959. "first_mpdu : %x "
  1960. "reserved_1a: %x "
  1961. "mcast_bcast: %x "
  1962. "ast_index_not_found: %x "
  1963. "ast_index_timeout: %x "
  1964. "power_mgmt: %x "
  1965. "non_qos: %x "
  1966. "null_data: %x "
  1967. "mgmt_type: %x "
  1968. "ctrl_type: %x "
  1969. "more_data: %x "
  1970. "eosp: %x "
  1971. "a_msdu_error: %x "
  1972. "fragment_flag: %x "
  1973. "order: %x "
  1974. "cce_match: %x "
  1975. "overflow_err: %x "
  1976. "msdu_length_err: %x "
  1977. "tcp_udp_chksum_fail: %x "
  1978. "ip_chksum_fail: %x "
  1979. "sa_idx_invalid: %x "
  1980. "da_idx_invalid: %x "
  1981. "reserved_1b: %x "
  1982. "rx_in_tx_decrypt_byp: %x ",
  1983. rx_attn->rxpcu_mpdu_filter_in_category,
  1984. rx_attn->sw_frame_group_id,
  1985. rx_attn->reserved_0,
  1986. rx_attn->phy_ppdu_id,
  1987. rx_attn->first_mpdu,
  1988. rx_attn->reserved_1a,
  1989. rx_attn->mcast_bcast,
  1990. rx_attn->ast_index_not_found,
  1991. rx_attn->ast_index_timeout,
  1992. rx_attn->power_mgmt,
  1993. rx_attn->non_qos,
  1994. rx_attn->null_data,
  1995. rx_attn->mgmt_type,
  1996. rx_attn->ctrl_type,
  1997. rx_attn->more_data,
  1998. rx_attn->eosp,
  1999. rx_attn->a_msdu_error,
  2000. rx_attn->fragment_flag,
  2001. rx_attn->order,
  2002. rx_attn->cce_match,
  2003. rx_attn->overflow_err,
  2004. rx_attn->msdu_length_err,
  2005. rx_attn->tcp_udp_chksum_fail,
  2006. rx_attn->ip_chksum_fail,
  2007. rx_attn->sa_idx_invalid,
  2008. rx_attn->da_idx_invalid,
  2009. rx_attn->reserved_1b,
  2010. rx_attn->rx_in_tx_decrypt_byp);
  2011. hal_verbose_debug(
  2012. "rx_attention tlv (2/2) - "
  2013. "encrypt_required: %x "
  2014. "directed: %x "
  2015. "buffer_fragment: %x "
  2016. "mpdu_length_err: %x "
  2017. "tkip_mic_err: %x "
  2018. "decrypt_err: %x "
  2019. "unencrypted_frame_err: %x "
  2020. "fcs_err: %x "
  2021. "flow_idx_timeout: %x "
  2022. "flow_idx_invalid: %x "
  2023. "wifi_parser_error: %x "
  2024. "amsdu_parser_error: %x "
  2025. "sa_idx_timeout: %x "
  2026. "da_idx_timeout: %x "
  2027. "msdu_limit_error: %x "
  2028. "da_is_valid: %x "
  2029. "da_is_mcbc: %x "
  2030. "sa_is_valid: %x "
  2031. "decrypt_status_code: %x "
  2032. "rx_bitmap_not_updated: %x "
  2033. "reserved_2: %x "
  2034. "msdu_done: %x ",
  2035. rx_attn->encrypt_required,
  2036. rx_attn->directed,
  2037. rx_attn->buffer_fragment,
  2038. rx_attn->mpdu_length_err,
  2039. rx_attn->tkip_mic_err,
  2040. rx_attn->decrypt_err,
  2041. rx_attn->unencrypted_frame_err,
  2042. rx_attn->fcs_err,
  2043. rx_attn->flow_idx_timeout,
  2044. rx_attn->flow_idx_invalid,
  2045. rx_attn->wifi_parser_error,
  2046. rx_attn->amsdu_parser_error,
  2047. rx_attn->sa_idx_timeout,
  2048. rx_attn->da_idx_timeout,
  2049. rx_attn->msdu_limit_error,
  2050. rx_attn->da_is_valid,
  2051. rx_attn->da_is_mcbc,
  2052. rx_attn->sa_is_valid,
  2053. rx_attn->decrypt_status_code,
  2054. rx_attn->rx_bitmap_not_updated,
  2055. rx_attn->reserved_2,
  2056. rx_attn->msdu_done);
  2057. }
  2058. static inline void hal_rx_dump_mpdu_start_tlv(struct rx_mpdu_start *mpdu_start,
  2059. uint8_t dbg_level,
  2060. struct hal_soc *hal)
  2061. {
  2062. hal->ops->hal_rx_dump_mpdu_start_tlv(mpdu_start, dbg_level);
  2063. }
  2064. /**
  2065. * hal_rx_dump_msdu_end_tlv: dump RX msdu_end TLV in structured
  2066. * human readable format.
  2067. * @ msdu_end: pointer the msdu_end TLV in pkt.
  2068. * @ dbg_level: log level.
  2069. *
  2070. * Return: void
  2071. */
  2072. static inline void hal_rx_dump_msdu_end_tlv(struct hal_soc *hal_soc,
  2073. struct rx_msdu_end *msdu_end,
  2074. uint8_t dbg_level)
  2075. {
  2076. hal_soc->ops->hal_rx_dump_msdu_end_tlv(msdu_end, dbg_level);
  2077. }
  2078. /**
  2079. * hal_rx_dump_mpdu_end_tlv: dump RX mpdu_end TLV in structured
  2080. * human readable format.
  2081. * @ mpdu_end: pointer the mpdu_end TLV in pkt.
  2082. * @ dbg_level: log level.
  2083. *
  2084. * Return: void
  2085. */
  2086. static inline void hal_rx_dump_mpdu_end_tlv(struct rx_mpdu_end *mpdu_end,
  2087. uint8_t dbg_level)
  2088. {
  2089. hal_verbose_debug(
  2090. "rx_mpdu_end tlv - "
  2091. "rxpcu_mpdu_filter_in_category: %x "
  2092. "sw_frame_group_id: %x "
  2093. "phy_ppdu_id: %x "
  2094. "unsup_ktype_short_frame: %x "
  2095. "rx_in_tx_decrypt_byp: %x "
  2096. "overflow_err: %x "
  2097. "mpdu_length_err: %x "
  2098. "tkip_mic_err: %x "
  2099. "decrypt_err: %x "
  2100. "unencrypted_frame_err: %x "
  2101. "pn_fields_contain_valid_info: %x "
  2102. "fcs_err: %x "
  2103. "msdu_length_err: %x "
  2104. "rxdma0_destination_ring: %x "
  2105. "rxdma1_destination_ring: %x "
  2106. "decrypt_status_code: %x "
  2107. "rx_bitmap_not_updated: %x ",
  2108. mpdu_end->rxpcu_mpdu_filter_in_category,
  2109. mpdu_end->sw_frame_group_id,
  2110. mpdu_end->phy_ppdu_id,
  2111. mpdu_end->unsup_ktype_short_frame,
  2112. mpdu_end->rx_in_tx_decrypt_byp,
  2113. mpdu_end->overflow_err,
  2114. mpdu_end->mpdu_length_err,
  2115. mpdu_end->tkip_mic_err,
  2116. mpdu_end->decrypt_err,
  2117. mpdu_end->unencrypted_frame_err,
  2118. mpdu_end->pn_fields_contain_valid_info,
  2119. mpdu_end->fcs_err,
  2120. mpdu_end->msdu_length_err,
  2121. mpdu_end->rxdma0_destination_ring,
  2122. mpdu_end->rxdma1_destination_ring,
  2123. mpdu_end->decrypt_status_code,
  2124. mpdu_end->rx_bitmap_not_updated);
  2125. }
  2126. #ifdef NO_RX_PKT_HDR_TLV
  2127. static inline void hal_rx_dump_pkt_hdr_tlv(struct rx_pkt_tlvs *pkt_tlvs,
  2128. uint8_t dbg_level)
  2129. {
  2130. }
  2131. #else
  2132. /**
  2133. * hal_rx_dump_pkt_hdr_tlv: dump RX pkt header TLV in hex format
  2134. * @ pkt_hdr_tlv: pointer the pkt_hdr_tlv in pkt.
  2135. * @ dbg_level: log level.
  2136. *
  2137. * Return: void
  2138. */
  2139. static inline void hal_rx_dump_pkt_hdr_tlv(struct rx_pkt_tlvs *pkt_tlvs,
  2140. uint8_t dbg_level)
  2141. {
  2142. struct rx_pkt_hdr_tlv *pkt_hdr_tlv = &pkt_tlvs->pkt_hdr_tlv;
  2143. hal_verbose_debug(
  2144. "\n---------------\n"
  2145. "rx_pkt_hdr_tlv \n"
  2146. "---------------\n"
  2147. "phy_ppdu_id %d ",
  2148. pkt_hdr_tlv->phy_ppdu_id);
  2149. hal_verbose_hex_dump(pkt_hdr_tlv->rx_pkt_hdr, 128);
  2150. }
  2151. #endif
  2152. /**
  2153. * hal_srng_ring_id_get: API to retrieve ring id from hal ring
  2154. * structure
  2155. * @hal_ring: pointer to hal_srng structure
  2156. *
  2157. * Return: ring_id
  2158. */
  2159. static inline uint8_t hal_srng_ring_id_get(hal_ring_handle_t hal_ring_hdl)
  2160. {
  2161. return ((struct hal_srng *)hal_ring_hdl)->ring_id;
  2162. }
  2163. /* Rx MSDU link pointer info */
  2164. struct hal_rx_msdu_link_ptr_info {
  2165. struct rx_msdu_link msdu_link;
  2166. struct hal_buf_info msdu_link_buf_info;
  2167. };
  2168. /**
  2169. * hal_rx_get_pkt_tlvs(): Function to retrieve pkt tlvs from nbuf
  2170. *
  2171. * @nbuf: Pointer to data buffer field
  2172. * Returns: pointer to rx_pkt_tlvs
  2173. */
  2174. static inline
  2175. struct rx_pkt_tlvs *hal_rx_get_pkt_tlvs(uint8_t *rx_buf_start)
  2176. {
  2177. return (struct rx_pkt_tlvs *)rx_buf_start;
  2178. }
  2179. /**
  2180. * hal_rx_get_mpdu_info(): Function to retrieve mpdu info from pkt tlvs
  2181. *
  2182. * @pkt_tlvs: Pointer to pkt_tlvs
  2183. * Returns: pointer to rx_mpdu_info structure
  2184. */
  2185. static inline
  2186. struct rx_mpdu_info *hal_rx_get_mpdu_info(struct rx_pkt_tlvs *pkt_tlvs)
  2187. {
  2188. return &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details;
  2189. }
  2190. #define DOT11_SEQ_FRAG_MASK 0x000f
  2191. #define DOT11_FC1_MORE_FRAG_OFFSET 0x04
  2192. /**
  2193. * hal_rx_get_rx_fragment_number(): Function to retrieve rx fragment number
  2194. *
  2195. * @nbuf: Network buffer
  2196. * Returns: rx fragment number
  2197. */
  2198. static inline
  2199. uint8_t hal_rx_get_rx_fragment_number(struct hal_soc *hal_soc,
  2200. uint8_t *buf)
  2201. {
  2202. return hal_soc->ops->hal_rx_get_rx_fragment_number(buf);
  2203. }
  2204. #define HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(_rx_mpdu_info) \
  2205. (_HAL_MS((*_OFFSET_TO_WORD_PTR(_rx_mpdu_info, \
  2206. RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_OFFSET)), \
  2207. RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_MASK, \
  2208. RX_MPDU_INFO_14_MPDU_FRAME_CONTROL_FIELD_LSB))
  2209. /**
  2210. * hal_rx_get_rx_more_frag_bit(): Function to retrieve more fragment bit
  2211. *
  2212. * @nbuf: Network buffer
  2213. * Returns: rx more fragment bit
  2214. */
  2215. static inline
  2216. uint8_t hal_rx_get_rx_more_frag_bit(uint8_t *buf)
  2217. {
  2218. struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
  2219. struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
  2220. uint16_t frame_ctrl = 0;
  2221. frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info) >>
  2222. DOT11_FC1_MORE_FRAG_OFFSET;
  2223. /* more fragment bit if at offset bit 4 */
  2224. return frame_ctrl;
  2225. }
  2226. /**
  2227. * hal_rx_get_frame_ctrl_field(): Function to retrieve frame control field
  2228. *
  2229. * @nbuf: Network buffer
  2230. * Returns: rx more fragment bit
  2231. *
  2232. */
  2233. static inline
  2234. uint16_t hal_rx_get_frame_ctrl_field(uint8_t *buf)
  2235. {
  2236. struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
  2237. struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
  2238. uint16_t frame_ctrl = 0;
  2239. frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info);
  2240. return frame_ctrl;
  2241. }
  2242. /*
  2243. * hal_rx_msdu_is_wlan_mcast(): Check if the buffer is for multicast address
  2244. *
  2245. * @nbuf: Network buffer
  2246. * Returns: flag to indicate whether the nbuf has MC/BC address
  2247. */
  2248. static inline
  2249. uint32_t hal_rx_msdu_is_wlan_mcast(qdf_nbuf_t nbuf)
  2250. {
  2251. uint8 *buf = qdf_nbuf_data(nbuf);
  2252. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  2253. struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
  2254. return rx_attn->mcast_bcast;
  2255. }
  2256. /*
  2257. * hal_rx_get_mpdu_sequence_control_valid(): Get mpdu sequence control valid
  2258. * @hal_soc_hdl: hal soc handle
  2259. * @nbuf: Network buffer
  2260. *
  2261. * Return: value of sequence control valid field
  2262. */
  2263. static inline
  2264. uint8_t hal_rx_get_mpdu_sequence_control_valid(hal_soc_handle_t hal_soc_hdl,
  2265. uint8_t *buf)
  2266. {
  2267. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2268. return hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid(buf);
  2269. }
  2270. /*
  2271. * hal_rx_get_mpdu_frame_control_valid(): Retrieves mpdu frame control valid
  2272. * @hal_soc_hdl: hal soc handle
  2273. * @nbuf: Network buffer
  2274. *
  2275. * Returns: value of frame control valid field
  2276. */
  2277. static inline
  2278. uint8_t hal_rx_get_mpdu_frame_control_valid(hal_soc_handle_t hal_soc_hdl,
  2279. uint8_t *buf)
  2280. {
  2281. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2282. return hal_soc->ops->hal_rx_get_mpdu_frame_control_valid(buf);
  2283. }
  2284. /**
  2285. * hal_rx_get_mpdu_mac_ad4_valid(): Retrieves if mpdu 4th addr is valid
  2286. * @hal_soc_hdl: hal soc handle
  2287. * @nbuf: Network buffer
  2288. * Returns: value of mpdu 4th address valid field
  2289. */
  2290. static inline
  2291. bool hal_rx_get_mpdu_mac_ad4_valid(hal_soc_handle_t hal_soc_hdl,
  2292. uint8_t *buf)
  2293. {
  2294. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2295. return hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid(buf);
  2296. }
  2297. /*
  2298. * hal_rx_clear_mpdu_desc_info(): Clears mpdu_desc_info
  2299. *
  2300. * @rx_mpdu_desc_info: HAL view of rx mpdu desc info
  2301. * Returns: None
  2302. */
  2303. static inline
  2304. void hal_rx_clear_mpdu_desc_info(
  2305. struct hal_rx_mpdu_desc_info *rx_mpdu_desc_info)
  2306. {
  2307. qdf_mem_zero(rx_mpdu_desc_info,
  2308. sizeof(*rx_mpdu_desc_info));
  2309. }
  2310. /*
  2311. * hal_rx_clear_msdu_link_ptr(): Clears msdu_link_ptr
  2312. *
  2313. * @msdu_link_ptr: HAL view of msdu link ptr
  2314. * @size: number of msdu link pointers
  2315. * Returns: None
  2316. */
  2317. static inline
  2318. void hal_rx_clear_msdu_link_ptr(struct hal_rx_msdu_link_ptr_info *msdu_link_ptr,
  2319. int size)
  2320. {
  2321. qdf_mem_zero(msdu_link_ptr,
  2322. (sizeof(*msdu_link_ptr) * size));
  2323. }
  2324. /*
  2325. * hal_rx_chain_msdu_links() - Chains msdu link pointers
  2326. * @msdu_link_ptr: msdu link pointer
  2327. * @mpdu_desc_info: mpdu descriptor info
  2328. *
  2329. * Build a list of msdus using msdu link pointer. If the
  2330. * number of msdus are more, chain them together
  2331. *
  2332. * Returns: Number of processed msdus
  2333. */
  2334. static inline
  2335. int hal_rx_chain_msdu_links(struct hal_soc *hal_soc, qdf_nbuf_t msdu,
  2336. struct hal_rx_msdu_link_ptr_info *msdu_link_ptr_info,
  2337. struct hal_rx_mpdu_desc_info *mpdu_desc_info)
  2338. {
  2339. int j;
  2340. struct rx_msdu_link *msdu_link_ptr =
  2341. &msdu_link_ptr_info->msdu_link;
  2342. struct rx_msdu_link *prev_msdu_link_ptr = NULL;
  2343. struct rx_msdu_details *msdu_details =
  2344. hal_rx_link_desc_msdu0_ptr(msdu_link_ptr, hal_soc);
  2345. uint8_t num_msdus = mpdu_desc_info->msdu_count;
  2346. struct rx_msdu_desc_info *msdu_desc_info;
  2347. uint8_t fragno, more_frag;
  2348. uint8_t *rx_desc_info;
  2349. struct hal_rx_msdu_list msdu_list;
  2350. for (j = 0; j < num_msdus; j++) {
  2351. msdu_desc_info =
  2352. hal_rx_msdu_desc_info_get_ptr(&msdu_details[j],
  2353. hal_soc);
  2354. msdu_list.msdu_info[j].msdu_flags =
  2355. HAL_RX_MSDU_FLAGS_GET(msdu_desc_info);
  2356. msdu_list.msdu_info[j].msdu_len =
  2357. HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info);
  2358. msdu_list.sw_cookie[j] = HAL_RX_BUF_COOKIE_GET(
  2359. &msdu_details[j].buffer_addr_info_details);
  2360. }
  2361. /* Chain msdu links together */
  2362. if (prev_msdu_link_ptr) {
  2363. /* 31-0 bits of the physical address */
  2364. prev_msdu_link_ptr->
  2365. next_msdu_link_desc_addr_info.buffer_addr_31_0 =
  2366. msdu_link_ptr_info->msdu_link_buf_info.paddr &
  2367. BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK;
  2368. /* 39-32 bits of the physical address */
  2369. prev_msdu_link_ptr->
  2370. next_msdu_link_desc_addr_info.buffer_addr_39_32
  2371. = ((msdu_link_ptr_info->msdu_link_buf_info.paddr
  2372. >> 32) &
  2373. BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK);
  2374. prev_msdu_link_ptr->
  2375. next_msdu_link_desc_addr_info.sw_buffer_cookie =
  2376. msdu_link_ptr_info->msdu_link_buf_info.sw_cookie;
  2377. }
  2378. /* There is space for only 6 MSDUs in a MSDU link descriptor */
  2379. if (num_msdus < HAL_RX_NUM_MSDU_DESC) {
  2380. /* mark first and last MSDUs */
  2381. rx_desc_info = qdf_nbuf_data(msdu);
  2382. fragno = hal_rx_get_rx_fragment_number(hal_soc, rx_desc_info);
  2383. more_frag = hal_rx_get_rx_more_frag_bit(rx_desc_info);
  2384. /* TODO: create skb->fragslist[] */
  2385. if (more_frag == 0) {
  2386. msdu_list.msdu_info[num_msdus].msdu_flags |=
  2387. RX_MSDU_DESC_INFO_0_LAST_MSDU_IN_MPDU_FLAG_MASK;
  2388. } else if (fragno == 1) {
  2389. msdu_list.msdu_info[num_msdus].msdu_flags |=
  2390. RX_MSDU_DESC_INFO_0_FIRST_MSDU_IN_MPDU_FLAG_MASK;
  2391. msdu_list.msdu_info[num_msdus].msdu_flags |=
  2392. RX_MSDU_DESC_INFO_0_MSDU_CONTINUATION_MASK;
  2393. }
  2394. num_msdus++;
  2395. /* Number of MSDUs per mpdu descriptor is updated */
  2396. mpdu_desc_info->msdu_count += num_msdus;
  2397. } else {
  2398. num_msdus = 0;
  2399. prev_msdu_link_ptr = msdu_link_ptr;
  2400. }
  2401. return num_msdus;
  2402. }
  2403. /*
  2404. * hal_rx_defrag_update_src_ring_desc(): updates reo src ring desc
  2405. *
  2406. * @ring_desc: HAL view of ring descriptor
  2407. * @mpdu_des_info: saved mpdu desc info
  2408. * @msdu_link_ptr: saved msdu link ptr
  2409. *
  2410. * API used explicitly for rx defrag to update ring desc with
  2411. * mpdu desc info and msdu link ptr before reinjecting the
  2412. * packet back to REO
  2413. *
  2414. * Returns: None
  2415. */
  2416. static inline
  2417. void hal_rx_defrag_update_src_ring_desc(
  2418. hal_ring_desc_t ring_desc,
  2419. void *saved_mpdu_desc_info,
  2420. struct hal_rx_msdu_link_ptr_info *saved_msdu_link_ptr)
  2421. {
  2422. struct reo_entrance_ring *reo_ent_ring;
  2423. struct rx_mpdu_desc_info *reo_ring_mpdu_desc_info;
  2424. struct hal_buf_info buf_info;
  2425. reo_ent_ring = (struct reo_entrance_ring *)ring_desc;
  2426. reo_ring_mpdu_desc_info = &reo_ent_ring->
  2427. reo_level_mpdu_frame_info.rx_mpdu_desc_info_details;
  2428. qdf_mem_copy(&reo_ring_mpdu_desc_info, saved_mpdu_desc_info,
  2429. sizeof(*reo_ring_mpdu_desc_info));
  2430. /*
  2431. * TODO: Check for additional fields that need configuration in
  2432. * reo_ring_mpdu_desc_info
  2433. */
  2434. /* Update msdu_link_ptr in the reo entrance ring */
  2435. hal_rx_reo_buf_paddr_get(ring_desc, &buf_info);
  2436. buf_info.paddr = saved_msdu_link_ptr->msdu_link_buf_info.paddr;
  2437. buf_info.sw_cookie =
  2438. saved_msdu_link_ptr->msdu_link_buf_info.sw_cookie;
  2439. }
  2440. /*
  2441. * hal_rx_defrag_save_info_from_ring_desc(): Saves info from ring desc
  2442. *
  2443. * @msdu_link_desc_va: msdu link descriptor handle
  2444. * @msdu_link_ptr_info: HAL view of msdu link pointer info
  2445. *
  2446. * API used to save msdu link information along with physical
  2447. * address. The API also copues the sw cookie.
  2448. *
  2449. * Returns: None
  2450. */
  2451. static inline
  2452. void hal_rx_defrag_save_info_from_ring_desc(void *msdu_link_desc_va,
  2453. struct hal_rx_msdu_link_ptr_info *msdu_link_ptr_info,
  2454. struct hal_buf_info *hbi)
  2455. {
  2456. struct rx_msdu_link *msdu_link_ptr =
  2457. (struct rx_msdu_link *)msdu_link_desc_va;
  2458. qdf_mem_copy(&msdu_link_ptr_info->msdu_link, msdu_link_ptr,
  2459. sizeof(struct rx_msdu_link));
  2460. msdu_link_ptr_info->msdu_link_buf_info.paddr = hbi->paddr;
  2461. msdu_link_ptr_info->msdu_link_buf_info.sw_cookie = hbi->sw_cookie;
  2462. }
  2463. /*
  2464. * hal_rx_get_desc_len(): Returns rx descriptor length
  2465. *
  2466. * Returns the size of rx_pkt_tlvs which follows the
  2467. * data in the nbuf
  2468. *
  2469. * Returns: Length of rx descriptor
  2470. */
  2471. static inline
  2472. uint16_t hal_rx_get_desc_len(void)
  2473. {
  2474. return sizeof(struct rx_pkt_tlvs);
  2475. }
  2476. /*
  2477. * hal_rx_reo_ent_rxdma_push_reason_get(): Retrieves RXDMA push reason from
  2478. * reo_entrance_ring descriptor
  2479. *
  2480. * @reo_ent_desc: reo_entrance_ring descriptor
  2481. * Returns: value of rxdma_push_reason
  2482. */
  2483. static inline
  2484. uint8_t hal_rx_reo_ent_rxdma_push_reason_get(hal_rxdma_desc_t reo_ent_desc)
  2485. {
  2486. return _HAL_MS((*_OFFSET_TO_WORD_PTR(reo_ent_desc,
  2487. REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_OFFSET)),
  2488. REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_MASK,
  2489. REO_ENTRANCE_RING_6_RXDMA_PUSH_REASON_LSB);
  2490. }
  2491. /**
  2492. * hal_rx_reo_ent_rxdma_error_code_get(): Retrieves RXDMA error code from
  2493. * reo_entrance_ring descriptor
  2494. * @reo_ent_desc: reo_entrance_ring descriptor
  2495. * Return: value of rxdma_error_code
  2496. */
  2497. static inline
  2498. uint8_t hal_rx_reo_ent_rxdma_error_code_get(hal_rxdma_desc_t reo_ent_desc)
  2499. {
  2500. return _HAL_MS((*_OFFSET_TO_WORD_PTR(reo_ent_desc,
  2501. REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_OFFSET)),
  2502. REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_MASK,
  2503. REO_ENTRANCE_RING_6_RXDMA_ERROR_CODE_LSB);
  2504. }
  2505. /**
  2506. * hal_rx_wbm_err_info_get(): Retrieves WBM error code and reason and
  2507. * save it to hal_wbm_err_desc_info structure passed by caller
  2508. * @wbm_desc: wbm ring descriptor
  2509. * @wbm_er_info: hal_wbm_err_desc_info structure, output parameter.
  2510. * Return: void
  2511. */
  2512. static inline void hal_rx_wbm_err_info_get(void *wbm_desc,
  2513. struct hal_wbm_err_desc_info *wbm_er_info,
  2514. hal_soc_handle_t hal_soc_hdl)
  2515. {
  2516. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2517. hal_soc->ops->hal_rx_wbm_err_info_get(wbm_desc, (void *)wbm_er_info);
  2518. }
  2519. /**
  2520. * hal_rx_wbm_err_info_set_in_tlv(): Save the wbm error codes and reason to
  2521. * the reserved bytes of rx_tlv_hdr
  2522. * @buf: start of rx_tlv_hdr
  2523. * @wbm_er_info: hal_wbm_err_desc_info structure
  2524. * Return: void
  2525. */
  2526. static inline void hal_rx_wbm_err_info_set_in_tlv(uint8_t *buf,
  2527. struct hal_wbm_err_desc_info *wbm_er_info)
  2528. {
  2529. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  2530. qdf_mem_copy(pkt_tlvs->rx_padding0, wbm_er_info,
  2531. sizeof(struct hal_wbm_err_desc_info));
  2532. }
  2533. /**
  2534. * hal_rx_wbm_err_info_get_from_tlv(): retrieve wbm error codes and reason from
  2535. * the reserved bytes of rx_tlv_hdr.
  2536. * @buf: start of rx_tlv_hdr
  2537. * @wbm_er_info: hal_wbm_err_desc_info structure, output parameter.
  2538. * Return: void
  2539. */
  2540. static inline void hal_rx_wbm_err_info_get_from_tlv(uint8_t *buf,
  2541. struct hal_wbm_err_desc_info *wbm_er_info)
  2542. {
  2543. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  2544. qdf_mem_copy(wbm_er_info, pkt_tlvs->rx_padding0,
  2545. sizeof(struct hal_wbm_err_desc_info));
  2546. }
  2547. #define HAL_RX_MSDU_START_NSS_GET(_rx_msdu_start) \
  2548. (_HAL_MS((*_OFFSET_TO_WORD_PTR((_rx_msdu_start), \
  2549. RX_MSDU_START_5_NSS_OFFSET)), \
  2550. RX_MSDU_START_5_NSS_MASK, \
  2551. RX_MSDU_START_5_NSS_LSB))
  2552. /**
  2553. * hal_rx_mon_hw_desc_get_mpdu_status: Retrieve MPDU status
  2554. *
  2555. * @ hal_soc: HAL version of the SOC pointer
  2556. * @ hw_desc_addr: Start address of Rx HW TLVs
  2557. * @ rs: Status for monitor mode
  2558. *
  2559. * Return: void
  2560. */
  2561. static inline
  2562. void hal_rx_mon_hw_desc_get_mpdu_status(hal_soc_handle_t hal_soc_hdl,
  2563. void *hw_desc_addr,
  2564. struct mon_rx_status *rs)
  2565. {
  2566. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2567. hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status(hw_desc_addr, rs);
  2568. }
  2569. /*
  2570. * hal_rx_get_tlv(): API to get the tlv
  2571. *
  2572. * @hal_soc: HAL version of the SOC pointer
  2573. * @rx_tlv: TLV data extracted from the rx packet
  2574. * Return: uint8_t
  2575. */
  2576. static inline uint8_t hal_rx_get_tlv(struct hal_soc *hal_soc, void *rx_tlv)
  2577. {
  2578. return hal_soc->ops->hal_rx_get_tlv(rx_tlv);
  2579. }
  2580. /*
  2581. * hal_rx_msdu_start_nss_get(): API to get the NSS
  2582. * Interval from rx_msdu_start
  2583. *
  2584. * @hal_soc: HAL version of the SOC pointer
  2585. * @buf: pointer to the start of RX PKT TLV header
  2586. * Return: uint32_t(nss)
  2587. */
  2588. static inline
  2589. uint32_t hal_rx_msdu_start_nss_get(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2590. {
  2591. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2592. return hal_soc->ops->hal_rx_msdu_start_nss_get(buf);
  2593. }
  2594. /**
  2595. * hal_rx_dump_msdu_start_tlv: dump RX msdu_start TLV in structured
  2596. * human readable format.
  2597. * @ msdu_start: pointer the msdu_start TLV in pkt.
  2598. * @ dbg_level: log level.
  2599. *
  2600. * Return: void
  2601. */
  2602. static inline void hal_rx_dump_msdu_start_tlv(struct hal_soc *hal_soc,
  2603. struct rx_msdu_start *msdu_start,
  2604. uint8_t dbg_level)
  2605. {
  2606. hal_soc->ops->hal_rx_dump_msdu_start_tlv(msdu_start, dbg_level);
  2607. }
  2608. /**
  2609. * hal_rx_mpdu_start_tid_get - Return tid info from the rx mpdu start
  2610. * info details
  2611. *
  2612. * @ buf - Pointer to buffer containing rx pkt tlvs.
  2613. *
  2614. *
  2615. */
  2616. static inline uint32_t hal_rx_mpdu_start_tid_get(hal_soc_handle_t hal_soc_hdl,
  2617. uint8_t *buf)
  2618. {
  2619. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2620. return hal_soc->ops->hal_rx_mpdu_start_tid_get(buf);
  2621. }
  2622. /*
  2623. * hal_rx_msdu_start_reception_type_get(): API to get the reception type
  2624. * Interval from rx_msdu_start
  2625. *
  2626. * @buf: pointer to the start of RX PKT TLV header
  2627. * Return: uint32_t(reception_type)
  2628. */
  2629. static inline
  2630. uint32_t hal_rx_msdu_start_reception_type_get(hal_soc_handle_t hal_soc_hdl,
  2631. uint8_t *buf)
  2632. {
  2633. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2634. return hal_soc->ops->hal_rx_msdu_start_reception_type_get(buf);
  2635. }
  2636. /**
  2637. * hal_rx_dump_pkt_tlvs: API to print all member elements of
  2638. * RX TLVs
  2639. * @ buf: pointer the pkt buffer.
  2640. * @ dbg_level: log level.
  2641. *
  2642. * Return: void
  2643. */
  2644. static inline void hal_rx_dump_pkt_tlvs(hal_soc_handle_t hal_soc_hdl,
  2645. uint8_t *buf, uint8_t dbg_level)
  2646. {
  2647. struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
  2648. struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn;
  2649. struct rx_mpdu_start *mpdu_start =
  2650. &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
  2651. struct rx_msdu_start *msdu_start =
  2652. &pkt_tlvs->msdu_start_tlv.rx_msdu_start;
  2653. struct rx_mpdu_end *mpdu_end = &pkt_tlvs->mpdu_end_tlv.rx_mpdu_end;
  2654. struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
  2655. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2656. hal_rx_dump_rx_attention_tlv(rx_attn, dbg_level);
  2657. hal_rx_dump_mpdu_start_tlv(mpdu_start, dbg_level, hal_soc);
  2658. hal_rx_dump_msdu_start_tlv(hal_soc, msdu_start, dbg_level);
  2659. hal_rx_dump_mpdu_end_tlv(mpdu_end, dbg_level);
  2660. hal_rx_dump_msdu_end_tlv(hal_soc, msdu_end, dbg_level);
  2661. hal_rx_dump_pkt_hdr_tlv(pkt_tlvs, dbg_level);
  2662. }
  2663. /**
  2664. * hal_reo_status_get_header_generic - Process reo desc info
  2665. * @d - Pointer to reo descriptior
  2666. * @b - tlv type info
  2667. * @h - Pointer to hal_reo_status_header where info to be stored
  2668. * @hal- pointer to hal_soc structure
  2669. * Return - none.
  2670. *
  2671. */
  2672. static inline
  2673. void hal_reo_status_get_header(uint32_t *d, int b,
  2674. void *h, struct hal_soc *hal_soc)
  2675. {
  2676. hal_soc->ops->hal_reo_status_get_header(d, b, h);
  2677. }
  2678. /**
  2679. * hal_rx_desc_is_first_msdu() - Check if first msdu
  2680. *
  2681. * @hal_soc_hdl: hal_soc handle
  2682. * @hw_desc_addr: hardware descriptor address
  2683. *
  2684. * Return: 0 - success/ non-zero failure
  2685. */
  2686. static inline
  2687. uint32_t hal_rx_desc_is_first_msdu(hal_soc_handle_t hal_soc_hdl,
  2688. void *hw_desc_addr)
  2689. {
  2690. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2691. return hal_soc->ops->hal_rx_desc_is_first_msdu(hw_desc_addr);
  2692. }
  2693. static inline
  2694. uint32_t
  2695. HAL_RX_DESC_GET_DECAP_FORMAT(void *hw_desc_addr) {
  2696. struct rx_msdu_start *rx_msdu_start;
  2697. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  2698. rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start;
  2699. return HAL_RX_GET(rx_msdu_start, RX_MSDU_START_2, DECAP_FORMAT);
  2700. }
  2701. #ifdef NO_RX_PKT_HDR_TLV
  2702. static inline
  2703. uint8_t *
  2704. HAL_RX_DESC_GET_80211_HDR(void *hw_desc_addr) {
  2705. QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_DEBUG,
  2706. "[%s][%d] decap format not raw", __func__, __LINE__);
  2707. QDF_ASSERT(0);
  2708. return 0;
  2709. }
  2710. #else
  2711. static inline
  2712. uint8_t *
  2713. HAL_RX_DESC_GET_80211_HDR(void *hw_desc_addr) {
  2714. uint8_t *rx_pkt_hdr;
  2715. struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr;
  2716. rx_pkt_hdr = &rx_desc->pkt_hdr_tlv.rx_pkt_hdr[0];
  2717. return rx_pkt_hdr;
  2718. }
  2719. #endif
  2720. static inline
  2721. bool HAL_IS_DECAP_FORMAT_RAW(hal_soc_handle_t hal_soc_hdl,
  2722. uint8_t *rx_tlv_hdr)
  2723. {
  2724. uint8_t decap_format;
  2725. if (hal_rx_desc_is_first_msdu(hal_soc_hdl, rx_tlv_hdr)) {
  2726. decap_format = HAL_RX_DESC_GET_DECAP_FORMAT(rx_tlv_hdr);
  2727. if (decap_format == HAL_HW_RX_DECAP_FORMAT_RAW)
  2728. return true;
  2729. }
  2730. return false;
  2731. }
  2732. /**
  2733. * hal_rx_msdu_fse_metadata_get: API to get FSE metadata
  2734. * from rx_msdu_end TLV
  2735. * @buf: pointer to the start of RX PKT TLV headers
  2736. *
  2737. * Return: fse metadata value from MSDU END TLV
  2738. */
  2739. static inline uint32_t
  2740. hal_rx_msdu_fse_metadata_get(hal_soc_handle_t hal_soc_hdl,
  2741. uint8_t *buf)
  2742. {
  2743. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2744. return hal_soc->ops->hal_rx_msdu_fse_metadata_get(buf);
  2745. }
  2746. /**
  2747. * hal_rx_msdu_flow_idx_get: API to get flow index
  2748. * from rx_msdu_end TLV
  2749. * @buf: pointer to the start of RX PKT TLV headers
  2750. *
  2751. * Return: flow index value from MSDU END TLV
  2752. */
  2753. static inline uint32_t
  2754. hal_rx_msdu_flow_idx_get(hal_soc_handle_t hal_soc_hdl,
  2755. uint8_t *buf)
  2756. {
  2757. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2758. return hal_soc->ops->hal_rx_msdu_flow_idx_get(buf);
  2759. }
  2760. /**
  2761. * hal_rx_msdu_flow_idx_timeout: API to get flow index timeout
  2762. * from rx_msdu_end TLV
  2763. * @buf: pointer to the start of RX PKT TLV headers
  2764. *
  2765. * Return: flow index timeout value from MSDU END TLV
  2766. */
  2767. static inline bool
  2768. hal_rx_msdu_flow_idx_timeout(hal_soc_handle_t hal_soc_hdl,
  2769. uint8_t *buf)
  2770. {
  2771. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2772. return hal_soc->ops->hal_rx_msdu_flow_idx_timeout(buf);
  2773. }
  2774. /**
  2775. * hal_rx_msdu_flow_idx_invalid: API to get flow index invalid
  2776. * from rx_msdu_end TLV
  2777. * @buf: pointer to the start of RX PKT TLV headers
  2778. *
  2779. * Return: flow index invalid value from MSDU END TLV
  2780. */
  2781. static inline bool
  2782. hal_rx_msdu_flow_idx_invalid(hal_soc_handle_t hal_soc_hdl,
  2783. uint8_t *buf)
  2784. {
  2785. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2786. return hal_soc->ops->hal_rx_msdu_flow_idx_invalid(buf);
  2787. }
  2788. /**
  2789. * hal_rx_hw_desc_get_ppduid_get() - Retrieve ppdu id
  2790. * @hal_soc_hdl: hal_soc handle
  2791. * @hw_desc_addr: hardware descriptor address
  2792. *
  2793. * Return: 0 - success/ non-zero failure
  2794. */
  2795. static inline
  2796. uint32_t hal_rx_hw_desc_get_ppduid_get(hal_soc_handle_t hal_soc_hdl,
  2797. void *hw_desc_addr)
  2798. {
  2799. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2800. return hal_soc->ops->hal_rx_hw_desc_get_ppduid_get(hw_desc_addr);
  2801. }
  2802. /**
  2803. * hal_rx_msdu_end_sa_sw_peer_id_get() - get sw peer id
  2804. * @hal_soc_hdl: hal_soc handle
  2805. * @buf: rx tlv address
  2806. *
  2807. * Return: sw peer id
  2808. */
  2809. static inline
  2810. uint32_t hal_rx_msdu_end_sa_sw_peer_id_get(hal_soc_handle_t hal_soc_hdl,
  2811. uint8_t *buf)
  2812. {
  2813. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2814. if ((!hal_soc) || (!hal_soc->ops)) {
  2815. hal_err("hal handle is NULL");
  2816. QDF_BUG(0);
  2817. return QDF_STATUS_E_INVAL;
  2818. }
  2819. if (hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get)
  2820. return hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get(buf);
  2821. return QDF_STATUS_E_INVAL;
  2822. }
  2823. static inline
  2824. void *hal_rx_msdu0_buffer_addr_lsb(hal_soc_handle_t hal_soc_hdl,
  2825. void *link_desc_addr)
  2826. {
  2827. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2828. return hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb(link_desc_addr);
  2829. }
  2830. static inline
  2831. void *hal_rx_msdu_desc_info_ptr_get(hal_soc_handle_t hal_soc_hdl,
  2832. void *msdu_addr)
  2833. {
  2834. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2835. return hal_soc->ops->hal_rx_msdu_desc_info_ptr_get(msdu_addr);
  2836. }
  2837. static inline
  2838. void *hal_ent_mpdu_desc_info(hal_soc_handle_t hal_soc_hdl,
  2839. void *hw_addr)
  2840. {
  2841. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2842. return hal_soc->ops->hal_ent_mpdu_desc_info(hw_addr);
  2843. }
  2844. static inline
  2845. void *hal_dst_mpdu_desc_info(hal_soc_handle_t hal_soc_hdl,
  2846. void *hw_addr)
  2847. {
  2848. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2849. return hal_soc->ops->hal_dst_mpdu_desc_info(hw_addr);
  2850. }
  2851. static inline
  2852. uint8_t hal_rx_get_fc_valid(hal_soc_handle_t hal_soc_hdl,
  2853. uint8_t *buf)
  2854. {
  2855. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2856. return hal_soc->ops->hal_rx_get_fc_valid(buf);
  2857. }
  2858. static inline
  2859. uint8_t hal_rx_get_to_ds_flag(hal_soc_handle_t hal_soc_hdl, uint8_t *buf)
  2860. {
  2861. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2862. return hal_soc->ops->hal_rx_get_to_ds_flag(buf);
  2863. }
  2864. static inline
  2865. uint8_t hal_rx_get_mac_addr2_valid(hal_soc_handle_t hal_soc_hdl,
  2866. uint8_t *buf)
  2867. {
  2868. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2869. return hal_soc->ops->hal_rx_get_mac_addr2_valid(buf);
  2870. }
  2871. static inline
  2872. uint8_t hal_rx_get_filter_category(hal_soc_handle_t hal_soc_hdl,
  2873. uint8_t *buf)
  2874. {
  2875. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2876. return hal_soc->ops->hal_rx_get_filter_category(buf);
  2877. }
  2878. static inline
  2879. uint32_t hal_rx_get_ppdu_id(hal_soc_handle_t hal_soc_hdl,
  2880. uint8_t *buf)
  2881. {
  2882. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2883. return hal_soc->ops->hal_rx_get_ppdu_id(buf);
  2884. }
  2885. /**
  2886. * hal_reo_config(): Set reo config parameters
  2887. * @soc: hal soc handle
  2888. * @reg_val: value to be set
  2889. * @reo_params: reo parameters
  2890. *
  2891. * Return: void
  2892. */
  2893. static inline
  2894. void hal_reo_config(struct hal_soc *hal_soc,
  2895. uint32_t reg_val,
  2896. struct hal_reo_params *reo_params)
  2897. {
  2898. hal_soc->ops->hal_reo_config(hal_soc,
  2899. reg_val,
  2900. reo_params);
  2901. }
  2902. /**
  2903. * hal_rx_msdu_get_flow_params: API to get flow index,
  2904. * flow index invalid and flow index timeout from rx_msdu_end TLV
  2905. * @buf: pointer to the start of RX PKT TLV headers
  2906. * @flow_invalid: pointer to return value of flow_idx_valid
  2907. * @flow_timeout: pointer to return value of flow_idx_timeout
  2908. * @flow_index: pointer to return value of flow_idx
  2909. *
  2910. * Return: none
  2911. */
  2912. static inline void
  2913. hal_rx_msdu_get_flow_params(hal_soc_handle_t hal_soc_hdl,
  2914. uint8_t *buf,
  2915. bool *flow_invalid,
  2916. bool *flow_timeout,
  2917. uint32_t *flow_index)
  2918. {
  2919. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2920. if ((!hal_soc) || (!hal_soc->ops)) {
  2921. hal_err("hal handle is NULL");
  2922. QDF_BUG(0);
  2923. return;
  2924. }
  2925. if (hal_soc->ops->hal_rx_msdu_get_flow_params)
  2926. hal_soc->ops->
  2927. hal_rx_msdu_get_flow_params(buf,
  2928. flow_invalid,
  2929. flow_timeout,
  2930. flow_index);
  2931. }
  2932. static inline
  2933. uint16_t hal_rx_tlv_get_tcp_chksum(hal_soc_handle_t hal_soc_hdl,
  2934. uint8_t *buf)
  2935. {
  2936. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2937. return hal_soc->ops->hal_rx_tlv_get_tcp_chksum(buf);
  2938. }
  2939. static inline
  2940. uint16_t hal_rx_get_rx_sequence(hal_soc_handle_t hal_soc_hdl,
  2941. uint8_t *buf)
  2942. {
  2943. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2944. return hal_soc->ops->hal_rx_get_rx_sequence(buf);
  2945. }
  2946. static inline void
  2947. hal_rx_get_bb_info(hal_soc_handle_t hal_soc_hdl,
  2948. void *rx_tlv,
  2949. void *ppdu_info)
  2950. {
  2951. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2952. if (hal_soc->ops->hal_rx_get_bb_info)
  2953. hal_soc->ops->hal_rx_get_bb_info(rx_tlv, ppdu_info);
  2954. }
  2955. static inline void
  2956. hal_rx_get_rtt_info(hal_soc_handle_t hal_soc_hdl,
  2957. void *rx_tlv,
  2958. void *ppdu_info)
  2959. {
  2960. struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl;
  2961. if (hal_soc->ops->hal_rx_get_rtt_info)
  2962. hal_soc->ops->hal_rx_get_rtt_info(rx_tlv, ppdu_info);
  2963. }
  2964. #endif /* _HAL_RX_H */