Add ini configuration to disable invalid decap type handling
during rx mon tlv processing. This is a temporary change for
debugging purpose and will be removed once HW issue is resolved.
Change-Id: I75eb53170833224ddd144baf1b1d8034f988dd3c
CRs-Fixed: 3308998
Add ini param "dp_disable_rx_buf_low_threshold" to disable
low threshold interrupts on regular rx refill ring. Default
it is enabled.
Change-Id: Ie471a4dc6862cbfe8b1eafe7c7d2ce2e0a7fcb7a
CRs-Fixed: 3313885
Update the prealloc size for RXDMA_BUF and REO_DST
rings using the ini values which have been configured.
Change-Id: Id47fbca3a79b37bba902d1b5bd0bf8c6073648cc
CRs-Fixed: 3283986
add debug prints and a custom timer for how long to wait to receive next
bk pressure event message.
Change-Id: I5a736b0f134cd179990de536da02967db3e39774
CRs-Fixed: 3273427
Add framework to use different RX hash values and ring masks
for ML and non-ML peers
Change-Id: I098cb50b8873eb137ce096011d01a5c21aaf854f
CRs-Fixed: 3269916
Currently in monitor mode for KIWI, interrupt for RXDMA2HOST is
enabled to process both monitor status srng and montior destination
srng, but low threshold interrupt for monitor status srng is also
enabled. so when available RX buffer in monitor status srng is less
then low threshold, it is possible that two kind of interrupt from
RXDMA2HOST ring and monitor status ring will call
dp_rx_mon_status_process_tlv() in different context and access to
mon_pdev->rx_status_q at the same time, this will lead to skb
double free issue.
solution:
(1) disable RXDMA2HOST srng interrupt in monitor mode.
(2) enable monitor status srng batch count interrupt for monitor
processing.
Change-Id: I1df8830cb7cc55468e5df5e49045c3d96f7c29a8
CRs-Fixed: 3245393
With KIWI_V2, wbm_ring_num for WBM2SW5 and WBM2SW6 have been changed
to 5 and 6. Hence properly update them in g_tcl_wbm_map_array. At the
same time, tx_ring_mask_msi and tx_ring_near_full_irq_mask are also
updated.
With IPA_OFFLOAD enabled soc->tcl_data_ring[0|1|2] is used by HOST
and the other two rings are allocated to IPA usage.
Change-Id: I4c13d0787e46be667c3a5a0ae624df8c2b2b354e
CRs-Fixed: 3229375
UMAC HW reset feature will be using the last interrupt context in each
DP interrupt combination i.e., on a system with more than 8 MSIs for DP,
UMAC HW reset will be assigned a dedicated interrupt context.
Add the necessary support for the same.
CRs-Fixed: 3163900
Change-Id: I26abd01e4261661ed95e1aa3cb2a774e78b50d9f
Increase the number of DP interrupts to 16. The interrupt assignment
table is updated to add new values for different MSI interrupts
available. 9, 10 and 11 MSIs configuration will take the same
configuration as that of 8 MSI. 13, 14 and 15 MSIs configuration
will take the same configuration as that of 12 MSI. New MSI assignment
configuration is introduced for 12 and 16 MSIs.
Change-Id: I82af75b21c793a62fc8f0bd5515e1160b601c0c2
CRs-Fixed: 3209397
Enable bits in WMI_INIT command to let the FW know about host's
capability to support notify frame feature. If the feature is enabled,
host can mark certain TX frames as "notify frames" for hardware and they
need not be sent to FW. FW depends on this capability exchange to decide
whether to install HW rules for frames to be sent to HW.
Change-Id: I7158e79ae0fbdc73a2f4096ae1577337e8291246
CRs-Fixed: 3209399
NAPI scale factor should be configured based on the board
type. for example Hawkeye could have a different scale factor
compared to Alder.
CRs-Fixed: 3212330
Change-Id: Ie0bad6aade9ca9379997aa974154f9fb903ab93e
Add ini support to configure TC ingress filter priority
value which would be used for TC based dynamic GRO.
Change-Id: I1742f4539353939e3a40ff4096b3f833f2029b12
CRs-Fixed: 3206817
For SW2HW ring, if time threshold is non-zero and low threshold
is 0, then if ring is empty, HW will keep generating low threshold
interrupt always which then LPL failed.
Configure SW2HW ring timer threshold 0 to disable low threshold
interrupt, also set batch_count threshold 0 as host not need the
interrupt if HW consumed entries.
Change-Id: I6c8ea516e66abd706fecd97649f3a19702453b85
CRs-Fixed: 3149341
Ageout flush does not happen for WBM2SW4 if there
is only one TX completion pending in FIFO and all the
other WBM release rings are not active. This is due to
an issue in HW and this prevents suspend to happen due
to pending tx completions.
Fix is to avoid using WBM2SW4 release ring and instead
reuse WBM2SW0.
Change-Id: I250d8c9d460895449939212ebdb7abd62edb0234
CRs-Fixed: 3124733
Enable the 4th Tx. completion ring to save CPU load
Initialization and interrupt handling for 4th completion ring
is done here.
Change-Id: I2db27218a3c3e14d719d012f03454a6a7aa647fe
User can specify a limit and frames are dropped when the memory
used by packets in the queues goes beyond the limit. This is a
SoC level param.
Change-Id: Id2bd9caaa11d9ea9f9e04c635ff629190bb62916
Currently, we are assigning 9 MSI Vector to DP.
But in some target available MSI Vector are less
because of which they are unable to assign 9 MSI
Vector to DP.
So, to fix the issue reduces MSI requirement for
DP from 9 to 7 and mux DP interrupts.
Change-Id: I48da2d0e8921db3298903a398f981e5b45a60987
CRs-Fixed: 3111170
For WCN7850, the first mac (i.e.. MAC0) is capable of
2G/5G and 6G data transfer. Hence initialize and use
only on RXDMA monitor status ring.
Change-Id: Idb6e23a887a9ed32a52dd54765e5ed3c6a12df06
CRs-Fixed: 3094138
Enable the interrupt based processing in monitor mode
for WCN7850, by enabling MSI interrupts for rxdma
monitor destination ring.
Change-Id: Ia3c4456d28ed58c8ef49a7aa8e711076fbdf9415
CRs-Fixed: 3094129
WCN7850 has only one RXDMA DST ring, as opposed to other
lithium family chipsets, which had 2 RXDMA DST ring.
Refactor the code to pick the number of rxdma destination
rings from CFG context.
Change-Id: I20d475c02690043e969bc7a78605809b8c6814ae
CRs-Fixed: 3084440
Offsets used by host for HTT stats are not aligned as per the
structure declaration given in file htt.h .
Make change to use the correct offsets to get the correct stats.
Also make change for byte count computation.
Also make cleanup changes for FR65817.
Change-Id: I8bc6164cc4994c49536d7277779f25b258be1592
CRs-Fixed: 3082742
Add configuration at SOC level for hw vdev stats in BE architecture.
Following config parameters are added:
vdev_stats_hw_offload: option to enable/disable hw vdev stats
hw_vdev_stats_timer: timer duration for hw vdev stats
Change-Id: I8cbd2b6a7378d8a9e7de920a3a6fdff0cf7785fe
CRs-Fixed: 3067843
Rx patch changes for multichip MLO
1. Create ini for rx ring mask for each chip
2. Configure hash based routing for each chip based
on lmac_peer_id_msb
3. Peer setup changes to configure lmac_peer_id_msb
to enable hash based routing
4. Rx Replenish changes to provide buffers back to owner
SOC of reo ring
Change-Id: Ibbe6e81f9e62d88d9bb289a082dd14b4362252c4
This force use BA64 ini config is no longer needed, because another
gRxAggregationSize can do the same settings and more flexible.
Change is used to remove this config.
Change-Id: Ie780489849f8b701481a628a9bca2b4112460bd8
CRs-Fixed: 3076982
Dynamic GRO feature is enabled by default and aimed for specific
customers. Add an ini control to allow other customers to config
this feature enable/disable.
Change-Id: I7f505599327ac131b3cdac9b4d9e038861b1aeb6
CRs-Fixed: 3074689
ipa_enabled cfg parameter is updated in DP post soc_attach
and soc_init and the default value of ipa_enabled in soc
cfg context is 0. ipa_enabled cfg is used in soc_attach
and soc_init for tx and tx completion ring configurations
and could potentially cause issues when ipa is enabled.
Fix is to update ipa_enabled config as part of dp soc
ipa_config_attach.
Change-Id: Ia797d8feed8aff619b0f7f63ba7ec5823c82458c
CRs-Fixed: 3075076
Repurpose the IPA tx and tx completions rings for
normal use when IPA is disabled either via config
flag or ini.
Change-Id: Ia4b6a89c73d888a217bdef40e3c05435c3bb1bb2
CRs-Fixed: 3059730
This change includes below
1) Changes needed to increase Tx rings to 4
2) Use WBM2SW4 ring for rx error in QCN9224
3) memset srng at alloc to avoid populating RBM_id
in per packet path and enable implicit RBM
Change-Id: Icbd5ac2378273b8f3c6adc41c611e29551fff22f
Currently the IRQ mask for tx completion near full
interrupt is not in sync with the tx completion rings
which are enabled for WCN7850.
Fix the mask for tx completion near full interrupt.
Change-Id: I1432191b260094060873406d48e04fde5b7bc35e
CRs-Fixed: 3052650
Currently, rx packet capture events processing happens even
when feature is disabled by ini. This incurs per packet overhead
in rx path.
The fix is to move all the processing from rx path to packet capture mode
component. Send only wdi event from rx path, when feature is enabled by
ini.
Change-Id: I647256b85117cd3373950c78a5a0ae7d6710e4e2
CRs-Fixed: 2969123
Add support configure ipa tx ring and tx completion ring for
2.4G and/or 5G separately.
Change-Id: Iafb8fa589ff0cce15609a3dfa2209364291d7cef
CRs-Fixed: 2996604
