qcacmn: Allocate dedicated tx desc pool for ppeds

Allocate dedicated tx desc pool for PPE2TCL ring
tx completion handling.

Change-Id: I3d3220b9b38b6f24d98ce73cb5273ae4dc6e7f37
CRs-Fixed: 3300660

dp/wifi3.0/be/dp_be.c

@@ -503,6 +503,16 @@ static QDF_STATUS dp_soc_ppe_detach_be(struct dp_soc *soc)
 	return QDF_STATUS_SUCCESS;
 }
 #else
+static QDF_STATUS dp_ppeds_init_soc_be(struct dp_soc *soc)
+{
+	return QDF_STATUS_SUCCESS;
+}
+
+static QDF_STATUS dp_ppeds_deinit_soc_be(struct dp_soc *soc)
+{
+	return QDF_STATUS_SUCCESS;
+}
+
 static inline QDF_STATUS dp_soc_ppe_attach_be(struct dp_soc *soc)
 {
 	return QDF_STATUS_SUCCESS;
@@ -624,7 +634,8 @@ static QDF_STATUS dp_soc_attach_be(struct dp_soc *soc,
 	int i = 0;
 
 	max_tx_rx_desc_num = WLAN_CFG_NUM_TX_DESC_MAX * MAX_TXDESC_POOLS +
-		WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX * MAX_RXDESC_POOLS;
+		WLAN_CFG_RX_SW_DESC_NUM_SIZE_MAX * MAX_RXDESC_POOLS +
+		WLAN_CFG_NUM_PPEDS_TX_DESC_MAX * MAX_PPE_TXDESC_POOLS;
 	/* estimate how many SPT DDR pages needed */
 	num_spt_pages = max_tx_rx_desc_num / DP_CC_SPT_PAGE_MAX_ENTRIES;
 	num_spt_pages = num_spt_pages <= DP_CC_PPT_MAX_ENTRIES ?
@@ -696,6 +707,8 @@ static QDF_STATUS dp_soc_deinit_be(struct dp_soc *soc)
 		dp_hw_cookie_conversion_deinit(be_soc,
 					       &be_soc->rx_cc_ctx[i]);
 
+	dp_ppeds_deinit_soc_be(soc);
+
 	return QDF_STATUS_SUCCESS;
 }
 
@@ -705,6 +718,8 @@ static QDF_STATUS dp_soc_init_be(struct dp_soc *soc)
 	struct dp_soc_be *be_soc = dp_get_be_soc_from_dp_soc(soc);
 	int i = 0;
 
+	dp_ppeds_init_soc_be(soc);
+
 	for (i = 0; i < MAX_TXDESC_POOLS; i++) {
 		qdf_status =
 			dp_hw_cookie_conversion_init(be_soc,

dp/wifi3.0/be/dp_be.h

@@ -97,8 +97,27 @@ enum CMEM_MEM_CLIENTS {
 #define WBM2SW_REL_ERR_RING_NUM 5
 #endif
 
+#ifdef WLAN_SUPPORT_PPEDS
+/* The MAX PPE PRI2TID */
+#define DP_TX_INT_PRI2TID_MAX 15
+
+#define DP_TX_PPEDS_POOL_ID 0
+
+/* size of CMEM needed for a ppeds tx desc pool */
+#define DP_TX_PPEDS_DESC_POOL_CMEM_SIZE \
+	((WLAN_CFG_NUM_PPEDS_TX_DESC_MAX / DP_CC_SPT_PAGE_MAX_ENTRIES) * \
+	 DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)
+
+/* Offset of ppeds tx descripotor pool */
+#define DP_TX_PPEDS_DESC_CMEM_OFFSET 0
+#else
+#define DP_TX_PPEDS_DESC_CMEM_OFFSET 0
+#define DP_TX_PPEDS_DESC_POOL_CMEM_SIZE 0
+#endif
+
 /* tx descriptor are programmed at start of CMEM region*/
-#define DP_TX_DESC_CMEM_OFFSET	0
+#define DP_TX_DESC_CMEM_OFFSET \
+	(DP_TX_PPEDS_DESC_CMEM_OFFSET + DP_TX_PPEDS_DESC_POOL_CMEM_SIZE)
 
 /* size of CMEM needed for a tx desc pool*/
 #define DP_TX_DESC_POOL_CMEM_SIZE \
@@ -206,6 +225,26 @@ struct dp_ppe_vp_profile {
 	uint8_t to_fw;
 	uint8_t use_ppe_int_pri;
 };
+
+/**
+ * struct dp_ppe_tx_desc_pool_s - PPEDS Tx Descriptor Pool
+ * @elem_size: Size of each descriptor
+ * @num_allocated: Number of used descriptors
+ * @freelist: Chain of free descriptors
+ * @desc_pages: multiple page allocation information for actual descriptors
+ * @elem_count: Number of descriptors in the pool
+ * @num_free: Number of free descriptors
+ * @lock- Lock for descriptor allocation/free from/to the pool
+ */
+struct dp_ppe_tx_desc_pool_s {
+	uint16_t elem_size;
+	uint32_t num_allocated;
+	struct dp_tx_desc_s *freelist;
+	struct qdf_mem_multi_page_t desc_pages;
+	uint16_t elem_count;
+	uint32_t num_free;
+	qdf_spinlock_t lock;
+};
 #endif
 
 /**
@@ -232,6 +271,8 @@ struct dp_ppe_vp_profile {
  * @ppe_vp_tbl_lock: PPE VP table lock
  * @num_ppe_vp_entries : Number of PPE VP entries
  * @ipa_bank_id: TCL bank id used by IPA
+ * @ppeds_tx_cc_ctx: Cookie conversion context for ppeds tx desc pool
+ * @ppeds_tx_desc: PPEDS tx desc pool
  * @ppeds_handle: PPEDS soc instance handle
  */
 struct dp_soc_be {
@@ -252,6 +293,8 @@ struct dp_soc_be {
 	struct dp_srng ppe2tcl_ring;
 	struct dp_srng ppe_release_ring;
 	struct dp_ppe_vp_tbl_entry *ppe_vp_tbl;
+	struct dp_hw_cookie_conversion_t ppeds_tx_cc_ctx;
+	struct dp_ppe_tx_desc_pool_s ppeds_tx_desc;
 	void *ppeds_handle;
 	qdf_mutex_t ppe_vp_tbl_lock;
 	uint8_t num_ppe_vp_entries;
@@ -749,6 +792,8 @@ uint32_t dp_desc_pool_get_cmem_base(uint8_t chip_id, uint8_t desc_pool_id,
 		return (DP_RX_DESC_CMEM_OFFSET +
 			((chip_id * MAX_RXDESC_POOLS) + desc_pool_id) *
 			DP_RX_DESC_POOL_CMEM_SIZE);
+	case DP_TX_PPEDS_DESC_TYPE:
+		return DP_TX_PPEDS_DESC_CMEM_OFFSET;
 	default:
 			QDF_BUG(0);
 	}

dp/wifi3.0/dp_tx.c

@@ -5209,7 +5209,7 @@ dp_tx_comp_process_desc_list(struct dp_soc *soc,
 							      desc->tx_status,
 							      false);
 			qdf_nbuf_free(desc->nbuf);
-			dp_tx_desc_free(soc, desc, desc->pool_id);
+			dp_ppeds_tx_desc_free(soc, desc);
 			desc = next;
 			continue;
 		}

dp/wifi3.0/dp_tx.h

@@ -286,6 +286,14 @@ qdf_nbuf_t dp_tx_exc_drop(struct cdp_soc_t *soc_hdl, uint8_t vdev_id,
 			  qdf_nbuf_t nbuf,
 			  struct cdp_tx_exception_metadata *tx_exc_metadata);
 #endif
+#ifdef WLAN_SUPPORT_PPEDS
+void dp_ppeds_tx_desc_free(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc);
+#else
+static inline
+void dp_ppeds_tx_desc_free(struct dp_soc *soc, struct dp_tx_desc_s *tx_desc)
+{
+}
+#endif
 #ifndef QCA_HOST_MODE_WIFI_DISABLED
 /**
  * dp_tso_attach() - TSO Attach handler

dp/wifi3.0/dp_types.h

@@ -82,6 +82,7 @@
 #endif
 
 #define MAX_RXDESC_POOLS 4
+#define MAX_PPE_TXDESC_POOLS 1
 
 /* Max no. of VDEV per PSOC */
 #ifdef WLAN_PSOC_MAX_VDEVS

wlan_cfg/cfg_dp.h

@@ -1578,6 +1578,17 @@
 #endif
 
 #ifdef WLAN_SUPPORT_PPEDS
+#define WLAN_CFG_NUM_PPEDS_TX_DESC_MIN 16
+#define WLAN_CFG_NUM_PPEDS_TX_DESC_MAX 0x8000
+#define WLAN_CFG_NUM_PPEDS_TX_DESC 0x8000
+
+#define CFG_DP_PPEDS_TX_DESC \
+		CFG_INI_UINT("dp_ppeds_tx_desc", \
+		WLAN_CFG_NUM_PPEDS_TX_DESC_MIN, \
+		WLAN_CFG_NUM_PPEDS_TX_DESC_MAX, \
+		WLAN_CFG_NUM_PPEDS_TX_DESC, \
+		CFG_VALUE_OR_DEFAULT, "DP PPEDS Tx Descriptors")
+
 #define CFG_DP_PPE_ENABLE \
 	CFG_INI_BOOL("ppe_enable", false, \
 	"DP ppe enable flag")
@@ -1604,12 +1615,14 @@
 		CFG_VALUE_OR_DEFAULT, "DP PPE Release Ring")
 
 #define CFG_DP_PPE_CONFIG \
+		CFG(CFG_DP_PPEDS_TX_DESC) \
 		CFG(CFG_DP_PPE_ENABLE) \
 		CFG(CFG_DP_REO2PPE_RING) \
 		CFG(CFG_DP_PPE2TCL_RING) \
 		CFG(CFG_DP_PPE_RELEASE_RING)
 #else
 #define CFG_DP_PPE_CONFIG
+#define WLAN_CFG_NUM_PPEDS_TX_DESC_MAX 0
 #endif
 
 #if defined(WLAN_FEATURE_11BE_MLO) && defined(WLAN_MLO_MULTI_CHIP)

wlan_cfg/wlan_cfg.c

@@ -2502,6 +2502,7 @@ wlan_soc_ppe_cfg_attach(struct cdp_ctrl_objmgr_psoc *psoc,
 	wlan_cfg_ctx->ppe2tcl_ring = cfg_get(psoc, CFG_DP_PPE2TCL_RING);
 	wlan_cfg_ctx->ppe_release_ring = cfg_get(psoc,
 						 CFG_DP_PPE_RELEASE_RING);
+	wlan_cfg_ctx->ppe_num_tx_desc = cfg_get(psoc, CFG_DP_PPEDS_TX_DESC);
 }
 #else
 static inline void
@@ -3920,6 +3921,12 @@ wlan_cfg_get_dp_soc_ppe_release_ring_size(struct wlan_cfg_dp_soc_ctxt *cfg)
 {
 	return cfg->ppe_release_ring;
 }
+
+int
+wlan_cfg_get_dp_soc_ppe_num_tx_desc(struct wlan_cfg_dp_soc_ctxt *cfg)
+{
+	return cfg->ppe_num_tx_desc;
+}
 #endif
 
 void

wlan_cfg/wlan_cfg.h

@@ -414,6 +414,7 @@ struct wlan_cfg_dp_soc_ctxt {
 	int reo2ppe_ring;
 	int ppe2tcl_ring;
 	int ppe_release_ring;
+	int ppe_num_tx_desc;
 #endif
 #ifdef WLAN_FEATURE_PKT_CAPTURE_V2
 	uint32_t pkt_capture_mode;
@@ -1952,6 +1953,15 @@ wlan_cfg_get_dp_soc_ppe2tcl_ring_size(struct wlan_cfg_dp_soc_ctxt *cfg);
  */
 int
 wlan_cfg_get_dp_soc_ppe_release_ring_size(struct wlan_cfg_dp_soc_ctxt *cfg);
+
+/*
+ * wlan_cfg_get_dp_soc_ppe_num_tx_desc() - Number of ppeds tx Descriptors
+ * @wlan_cfg_ctx - Configuration Handle
+ *
+ * Return: num_tx_desc
+ */
+int
+wlan_cfg_get_dp_soc_ppe_num_tx_desc(struct wlan_cfg_dp_soc_ctxt *cfg);
 #else
 static inline bool
 wlan_cfg_get_dp_soc_is_ppe_enabled(struct wlan_cfg_dp_soc_ctxt *cfg)
@@ -1976,6 +1986,12 @@ wlan_cfg_get_dp_soc_ppe_release_ring_size(struct wlan_cfg_dp_soc_ctxt *cfg)
 {
 	return 0;
 }
+
+static inline int
+wlan_cfg_get_dp_soc_ppe_num_tx_desc(struct wlan_cfg_dp_soc_ctxt *cfg)
+{
+	return 0;
+}
 #endif
 
 /**