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@@ -97,8 +97,27 @@ enum CMEM_MEM_CLIENTS {
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#define WBM2SW_REL_ERR_RING_NUM 5
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#endif
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+#ifdef WLAN_SUPPORT_PPEDS
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+/* The MAX PPE PRI2TID */
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+#define DP_TX_INT_PRI2TID_MAX 15
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+
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+#define DP_TX_PPEDS_POOL_ID 0
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+
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+/* size of CMEM needed for a ppeds tx desc pool */
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+#define DP_TX_PPEDS_DESC_POOL_CMEM_SIZE \
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+ ((WLAN_CFG_NUM_PPEDS_TX_DESC_MAX / DP_CC_SPT_PAGE_MAX_ENTRIES) * \
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+ DP_CC_PPT_ENTRY_SIZE_4K_ALIGNED)
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+
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+/* Offset of ppeds tx descripotor pool */
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+#define DP_TX_PPEDS_DESC_CMEM_OFFSET 0
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+#else
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+#define DP_TX_PPEDS_DESC_CMEM_OFFSET 0
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+#define DP_TX_PPEDS_DESC_POOL_CMEM_SIZE 0
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+#endif
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+
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/* tx descriptor are programmed at start of CMEM region*/
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-#define DP_TX_DESC_CMEM_OFFSET 0
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+#define DP_TX_DESC_CMEM_OFFSET \
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+ (DP_TX_PPEDS_DESC_CMEM_OFFSET + DP_TX_PPEDS_DESC_POOL_CMEM_SIZE)
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/* size of CMEM needed for a tx desc pool*/
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#define DP_TX_DESC_POOL_CMEM_SIZE \
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@@ -206,6 +225,26 @@ struct dp_ppe_vp_profile {
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uint8_t to_fw;
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uint8_t use_ppe_int_pri;
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};
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+
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+/**
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+ * struct dp_ppe_tx_desc_pool_s - PPEDS Tx Descriptor Pool
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+ * @elem_size: Size of each descriptor
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+ * @num_allocated: Number of used descriptors
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+ * @freelist: Chain of free descriptors
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+ * @desc_pages: multiple page allocation information for actual descriptors
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+ * @elem_count: Number of descriptors in the pool
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+ * @num_free: Number of free descriptors
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+ * @lock- Lock for descriptor allocation/free from/to the pool
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+ */
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+struct dp_ppe_tx_desc_pool_s {
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+ uint16_t elem_size;
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+ uint32_t num_allocated;
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+ struct dp_tx_desc_s *freelist;
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+ struct qdf_mem_multi_page_t desc_pages;
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+ uint16_t elem_count;
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+ uint32_t num_free;
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+ qdf_spinlock_t lock;
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+};
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#endif
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/**
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@@ -232,6 +271,8 @@ struct dp_ppe_vp_profile {
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* @ppe_vp_tbl_lock: PPE VP table lock
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* @num_ppe_vp_entries : Number of PPE VP entries
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* @ipa_bank_id: TCL bank id used by IPA
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+ * @ppeds_tx_cc_ctx: Cookie conversion context for ppeds tx desc pool
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+ * @ppeds_tx_desc: PPEDS tx desc pool
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* @ppeds_handle: PPEDS soc instance handle
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*/
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struct dp_soc_be {
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@@ -252,6 +293,8 @@ struct dp_soc_be {
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struct dp_srng ppe2tcl_ring;
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struct dp_srng ppe_release_ring;
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struct dp_ppe_vp_tbl_entry *ppe_vp_tbl;
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+ struct dp_hw_cookie_conversion_t ppeds_tx_cc_ctx;
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+ struct dp_ppe_tx_desc_pool_s ppeds_tx_desc;
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void *ppeds_handle;
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qdf_mutex_t ppe_vp_tbl_lock;
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uint8_t num_ppe_vp_entries;
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@@ -749,6 +792,8 @@ uint32_t dp_desc_pool_get_cmem_base(uint8_t chip_id, uint8_t desc_pool_id,
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return (DP_RX_DESC_CMEM_OFFSET +
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((chip_id * MAX_RXDESC_POOLS) + desc_pool_id) *
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DP_RX_DESC_POOL_CMEM_SIZE);
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+ case DP_TX_PPEDS_DESC_TYPE:
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+ return DP_TX_PPEDS_DESC_CMEM_OFFSET;
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default:
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QDF_BUG(0);
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}
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