As per current design misr enable sequence is happening at
atomic check level. At this state, misr configuration may reset
if clocks are enabled through atomic commit sequence. This change
moves misr enable/disable sequence from debugfs context to
encoder kickoff to avoid misr register reset with idle pc.
Change-Id: Ia4faa200f96b76ba8c7ef3f45a26108e34b5e687
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
SDE encoder modeset add and remove the vblank refcount
based on userspace vblank refcount request. This logic
can have race condition with vblank update from
crtc event thread. It is already avoided with
Ibb810ec90e8 ("disp: msm: sde: manage vblank
refcount concurrency").
Change-Id: I1749bff2e2574500db03a405781eab7496f307b2
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
In current SDE driver when misr is enabled, for each commit in
encoder kickoff stage misr is configured for both lm and interface
misr blks. This can clear misr data before client could collect misr.
This change avoids misr data clear and configures misr based on
user input.
Change-Id: I85fc19c78afc6d01346219250c82f2ada824eb0d
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
Commit d46cae019e ("disp: msm: sde: trigger pm_qos vote
with irq enable") moves the pm_qos vote with irq
enable/disable state. Such irq enable/disable call may be
triggered from atomic context and lead to scheduling issues
due to mutex_lock usage in pm_qos APIs. This change moves
the vote with encoder idle pc to allow lock usage with sleep.
Change-Id: I2d22566fbfb5399c5d2d2a4efe882a1928cfbbf8
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Add trace logs in display early wakeup function for performance
profiling.
Change-Id: I63392417f03eac60dba1c43cd71fe5032ba59ed3
Signed-off-by: Lei Chen <chenlei@codeaurora.org>
Display clocks and IRQs are disabled during idle state
on command mode for power saving, and will be enabled
when a new frame commits to display driver. But enable
display clocks and IRQs will cause some latency.
So add a new SDE custom IOCTL for user-space to early wake
up display before first frame commits to kernel.
Change-Id: I6ca0188d321c4964f29c46e588b64d06b9634c59
Signed-off-by: Lei Chen <chenlei@codeaurora.org>
Expose an API in encoder to control display irq's
when the VM enters and exits TUI use case.
Change-Id: Ic2386dcebfd8a9dd2ce06f068c6daf066a3e885f
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
This change to address use after free and null checks in
sde driver.
Change-Id: Iade91596748b1b867ae959e61fca0f7072eda8f3
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
For dual panel, if they both used sim TE, the vsync sources
were set to the same watchdog timer. That's wrong, so need to
set different watchdog timer for different panels.
Change-Id: I8a5b4c6bb86b0b640d24fbfe6517e223d313fb68
Signed-off-by: Yuan Zhao <yzhao@codeaurora.org>
Adjust the QSYNC line count calculation to compensate for the
idle time, when no transfers are actively taking place.
Change-Id: If91eab25321eea6e6880f07605c5a9c1b7b7ee05
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
VM switches during TUI usecase are expected to be seamless i.e without
display reset. In SDE language, this translates to respective display
drivers not tearing down the HW pipeline while releasing the HW.
In Primary VM, this taken care by keeping the DRM pipeline alive when
TUI is active.
In Trusted VM, since the client creates and destroys the display per
session, checks are needed to bypass the physical encoder disable(s).
Change-Id: Iac42f02806962405c9364b1ffed85778229977e9
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
A frame trigger with posted start may have two frames
in wait state due to irq disable on that CPU. In such
case, frame_done count can reach till 2. Allowing count
only till 1, can cause the release_fence trigger miss
and a buffer is held by DPU driver.
Change-Id: I42c10b064ebcaff136591975f3010c11f99a0731
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
During transition to cwb, kthread initialisation has to
be done for the corresponding encoder off work so that
the correct worker thread is used for this particular
work. There can be scenarios where a cwb commit is
received after a writeback session and the worker
associated with the off work is still assigned to
old crtc's worker resulting in a mismatch when
this work is queued. Add support to handle such
scenarios.
Change-Id: I6080025e799977827f4d0f4ab7eb93c6644f981e
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
This change addresses out of range and null checks in
sde driver.
Change-Id: I4ee82760ce3ee7053c336e49ec9eaae8b4c31b1e
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
Add support for all 4LM topologies in new DCE encoder framework.
This change also aligns with the new way of checking topology
information.
Change-Id: I5358d60634070bdb26059056db884ad4161c073e
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
Vsync event timer wakeup was designed to reduced the
interrupt latency and trigger retire fence without delay.
This is fixed by avoiding CPU power collapse where MDSS
interrupt is scheduled. This change avoids extra CPU
wakeup.
Change-Id: Iadaf0e2b84fb079bbc64d9201230df54f8dbe8c1
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Add support for all 4LM topologies in new DCE encoder framework.
This change also aligns with the new way of checking topology
information.
Change-Id: I20785c96569fd07cbd8016d244a7e4c929bfa071
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
Display is entering into mode2 since no new frames are queued,
but auto-refresh requires HW to remain active. Make sure to
cancel the timer for entering idle power collapse whenever
there's a kickoff with auto-refresh feature enabled.
Change-Id: I0ac74e514c9893c31506edc3f2d7e069ab9a3ef8
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
This change updates resource topology mapping tables and includes
logic to compare compression types for dsc vs vdc.
Change-Id: I1735edeb07aec8ed0065f84ac0824c58158412f3
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
Setup blendstages is done per LM but FETCH_PIPE_ACTIVE is per CTL.
Overloading mixer blendstage setup with fetch pipe logic can lead
to HW programming errors. Refactor the logic for setting
FETCH_PIPE_ACTIVE by adding a new op that allows caller to provide
a bitmask of all pipes required to be active on this CTL. This new
logic includes support for:
- 4LM use-cases, staging pipes for all LMs within a CRTC
- Demura fetch-pipe without need for tracking via active_cfg (removed)
Also, lower the cyclomatic complexity in setup_blendstages by moving
the logic for obtaining the mixer config settings in to a helper
function.
Change-Id: I2907b359ffad5734be5b06f44919b5ddb1ef3f7c
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
Currently, compression info passed to resource manager is not
valid in atomic check phase. Also in current design allocation
of msm mode info object is from stack which is huge and causing
stack overflow in continuous splash use case. This change fixes
these issues by moving mode info object to heap allocation.
Change-Id: Ifaf39b3ae59c942da5c00b82c73cb97cdaf500d3
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
Lower the cyclomatic complexity for this function by splitting
the work into helpers.
Change-Id: I9e32d4ff13d31360a2baa77e013751ee8f0773fb
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
This change updates plane's dirty flag with QoS
value to ensure QoS gets reprogrammed with new FPS
settings. This is required as QoS values will change
with FPS.
Change-Id: I377b99da2a640d375bd48477f149197b332e7f7b
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Restart the timeline for the idle power collapse delayed work
timer for every resource control kickoff instead of only during
a power state change. This will prevent entering mode2 at
unexpected times during active scanouts.
Change-Id: I001157ff7e6b6246e26d537e30d8617cab9cb463
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
Current computation of line time does not include compression ratio
from either DSC or VDC. This change stores source bpp and target bpp in
sde_crtc during sde encoder mode set to be used while calculating line
time.
Change-Id: Ib1e045dce17fcf006447d4562b402cc3f214ed8c
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
From Lahaina onwards, widebus is enabled for compressed DSI stream.
This change adjusts interface timing parameters to account for widebus.
Change-Id: Ie6b739ed2cdb515064e3a94404b3e0fe07755d7e
Signed-off-by: Rajkumar Subbiah <rsubbia@codeaurora.org>
Current wakeup time is surpassing next vsync and not being used.
This change will use mdp transfer time calculated by dsi to compute
line time in command mode. In video mode, fps will be used to compute
the line time. This line time will be used with current interface
line count to calculate time until the next vsync.
Change-Id: I0b6fc396711ade95ecf95755a907280309af223e
Signed-off-by: Thomas Dedinsky <tdedinsk@codeaurora.org>
This change adds helper to retrieve the kms from
the drm_enc structure and provides additional error
checking which can be avoided in the callers.
Change-Id: Id8ba07a2d48a605dd4ce846e5d61f302e5861b4d
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
