Delete destination scaler dirty bit clearing when crtc
is disabled as well as during duplicate state.
Change-Id: I4b2201c792a6750c060b2d9291d52547d8a81c15
Signed-off-by: Manoj Kumar AVM <manojavm@codeaurora.org>
Signed-off-by: obrody <obrody@codeaurora.org>
Fix a possible uninitialized variable usage in sde
catalog and a null pointer dereference in sde crtc.
Change-Id: I4299ade65fa7cf5bfc3d60d6d7a368d523286626
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Currently, when runtime_pm_suspend occurs DS property is marked
as dirty invariably if the CRTC allocated the blocks or not.
This causes atomic check failure on CRTCs without DS allocation.
Change-Id: I90287e8e283d2e80aa47627d4aa045040d76b472
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
Add plane buffer flag to get the correct aspace during
TUI VM usecase. FB_NON_SEC_DIR_TRANS plane flag is set
by user-mode to indicate S2-only non-secure buffer in
TUI VM. Return the default drm device when SMMU is not
available during get_aspace_device to make the working
seamless with/without SMMU.
Change-Id: I158dc17ba51ff4b2f302d3e7017db8ab3cfe2b84
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
In some cases like suspend and cwb concurrencies,
the number of mixers in the sde_crtc structure
can become zero. Add support to get the number
of mixers from topology in those cases to
avoid incorrect resource allocation request.
Change-Id: Id9b82e805ff50a107ad06514b4e41c0917abdf33
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
Add support for all 4LM topologies in new DCE encoder framework.
This change also aligns with the new way of checking topology
information.
Change-Id: I20785c96569fd07cbd8016d244a7e4c929bfa071
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
Increase the maximum number of mixers per crtc to 4 to
support 4LM use case. This change also increases the number
of data path to 4 to support 4LM in continuous splash handoff.
Change-Id: I4655017dcb405fad69513bebb8fd7f848fc5873d
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
When a 4LM topology is used each plane attached to a CRTC
is tagged with a L/R layout value and an offset value
depending on where destination X coordinate lands on the display.
The layout information is used to determine SSPP to LM
pair mapping and local coordinate space.
This change also handles source-split and Z-order
validation checks for planes staged on different mixer
pairs.
Change-Id: I1b20223388e65fc36a8b379ad9df23a277fcd1a5
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
Setup blendstages is done per LM but FETCH_PIPE_ACTIVE is per CTL.
Overloading mixer blendstage setup with fetch pipe logic can lead
to HW programming errors. Refactor the logic for setting
FETCH_PIPE_ACTIVE by adding a new op that allows caller to provide
a bitmask of all pipes required to be active on this CTL. This new
logic includes support for:
- 4LM use-cases, staging pipes for all LMs within a CRTC
- Demura fetch-pipe without need for tracking via active_cfg (removed)
Also, lower the cyclomatic complexity in setup_blendstages by moving
the logic for obtaining the mixer config settings in to a helper
function.
Change-Id: I2907b359ffad5734be5b06f44919b5ddb1ef3f7c
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
In few targets, ubwc might not be supported. In those
cases, ubwc properties should not be added to crtc.
Change-Id: I57d295fca018239ae3695657963d8162d6a50df5
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Store full or partial static image in system cache (L3 cache)
for video mode primary display. Added additional commit to
crtc commit thread to transition to read cache state.
The change also updates llcc APIs to support generic functionality.
Change-Id: I6b2a45da946d7e0e0b326da9d214be3f01a9420e
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
This reverts commit a4c2827a47.
The change is not needed on 5.4 since BW limits have moved to
user-space per-target based XML file, and there are already other
properties for specifying the various linewidth parameters.
Change-Id: I87d81047678869bba6f8ec98104dec17c7a9ace2
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
This change updates plane's dirty flag with QoS
value to ensure QoS gets reprogrammed with new FPS
settings. This is required as QoS values will change
with FPS.
Change-Id: I377b99da2a640d375bd48477f149197b332e7f7b
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Dim layer clearing/setup requires reading registers in order to update
value, doing this add additional CPU processing when it's not really
needed. Add logic to only do the updates only when needed.
Bug: 142504774
Change-Id: I23bcbe39575de35c387cfb7d2b9dc993525e4f98
Signed-off-by: Adrian Salido <salidoa@google.com>
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
This change calls setup on blend configuration per stage
instead of per plane per crtc mixer. This avoids unnecessary
register programming if two planes are in the same stage.
Change-Id: I7481270edad13a4182352e72d5d2ab8941de0ae5
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Add xlogs to capture the secure state information of
each of the planes during mixer setup.
Change-Id: I5d60fb4287b13b3ba5a78c6b858dd244ebeb18aa
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
When there is a race condition between DMS seamless transition and
drm_wait_vblank_ioctl, the latter gets deregistered for vblank
handle as drm_crtc_vblank_on call in crtc enbale increments vblank
count. This change avoids drm_crtc_vblank_on call during seamless
transition when crtc is already enabled as it is not required.
Change-Id: I0b9327a98cef00405b5b94e24a3fd15205339cfc
Signed-off-by: Raviteja Tamatam <travitej@codeaurora.org>
During stability tests there are cases where smmu faults are
seen due to direct transition from secure display to secure
camera without smmu ATTACHED state. Added atomic check to avoid
such transitions.
Change-Id: I307e342f35c6e7dab82902fa77e3a5c0c082f4e4
Signed-off-by: Raviteja Tamatam <travitej@codeaurora.org>
Active pipe index will be incremented when free entry is found with the
current implementation. All the indexes will not be used and there is need
to have special handling for last index with current implementation.
Change adds a break in the loop and simplifies the handling.
Change-Id: Ic74ad2aef791ba9c81acb19e85f44edf4d59e434
Signed-off-by: Gopikrishnaiah Anandan <agopik@codeaurora.org>
Some of the features in the DPU hardware needs planes to be staged but
it should not be blended in the layer mixer. Change adds support for drm
driver client to set the blend type on the plane and updates driver code
to skip staging the plane.
Change-Id: I1e8c7f6ce5617820ea8b24419e0d4d27b481819b
Signed-off-by: Gopikrishnaiah Anandan <agopik@codeaurora.org>
This change removes the check comparing encoder's crtc to the
crtc passed in. This check was required up until commit 70486d209c
("disp: msm: sde: remove vblank cache logic"). Now that iteration
is only happening over encoders in the encoder mask, there is no
need to check for a matching crtc to ensure it is valid.
Change-Id: I4ee08061e6c8679fe03f42cf2f889704c99526e5
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
If unregister event fails to succeed due to invalid params
or due to inappropriate hardware configuration, The callback function
is not deleted from the irq table. This leads to list corruption
issues in the subsequent calls to event enable and disable.
Change-Id: I549bd15b07b9a3b04c0f0a239bd85748acf7d473
Signed-off-by: Lakshmi Narayana Kalavala <lkalaval@codeaurora.org>
During wb use case, if any of the input buffers are secure,
the output buffer must also be in secure. In order to
successfully check if output buffer is secure context,
kernel needs to access new connector state.
Change-Id: Ia0124418eac35cf6d3301603e39ed45b971e2665
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
Submit a cwb frame event signal to notify the crtc that cwb
is completed. Currently cwb also uses the same frame done
event as primary. When a single cwb commit is completed, because
cwb is on a slower path there is a race condition in which the
subsequent frame done event for primary clears the refcount.
This fix isolates the events and removes this situation.
Change-Id: Ic3e18302eb8a497cbd7a00f271de2ab320576c83
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
List head should be initialized after the irq node is allocated.
Change initializes the list head of the node.
Change-Id: I495751fcf2422bba3f39a0719e2d76738b691dd9
Signed-off-by: Lakshmi Narayana Kalavala <lkalaval@codeaurora.org>
This change adds support to check whether uidle
is supported for given target.
Change-Id: Icd7ef36eeefcd8d1fc3c960dc7c7560469945408
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
Stage property is modified for dimlayer during atomic
set property phase. This avoids any commit failure occurred due
to dimlayer checks during atomic check phase.
Change-Id: I4ff3d83a5aa9d6446fd4955f6c29854acf93bc68
Signed-off-by: Prashant Singh <prasin@codeaurora.org>
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
Add support to expose base layer staging property to HAL.
In those targets where base layer staging is enabled in mixer,
layer with zorder 0 will be staged as base layer.
Change-Id: Id825357c61ac6913bdcb8a184fc501236519d5dd
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
Add support to stage layer with zorder 0 as base
layer and stage borderfill only during null commit.
Change-Id: I54356c1b7834227cc3da00c211e71ac5816ce51a
Signed-off-by: Krishna Manikandan <mkrishn@codeaurora.org>
During validate, kernel should check if input buffer frame
buffer for wb conn is in secure context. If so, the output
buffer must also be secure context, or fail validate before commit.
Change-Id: I38e50f8b2ac71c8532d9d44df08850bf33180c41
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
Reset MDP ctl path and DSI ctl on autorefresh
disable failure. This will enable the hardware
to recover from the hang.
Change-Id: Ia9acc8573c22e0713179ef4f6ef604caacabfadb
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
BW_INDICATION indication must be programed before BWI_THRESHOLD.
Otherwise, it will revert to legacy behaviour and rsc wakeup is
delayed by one vsync causing janks. In current code BW_INDICATION
is done after LM/SSPP programming and plane fence wait. Moved the
perf_crtc_update before this and just after ctl prepare configuration
to avoid chances of BW_INDICATION crossing BWI_THRESHOLD time.
Change-Id: Ie976720910c34aaf140f1ce7daef38ba20bc10f5
Signed-off-by: Raviteja Tamatam <travitej@codeaurora.org>
Move blendstage initialization to the atomic begin path in the
case where mixers are not setup. Additionally, clear all
blendstages during crtc disable to clean up registers.
This will avoid resetting each of the blend stages in every
commit and then writing only to the layer being used.
Change-Id: Idf7cb3e17de37034c2060f2563bc082fceb5cae9
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
DPU configuration should be changed when resolution switch happens at
the layer mixer level for ltm feature. Driver should mark ltm properties
as dirty when resolution switch happens. Change handles dynamic resolution
switch for ltm by marking the properties as dirty.
Change-Id: I5ffc8e74c42da6c2902eb42fd2e3ed1b9f9e3e4c
Signed-off-by: Gopikrishnaiah Anandan <agopik@codeaurora.org>
