In WIN BE chipsets, replace the REO tid
queue programming in FW via WMI with writing to a
Host managed table shared by HW and SW. REO HW will
pick the tid queue address from the table indexed by
peer id and tid number.
Change-Id: I8107ca5116425538329b11ae3519f02b32573bac
In qcn9224, NAWDS Learning repeater mode will receive packets
with reason as HAL_RXDMA_UNAUTHORIZED_WDS.
Change-Id: I6fe8428a5f8e2bac0e1db45b87169db0bd4cc271
Add 2 hal soc ops, hal_msdu_desc_info_set and
hal_mpdu_desc_info_se for berilliyum datapath.
Attach hal_rx_msdu_ext_desc_info_get_ptr_be to its function
pointer.
Get reo queue descriptor address as a 5 byte value as in
beryllium datapath it is being obtained from rx packet tlv.
Change-Id: Ia58597384e1a3d5eec493b865a88bab4f209502d
CRs-Fixed: 3084532
In WBM error processing read peer_id from peer_meta_data
instead of sw_peer_id.
This changes is needed because we need to process Rx packet
on ML peer. But in MLO case sw_peer_id field contains
link_peer_id where as peer_meta_data has ml_peer_id.
Change-Id: I3f469adfdf7efa88cb081e94fa9fe0c54c1fb078
This change includes below
1) Changes needed to increase Tx rings to 4
2) Use WBM2SW4 ring for rx error in QCN9224
3) memset srng at alloc to avoid populating RBM_id
in per packet path and enable implicit RBM
Change-Id: Icbd5ac2378273b8f3c6adc41c611e29551fff22f
The multicast echo check feature is moved to hardware in
Beryllium. Enable this hardware feature and also disable
the MEC handing code for Beryllium in the host.
Change-Id: I86d319963191f3ed77aba16dcccbc659906edd9f
In Beryllium the HW does the ast lookup and match
and sets the intra-bss bit in the msdu_desc_info
structure of reo_destination ring and WBM Rx release ring.
So, change the Beryllium code to make use of this
hardware assistance for intra-bss.
Change-Id: Ic7c89efc741fefe35603082309204fbe3c9a97c7
In WBM error path, add handling for packets received with
rxdma_psh_rsn as rxdma_rx_flush. Also add assert for packets
received with an invalid push reason.
Change-Id: I4e445d52f00bbbdca358225aef488da0e8dccaa7
CRs-Fixed: 2978262
Currently the EAPOL/ARP/DHCP frames arriving as 2K-jump
or out-of-order frmaes are being delivered to the network
stack, without checking for the packet-number sequence.
WCN7850 has hardware support to provide the packet number
of the previous successful re-ordered packet from hardware.
Use this feature to check if the packet-number are in proper
sequence for these EAPOL/ARP/DHCP packets arriving as 2k-jump
or out-of-order packets before submitting it to the network
stack.
Change-Id: I1078452afce4bc00b2509436295e5bd80000feb4
CRs-Fixed: 2965086
When a msdu scattered across multiple nbufs is received
in REO2SW ring and the remaining nbufs are not yet
available in the ring, loop in dp_rx_process is exited
without resetting the invalid bit in the ring desc cookie.
This will result in an incorrect assertion failure when
the same entry is processed the next time.
Fix is to reset the invalid bit in ring desc cookie
when the loop is exited in the above msdu scattered
scenario.
Change-Id: Ie5cfa1fb8ea1db4b7a0a4837545ecbfdfbb8719a
CRs-Fixed: 2916296
Use macros like dp_cdp_debug, dp_cdp_err, dp_cdp_info to
print logs for QDF_MODULE_ID_CDP
Change-Id: I550eefa82c3417b8bf83378d4a9c6f382098fea6
CRs-Fixed: 2855937
Currently the FW configures the mac with appropriate
offsets for rx pkt tlvs using the structure defined in
te FW and the host does not send the ring selction config
HTT message. This can create a problem when FW stops subscribing
to tlvs or changes its rx pkt tlvs offset.
Fix this by configuring the rx pkt tlv offsets via HTT
ring selection config message.
Change-Id: I1a2865f91b34dd7bda1af8651d7831097dac0bee
CRs-Fixed: 2860504
Due to recent FW changes not filtering out BAR frames, redirect these
frames to REO exception ring and handle as normal data packets.
Change-Id: I4540929fddab14de57a23f6364fc916a70057cbe
CRs-Fixed: 2795499
Get reo destination indication from REO2SW ring descriptor,
store it to qdf_nbuf_cb of skb.
Change-Id: I5a4c504b2550229a77a435b1f5ddb78c4abe51aa
CRs-Fixed: 2809080
If frames from the same FISA flow goes into different REO2SW rings, it
will result in an unexpected FISA behavior. This can happen if the
frames have been reinjected from FW offload module since FW will select
REO2SW1 ring. If the same flow frames hash to other REO2SW rings, then
the same flow UDP frames will do to different rings.
Reo_destination_indication of 6 indicates if the frame has been
reinjected from FW. If so, then continue to deliver the packet without
FISA.
Change-Id: I14a17a10d04909adfb30557d58beb1610e59bf70
CRs-Fixed: 2790292
Reserve 128 bytes headroom for monitor status buffer
to accomadate feature specific radiotap header or any other info
in the headroom.
CRs-Fixed: 2775118
Change-Id: I2b1aba26e565b58c48a2e24ad17965aacd6b4526
MSDU count is not reliable in all cases.Hence it is better
to check whether next_link_desc is valid or not and then
free the MSDUs in the next descriptor and subsequently
release both the current and next link descriptor back to HW.
Change-Id: Ie5ea3be547f9aed6673293221f6b47661cd92cce
Memory optimization of monitor status ring by allocating buffers during
replenish using alloc_skb (linux API).
It creates buffer of required size rather than 4k size(dev_alloc_skb)
Change-Id: I3ae5e403de28c4570f8ac3b50d3ca878a9e4b2f9
CRs-Fixed: 2733931
In monitor mode, radiotap header contains VHT/HE information in management
and control frames after association of STA to AP.For this,reset of
ppdu_info is required before processing of ppdu in order to avoid reuse
of ppdu_info.
Change-Id: Ia36ec2664f79d645ff76db016f986dfb92ec8bbd
CRs-Fixed: 2734804
On returning the msdu link descriptor to HW via WBM
release ring, the rx exception ring contents are not
zeroed. This could result in host reading stale ring
descriptor content in the scenario when HP is updated
even before the latest values are reflected in the ring
descriptor.
Fix is to set invalid bit in cookie for exception ring
descriptor and add cookie sanity check.
Change-Id: I01a294c92b260ebe8e584ef20e9550b1febec913
CRs-Fixed: 2730759
Currently all the rx ring descriptor contents are left
intact even after these entries are processed. This can,
at times, lead to stale entries being processed, if the
head pointer of any ring is updated before the updated
contents of the ring descriptor gets reflected in the memory.
This can lead to scenarios where the host driver reads a
stale value of sw_cookie, and free/unmap a currently in-use
buffer, thereby leading to the hardware accessing unmapped
memory region.
The sw_cookie is the integral part of al the rx ring
processing. Hence we always mark the sw_cookie as invalid
after dequeuing an entry from the REO2SW ring. Every time
we check for the validity of the sw_cookie before we try to
process an entry from REO2SW ring. if the invalid bit in the
sw_cookie is set, we just skip this entry and move on to the
next entry in the ring.
Change-Id: I0e78fa662b8ba33e64687a4dee4d1a5875ddb4bf
CRs-Fixed: 2730718
Remove uncessary msdu count check against msdu count in
mpdu desc info while processing REO Rx err pkts.
As per h/w team msdu count can be obtained from msdu link
desc instead of mpdu desc info.
SOC level Rx err stat rx.err.msdu_count_mismatch is
incremented to log this condition.
Change-Id: I4f7d2df7335778f2f2d28e542da17fc7f6970009
CRs-Fixed: 2729693
Due to changes in datapath init/deinit path, mon_lock spinlock was not
getting created. Create mon_lock spinlock during
dp_rx_pdev_mon_cmn_desc_pool_init.
Add null check to validate rx_tlv_header before calling
hal_rx_mpdu_start_tlv_tag_valid.
Change-Id: I41c781de29f2c8c05ec1bfa90f9c8f742f2539bf
CRs-Fixed: 2693687
Size of the TLVs have changed across generation of chipsets
Offset values need to be configured into DMA register for preheader DMA
Added APIs to get offsets of each TLV based on chip type
Change-Id: Ic011332cbf3a1017f324f246e47c9e2c91441c70
Support RX 2K jump/OOR frame handling from REO2TCL ring.
(a) configure REO error destination ring register to route 2K jump
/OOR frame to REO2TCL ring.
(b) for 2K jump RX frame, only accept ARP frame and drop others,
meanwhile, send delba action frame to remote peer once receive first
2K jump data.
(c) for OOR RX frame, accept ARP/EAPOL/DHCP/IPV6_DHCP frame, otherwise
drop it.
Change-Id: I7cb33279a8ba543686da4eba547e40f86813e057
CRs-Fixed: 2631949
In QCN9000, wbm release ring has msdu continuation bit
support for invld peer MPDUs. Host needs to form SG
buffer for packets with msdu continuation bit set
Change-Id: Ica03c78068d32d2c8dc609b9a50298b91dd48c0a
Intercept monitor destination path for NDPA frames,
use it to generate noack frames for tx capture.
Change-Id: Ia54196bd84729a7863954b6deec7e02b52f23556
CRs-Fixed: 2605672
For qcn9000, As part HW enhancements, PPDU_ID is sent
in reo_entrance_ring descriptor instead of RX_MPDU_START
tlv. Add support to read ppdu id from descriptor.
Modify existing hal API hal_rx_hw_desc_get_ppduid_get ()
arguments to pass RxDMA ring HW descriptor.
Usage:
a. Use hal_rx_hw_desc_get_ppduid_get () -
to get ppdu id from rx_tlv_hdr or hw descriptor based on target.
for qcn9000, this API gets ppdu_id from HW descriptor,
for other platforms, gets ppdu_id from rx_tv_hdr
b. Use hal_rx_get_ppdu_id () - to get ppdu_id from rx_tlv_hdr
Change-Id: I5838227c12cde50cbb2a9da7a0d8056b8b9b7ef5
Rather than extracting msdu end pkt tlv information per field basis
during fast data path, extract msdu end pkt tlv information at once
and store in local structure.
Change-Id: I0877ba4f824d480cc0851c72090f010852d0d203
Add a framework to configure varying buffer size for both data and monitor
buffers.
For example, with this framework, the user can configure 2K SKB for Data
buffers, monitor status rings, monitor descriptor rings, monitor
destination rings and 4K SKB for monitor buffers through compile time.
Change-Id: I212d04ff6907e71e9c80b69834aa07ecc6db4d2e
CRs-Fixed: 2604646
fix the issue for block ack/ack for tx capture mode.
1. Hanndle BAR frame.
2. set rate for ACK frame.
3. Check block ack session and use block ack if block
ack session is established.
4. no ACK for broadcast probe request.
5. not ack if the ack policy is set to no ack in qos control.
Change-Id: I4f22c1c976334978fb971b42319fb3a6e43a00c2
Channel Frequency Response(CFR) feature requires PPDU information
for correlation with CFR data. Host subscribes for the relevant PPDU
status TLVs via the Host RX monitor status ring. During monitor status
ring reap, all information needed for CFR correlation is accumulated
in a HAL PPDU structure and delivered to WDI event subscribers.
Change-Id: I3662b60375cb8886447a2fba3efead6a1ef3a98d
CRs-Fixed: 2593408
Link descriptor were getting freed by the pointer
of the previous freed link descriptor. This patch
fixes by copying the address of the current in a
local descriptor info and using it to free the
current.
Change-Id: I95e137ba5b1f0ad21b0e6fb39f6671e1d5b65ba6
CRs-Fixed: 2577624
Block ack and ack frame is composed and sent to up
layer after a unicast packet to AP is received for
tx capture feature.
Change-Id: I4b6bb35fa093432539d15d09a93f85a8ec700b34
Add hal_rx_get_rx_sequence API to retrieve
rx sequence value based on the chipset.
Change-Id: I8377b96dfe04e9695a183482d9fcc4a804f845e0
CRs-Fixed: 2522133
Implement hal_rx_tlv_get_tcp_chksum API
to retrieve tcp_udp_checksum value
based on the chipset.
Change-Id: Ifab970f10af06f8c0cdbd14d57cb66b49bae1648
CRs-Fixed: 2522133
Implement hal_rx_msdu_get_flow_params API
per chipset as the macro
to retrieve the flow parameters is
chipset dependent.
Change-Id: I6ef83232ebdf7497871a7fc588e082d14cdc9e75
CRs-Fixed: 2522133
Implement hal_rx_msdu_cce_metadata API per
chipset as the macro to retrieve the cce_metadata
value is chipset dependent.
Change-Id: Icd87d4ac32be78d69b24da106381a7669c86ada6
CRs-Fixed: 2522133
Implement hal_rx_msdu_fse_metadata API per
chipset as the macro to retrieve the fse_metadata
value is chipset dependent.
Change-Id: Iae7f532460b5203af2f95c504a6941c0b18b665e
CRs-Fixed: 2522133
Implement hal_rx_msdu_flow_idx_timeout API
per chipset as the macro
to retrieve the flow_idx_timeout value is
chipset dependent.
Change-Id: I03030e3763b3c4a9099699a2d24b8110961610cf
CRs-Fixed: 2522133
