Currently in monitor mode, links are released to WBM through the
SW2WBM_RELEASE ring and WBM will feed the links back to RXDMA
through the WBM2RXDMA_LINK_RING.
WCN6450 uses SOFTUMAC architecture where WBM is not present.
Hence the WBM2RXDMA_LINK_RING is repurposed to SW2RXDMA_LINK_RING
where host will directly release the links to RXDMA using this ring.
Change-Id: I110f607e38c4c2ab10eb1bd7b1f5a7bce2f03692
CRs-Fixed: 3493368
The kernel-doc script identified some documentation issues in the
hal/wifi3.0/qcn9000 folder, so fix them.
Change-Id: I8e15c38f02610a02d9f5a553b328e0bc7333271e
CRs-Fixed: 3411746
For 802.11 Fragmented frames, currently there is a
generic GetFrameControl API from RX TLV for all Li
Chipsets. As the offset for frame control in RX TLV
is different for QCN9000 and QCA8074V2, reading the
frame control with generic API gives wrong frame
control value. The Offset is different as the size
of RX_MSDU_START struct is 8DWORDS in QCA8074v2 while
it is 9DWORDS in QCA9000. In the reo reinject path
the destination queue descriptor address read from ring
descriptor address is Invalid
Fix is Separating out the GetFrameControl API from
generic API to Chip specific API. Also fix the reading
of queue descriptor address.
CRs-Fixed: 3280809
change-Id: Ifc5eca31b9b7e70c84ca455d56a58c27601cd51d
In QCN9224 fetch the peer meta data from the msdu end tlv
instead of MPDU start
Change-Id: Icd9420cd83e06abe5e54e9e05cc8cbf8d8312ae1
CRs-Fixed: 3245626
Change macro IPA_WDI3_RX_TWO_PIPES to IPA_WDI3_VLAN_SUPPORT to represent
the feature supported under this macro
Change-Id: Ie1e387d641052cd5690c63f0c1216f4852544605
CRs-Fixed: 3250264
In IPA offload, both tagged and untagged traffic cannot be handled with
a single rx pipe. Hence, add support for 2nd RX pipe for tagged and
untagged traffic respectively.
Change-Id: I77ff633327696f66df42fb592492321c1591646b
CRs-Fixed: 3226021
Skb under panic issue is seen when a packet comes via RX err path,
MSDU length read by SW is coming as 0 and leaving no space for skb_push
in buffer, data is moving beyond the head and causing the issue.
MSDU length is read by generic API which is architecture-independent,
hence the struct size for one architecture is different from another
architecture.
FIX is to get the MSDU length by architecture-specific API.
Change-Id: I5a6259034e5e06ae9ce7ba6b135b44f2849f2fd9
CRs-Fixed: 3235636
Currently in some case we are receiving non error packets on REO2TCL
ring, which is causing issue.
Fix is to set DEST_RING_MAPPING_0 to SW1 for REO dest ctrl
register, So that non error packets with reo_destination_indication
with 0x0 in the reo entrance ring will be routed to SW1 ring.
Change-Id: I67f78f35e7dba899943307902d99d0325a60498f
CRs-Fixed: 3150186
Add change:
1. Extract phyrx abort and phyrx abort reason error
code from PPDU END TLV
2. Extract additional necessary fields from L SIG,
HT/VHT/HE SIG TLVs
Change-Id: I3b05009cdc7ce7b585c00d1690ad238b9e6a88b2
Enable the 4th Tx. completion ring to save CPU load
Initialization and interrupt handling for 4th completion ring
is done here.
Change-Id: I2db27218a3c3e14d719d012f03454a6a7aa647fe
In WBM error processing read peer_id from peer_meta_data
instead of sw_peer_id.
This changes is needed because we need to process Rx packet
on ML peer. But in MLO case sw_peer_id field contains
link_peer_id where as peer_meta_data has ml_peer_id.
Change-Id: I3f469adfdf7efa88cb081e94fa9fe0c54c1fb078
HAL generic APIs which use HW definitons that
do not have same value across all lithium chipset
are moved to header files. So that these will be
compiled with appropriate header files
Change-Id: I6c167afa4212c5e884f5e18ff1ccb3bbbba8f5f5
Currently the hardware srng register offset is statically
assigned to the handle. This can lead to incorrect index access
when targets (eg: wcn7850) is added which require additional
register offsets to be stored in the hw srng register offset table.
Move to the index based assignment of the srng register offset.
Change-Id: I8e38bdd0c28068029a0267fce706edf4378b9df8
CRs-Fixed: 2965081
Assign th HAL TX/RX ops in a function instead of assining a structure
directly. This can be later extended to have default ops for a family of
chips and then override that with chip specific ops.
This also helps the case where a new hal_soc->ops needs to be added.
The new 'op' will need to be added to only a default ops initializer
(with assumption that it applies to all chips).
Change-Id: Iefa23d14110fa5252444fad89737a3b2b2fbab6f
CRs-Fixed: 2891049
Currently the FW configures the mac with appropriate
offsets for rx pkt tlvs using the structure defined in
te FW and the host does not send the ring selction config
HTT message. This can create a problem when FW stops subscribing
to tlvs or changes its rx pkt tlvs offset.
Fix this by configuring the rx pkt tlv offsets via HTT
ring selection config message.
Change-Id: I1a2865f91b34dd7bda1af8651d7831097dac0bee
CRs-Fixed: 2860504
Change hal_hw_txrx_ops struct to designated initializer syntax for
structs for qcn9000.
Change-Id: I3144d5f184d196365e49d6afae843316fef0f1e2
CRs-Fixed: 2837917
If frames from the same FISA flow goes into different REO2SW rings, it
will result in an unexpected FISA behavior. This can happen if the
frames have been reinjected from FW offload module since FW will select
REO2SW1 ring. If the same flow frames hash to other REO2SW rings, then
the same flow UDP frames will do to different rings.
Reo_destination_indication of 6 indicates if the frame has been
reinjected from FW. If so, then continue to deliver the packet without
FISA.
Change-Id: I14a17a10d04909adfb30557d58beb1610e59bf70
CRs-Fixed: 2790292
In QC9000, the channel capture status gets update in reserved_8
field's lower 2 bits only. Remaining bits are used for debug.
CRs-Fixed: 2740908
Change-Id: I97321addb18f8e5944f5f58d670dfa9858dca4ec
Adding support for enabling ini config to remap reo destination rings
for HK v1, HK v2, maple and pine platforms.
Change-Id: Id9d304521f32497e3acd845ddd2973b96b641516
Size of the TLVs have changed across generation of chipsets
Offset values need to be configured into DMA register for preheader DMA
Added APIs to get offsets of each TLV based on chip type
Change-Id: Ic011332cbf3a1017f324f246e47c9e2c91441c70
Support RX 2K jump/OOR frame handling from REO2TCL ring.
(a) configure REO error destination ring register to route 2K jump
/OOR frame to REO2TCL ring.
(b) for 2K jump RX frame, only accept ARP frame and drop others,
meanwhile, send delba action frame to remote peer once receive first
2K jump data.
(c) for OOR RX frame, accept ARP/EAPOL/DHCP/IPV6_DHCP frame, otherwise
drop it.
Change-Id: I7cb33279a8ba543686da4eba547e40f86813e057
CRs-Fixed: 2631949
In QCN9000, wbm release ring has msdu continuation bit
support for invld peer MPDUs. Host needs to form SG
buffer for packets with msdu continuation bit set
Change-Id: Ica03c78068d32d2c8dc609b9a50298b91dd48c0a
Add HAL layer changes for full monitor mode.
Define HAL API and Data structures to read sw_monitor_ring
descriptor.
CRs-Fixed: 2630982
Change-Id: I015fa106d9da74222bef092d50e96fc70a117a4a
For qcn9000, As part HW enhancements, PPDU_ID is sent
in reo_entrance_ring descriptor instead of RX_MPDU_START
tlv. Add support to read ppdu id from descriptor.
Modify existing hal API hal_rx_hw_desc_get_ppduid_get ()
arguments to pass RxDMA ring HW descriptor.
Usage:
a. Use hal_rx_hw_desc_get_ppduid_get () -
to get ppdu id from rx_tlv_hdr or hw descriptor based on target.
for qcn9000, this API gets ppdu_id from HW descriptor,
for other platforms, gets ppdu_id from rx_tv_hdr
b. Use hal_rx_get_ppdu_id () - to get ppdu_id from rx_tlv_hdr
Change-Id: I5838227c12cde50cbb2a9da7a0d8056b8b9b7ef5
8074 and QCN9000 coexist, so make hal_rx_msdu_packet_metadata_get()
as chip specific
Change-Id: I5b0b5e7f8915d12d4b267d5f07b03b47bb49a83f
CRs-Fixed: 2595314
Move HAL_RX_MSDU_END_DA_IDX_GET macros to chip specific header file.
Fixing compilation failure for 6490 and 6750.
hal_rx_msdu_packet_metadata_get_generic need not be chip specific,
macros defining the function are already chip specific.
Change-Id: I940a289662bdeddfbf99fae2a80d7796334832e7
CRs-Fixed: 2595314
Rather than extracting msdu end pkt tlv information per field basis
during fast data path, extract msdu end pkt tlv information at once
and store in local structure.
Change-Id: I0877ba4f824d480cc0851c72090f010852d0d203
the current HAL API is to read the WBM internal error
bit from the wbm release ring descriptor is always taking
HKv1 HW structure. But the wbm_internal_error bit
placement has changed from HKv2, for this reason we have
to use target specific HAL API.
Change-Id: I44789180754ca21ae59650b6d8620321a1f12569
Channel Frequency Response(CFR) feature requires PPDU information
for correlation with CFR data. Host subscribes for the relevant PPDU
status TLVs via the Host RX monitor status ring. During monitor status
ring reap, all information needed for CFR correlation is accumulated
in a HAL PPDU structure and delivered to WDI event subscribers.
Change-Id: I3662b60375cb8886447a2fba3efead6a1ef3a98d
CRs-Fixed: 2593408
Write into hal register using three floating windows instead of one.
This change is done to avoid frequent window changes for writing into
DP and CE registers. Instead 3 windows are used. One window is statically
mapped to CE block and another window is mapped statically to DP block.
Due to this design there is no need to change the window register to
write into these blocks and write can be done on corresponding window
with single iowrite32. Similar loginc is used for ioread32.
Also modified the hp_addr and tp_addr in initialisation stage so that
hal_write will not have multiple if checks.
Change-Id: Ibb99ec4da7f63323082e46a28afbe90e1f555545
CRs-fixed: 2507441
Add hal_rx_get_rx_sequence API to retrieve
rx sequence value based on the chipset.
Change-Id: I8377b96dfe04e9695a183482d9fcc4a804f845e0
CRs-Fixed: 2522133
Implement hal_rx_tlv_get_tcp_chksum API
to retrieve tcp_udp_checksum value
based on the chipset.
Change-Id: Ifab970f10af06f8c0cdbd14d57cb66b49bae1648
CRs-Fixed: 2522133
Implement hal_rx_msdu_get_flow_params API
per chipset as the macro
to retrieve the flow parameters is
chipset dependent.
Change-Id: I6ef83232ebdf7497871a7fc588e082d14cdc9e75
CRs-Fixed: 2522133
Implement hal_rx_msdu_cce_metadata API per
chipset as the macro to retrieve the cce_metadata
value is chipset dependent.
Change-Id: Icd87d4ac32be78d69b24da106381a7669c86ada6
CRs-Fixed: 2522133
Implement hal_rx_msdu_fse_metadata API per
chipset as the macro to retrieve the fse_metadata
value is chipset dependent.
Change-Id: Iae7f532460b5203af2f95c504a6941c0b18b665e
CRs-Fixed: 2522133
