1. Change the names of parameters and functions related
to direct switch feature from ppe to ppeds
2. Remove the unused ppe_release_ring
Change-Id: I5a95b1273e338f354903af98158578ac65758a8a
CRs-Fixed: 3345097
The kernel-doc script identified a multitude of documentation issues
in the wlan_cfg folder, so fix them.
Change-Id: Id6bfb397608de6b858e448a867a3c21dffc9a178
CRs-Fixed: 3352408
Enable and register PPE2TCL and REO2PPE ring interrupts
for direct switch
Set interrupt timer threshold for ppe2tcl ring as 30 us.
Change-Id: Ida1ff6c3c2000f16f07960f7eae0d10edc337dc0
CRs-Fixed: 3341790
Change minimum limit of dp_rxdma_buf_ring and
dp_ipa_tx_alt_ring_size value for ini may change little.
Change-Id: Ibbf8843b8f21bbfff1db83a0934f95222930b9ab
CRs-Fixed: 3338076
On low memory targets, even with current min values, OOM is seen
on driver load time. This requires us to further reduce
the min value.
With 11be enabled, current max value may not meet KPI requirements.
Hence align min and max INI values for IPA TX ring and TX completion
ring size with HOST used ones.
Change-Id: Iedf1c2d4be04d798314e9ba61a844038c5696f45
CRs-Fixed: 3338114
To support MLO on 4 chips, update the maximum number of chips that
can participate in MLO to 4.
CRs-Fixed: 3314581
Change-Id: I93a253b4e54f7e4e19ea8407facfb69e6347d192
Enable ppe direct switch feature by default
through ini, and rename the ppe_enable parameter
to ppe_ds_enable
Change-Id: I574838394ab9edd0445f65f81f05566967208276
CRs-Fixed: 3339167
Add ini configuration to disable invalid decap type handling
during rx mon tlv processing. This is a temporary change for
debugging purpose and will be removed once HW issue is resolved.
Change-Id: I75eb53170833224ddd144baf1b1d8034f988dd3c
CRs-Fixed: 3308998
Add ini param "dp_disable_rx_buf_low_threshold" to disable
low threshold interrupts on regular rx refill ring. Default
it is enabled.
Change-Id: Ie471a4dc6862cbfe8b1eafe7c7d2ce2e0a7fcb7a
CRs-Fixed: 3313885
delete QCA_TEST_MON_PF_TAGS_STATS to enable stats by default
and just use flag to enable debug nbuf_head dump
Change-Id: I0b0bb627f4d597d28181a11c38fa18b191210da4
CRs-Fixed: 3278411
Update the prealloc size for RXDMA_BUF and REO_DST
rings using the ini values which have been configured.
Change-Id: Id47fbca3a79b37bba902d1b5bd0bf8c6073648cc
CRs-Fixed: 3283986
1. Add stats to indicate REO ring size and Rx desc pool size
2. Add low threshold interrupt stats
3. Update SW2RxDMA ring size max to 16K
Change-Id: If84b88bc08e447774ab445df36b9f2f2219356b8
CRs-Fixed: 3286940
add debug prints and a custom timer for how long to wait to receive next
bk pressure event message.
Change-Id: I5a736b0f134cd179990de536da02967db3e39774
CRs-Fixed: 3273427
Add framework to use different RX hash values and ring masks
for ML and non-ML peers
Change-Id: I098cb50b8873eb137ce096011d01a5c21aaf854f
CRs-Fixed: 3269916
At 802.11BE 320 MHz throughputs, flow collision and
the resultant flow eviction can lead to throughput
degradation. Skid length is a parameter which can be
used to reduce these continuous flow eviction from the
FISA flow table.
Increase the FISA flow table skid length to 16 to reduce
the chances of flow eviction from FISA flow table.
Change-Id: I3badcb364d45b19a8a266fe335df320c30f999ae
CRs-Fixed: 3232508
Currently in monitor mode for KIWI, interrupt for RXDMA2HOST is
enabled to process both monitor status srng and montior destination
srng, but low threshold interrupt for monitor status srng is also
enabled. so when available RX buffer in monitor status srng is less
then low threshold, it is possible that two kind of interrupt from
RXDMA2HOST ring and monitor status ring will call
dp_rx_mon_status_process_tlv() in different context and access to
mon_pdev->rx_status_q at the same time, this will lead to skb
double free issue.
solution:
(1) disable RXDMA2HOST srng interrupt in monitor mode.
(2) enable monitor status srng batch count interrupt for monitor
processing.
Change-Id: I1df8830cb7cc55468e5df5e49045c3d96f7c29a8
CRs-Fixed: 3245393
With KIWI_V2, wbm_ring_num for WBM2SW5 and WBM2SW6 have been changed
to 5 and 6. Hence properly update them in g_tcl_wbm_map_array. At the
same time, tx_ring_mask_msi and tx_ring_near_full_irq_mask are also
updated.
With IPA_OFFLOAD enabled soc->tcl_data_ring[0|1|2] is used by HOST
and the other two rings are allocated to IPA usage.
Change-Id: I4c13d0787e46be667c3a5a0ae624df8c2b2b354e
CRs-Fixed: 3229375
UMAC HW reset feature will be using the last interrupt context in each
DP interrupt combination i.e., on a system with more than 8 MSIs for DP,
UMAC HW reset will be assigned a dedicated interrupt context.
Add the necessary support for the same.
CRs-Fixed: 3163900
Change-Id: I26abd01e4261661ed95e1aa3cb2a774e78b50d9f
Currently the max number of rx descriptors, via INI,
is 4096, which is not sufficient if the number of
entries in rx buffer refill ring is increased.
Hence the set the max allowed number of rx descriptors
to 16K, which is also the max allowed entries in the
rx buffers refill ring.
Change-Id: I287a3f47525179ebf8de65e2f8310a961881916b
CRs-Fixed: 3224590
Increase the number of DP interrupts to 16. The interrupt assignment
table is updated to add new values for different MSI interrupts
available. 9, 10 and 11 MSIs configuration will take the same
configuration as that of 8 MSI. 13, 14 and 15 MSIs configuration
will take the same configuration as that of 12 MSI. New MSI assignment
configuration is introduced for 12 and 16 MSIs.
Change-Id: I82af75b21c793a62fc8f0bd5515e1160b601c0c2
CRs-Fixed: 3209397
Enable bits in WMI_INIT command to let the FW know about host's
capability to support notify frame feature. If the feature is enabled,
host can mark certain TX frames as "notify frames" for hardware and they
need not be sent to FW. FW depends on this capability exchange to decide
whether to install HW rules for frames to be sent to HW.
Change-Id: I7158e79ae0fbdc73a2f4096ae1577337e8291246
CRs-Fixed: 3209399
NAPI scale factor should be configured based on the board
type. for example Hawkeye could have a different scale factor
compared to Alder.
CRs-Fixed: 3212330
Change-Id: Ie0bad6aade9ca9379997aa974154f9fb903ab93e
Add ini support to configure TC ingress filter priority
value which would be used for TC based dynamic GRO.
Change-Id: I1742f4539353939e3a40ff4096b3f833f2029b12
CRs-Fixed: 3206817
Change tx monitor ring sizes and make minor fix when getting the
number of entries.
Change-Id: Iec458d88948556f7007d4fa33bf082c8ee089064
CRs-Fixed: 3206170
Limit the desc pools such that the max ppt entries
do not cross limit for the hardware cookie conversion.
Change-Id: I9149b20bea0d72b466ef8c3e2ee9c0b536ffe24e
CRs-Fixed: 3201792
Increase max value of Rx refill ring size that
can be configured via ini to 8192
Change-Id: I5180996181e43d26221e0106488eda86cf711e1c
CRs-Fixed: 3198408
This is a WAR to match the TX_DESC_POOL size
to maximum number of VDEVs allowed.
Change-Id: I646a67ef2b611bea1ca5a6e2bf781a9454d409ed
CRs-Fixed: 3168359
Currently, data stall detection is without control over
individual data stall events.
INI variable, gEnableDataStallDetection is converted from
boolean to unsigned int which provides control over events
across FW and host with each bit corresponding to different
data stall events.
Bit 0: Enable all data stall events if set.
Bit 1-30: mapped to data stall events. Used when Bit 0 is 0
Bit 31: Enable aggressive timeout for WLM Mode.
Change-Id: I4656520accd1589e77d5054eaa0a3cb8e63b14b2
CRs-Fixed: 3174906
For SW2HW ring, if time threshold is non-zero and low threshold
is 0, then if ring is empty, HW will keep generating low threshold
interrupt always which then LPL failed.
Configure SW2HW ring timer threshold 0 to disable low threshold
interrupt, also set batch_count threshold 0 as host not need the
interrupt if HW consumed entries.
Change-Id: I6c8ea516e66abd706fecd97649f3a19702453b85
CRs-Fixed: 3149341
Add support to change the tx_desc value to 65536. Some changes
to make the function argument as u32 type us made
Change-Id: I7cbde1b7ed4ab4e278c25c1ecfa94b7f673197f2
CRs-Fixed: 3130833
Make 1:1 dependency on num REOs and rx_thread. Keep num rx_thread
dependent on rx REO rings, 1 rx_thread for each rx REO ring.
Controlled via INI dp_reo_rings_map.
Change-Id: I7c199226cfa3f173ea328d71075816b8eb9ba91f
CRs-Fixed: 3048260
Ageout flush does not happen for WBM2SW4 if there
is only one TX completion pending in FIFO and all the
other WBM release rings are not active. This is due to
an issue in HW and this prevents suspend to happen due
to pending tx completions.
Fix is to avoid using WBM2SW4 release ring and instead
reuse WBM2SW0.
Change-Id: I250d8c9d460895449939212ebdb7abd62edb0234
CRs-Fixed: 3124733
