Replaced lane swap register for lane swap in DSI controller.
Added check for where to perform lane swap based on DSI controller
version. Replaced function to parse device tree data for lane swap,
as previous function did not work.
Change-Id: I5e50a761b6ac0d2658ba73a5648e2f80f3470b96
Signed-off-by: Rohith Iyer <quic_rohiiyer@quicinc.com>
Current implementation we apply the color properties when atomic begin
is called and mark features as dirty if crtc is not enabled.
For some of the non double buffered features in video mode we will
see a corruption. Change removes marking color properties as dirty
based on crtc on/off.
Change-Id: I4d93b14627d2bc06fcbca3ea9538a4baedb00e56
Signed-off-by: Lakshmi Narayana Kalavala <quic_lkalaval@quicinc.com>
Wait for the userspace to disable DP when usb cable is removed
during DP simulation. The usb notifier is a blocking call.
Change-Id: I6c00cc684b4d99da30a129f034eb17bf505738bb
Signed-off-by: Sankeerth Billakanti <quic_sbillaka@quicinc.com>
When broadcast command is sent with command DMA window scheduling enabled,
DSI_TRIG_CTRL.COMMAND_MODE_DMA_TRG_MUX does not get reset after command
transfer. Due to this next unicast command on slave fails.
This change resets DMA trigger mux during DSI_TRIG_CTRL initialization.
Change-Id: I74503d82ab1cb6ca4d61a9d14f2b3cd2c3936ea7
Signed-off-by: Kashish Jain <quic_kashjain@quicinc.com>
In DMA start window scheduling, TRIG_CTRL.COMMAND_MODE_DMA_TRIGGER_SEL
is programmed to SW + DMA start window trigger. But if DMS switch
comes after command is scheduled, COMMAND_MODE_DMA_TRIGGER_SEL gets
reprogrammed to SW trigger leading to command transfer failure.
Program the COMMAND_MODE_DMA_TRIGGER_SEL only from the CMD DMA Tx path.
Change-Id: I01062497bb70aa5fdcb25be3715c7cbc4c68b681
Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
Signed-off-by: Rajeev Nandan <quic_rajeevny@quicinc.com>
Signed-off-by: Kirill Shpin <quic_kshpin@quicinc.com>
In MST atomic check function, allow to release vcpi slots for
any case of changes in modes, active state or connectors for a crtc state.
This reverts the commmit id 28cde80bd3666b6b339a21cac3d04b3b11c318b6.
Change-Id: Ice13790f2e652b336619e1d78b42ddb708b4cb2e
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
Attach the S2-only secure camera preview buffers with dummy drm
device during dma_buf_attach. This will ensure when sg_dma_address
will return the phys address for this buffer as its not backed
by a context-bank.
Change-Id: Iafd40352b92b842d19194976fa4b58e1e07e6f0d
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
When a display is disabled, the mst slot payloads get updated in the
topology manager and also the start_slot for the remaining payloads
get adjusted, if necessary to start from 1. But the copy of these
values in dp_mst_drm context are getting readjusted properly. But
since the local context is used to update the slot configuration in
the dp controller, it is possible for the slot configuration in the
source and sink to mismatch causing blank output.
This change introduces a 2 pass solution while updating timeslots to
make sure the values in the bridge context reflect the values in
the topology manager.
Change-Id: Ia6f66e8d5ffcde3f25b1b2649733a547a06de995
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
This is a partial revert of I67ace5c064b2b56d03732a78f334ea6b1b649608 which tries
to enable Sink CRC irrespective of the sink's CRC capability to workaround an
issue with a specific sinks which reports incorrect capability on first plugin.
But this causes some MST dongles to misbehave causing one or both outputs to
be blank.
Change-Id: I70c70db8ac371fe0094a45780216a2518d688a36
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
Attach the dmabuf with cp-pixel vmid to secure-cb device and the
tvm vmid in HLOS to DRM device to support CSF 2.5. Some cases like
DEMURA has dmabuf set with both cp-pixel & tvm VMIDs as its used
in HLOS and shared with Trusted-vm. Attach to secure-cb device in
these cases.
Change-Id: I97f59cc01bb5ea18061541e68454b848f1a78a09
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
This change adds hardware programming that will update the
txq wr_ptr upon output fence firing.
Change-Id: I79ff0ea5fb2b7f73a48bd70e3c8e71ea69fead95
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
For a proxy-scheduled VCPU like the TUI VM, assignment to a
physical core is a runtime decision made by the HLOS scheduler,
and it may change frequently. pm_qos vote added by PVM for
specific CPUs won't be sufficient for addressing irq latency.
This change updates votes for all possible CPUs during TVM
entry and also removes the vote during exit.
Change-Id: Iab5cb5f57e2389ee57689ba2ab69394376f59788
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
After introducing avr step state, the driver checks for avr
state none before returning early. In the case where avr property
is not being set, this leads to skipping qsync programming.
This change removes this state check.
Change-Id: Ie277dd04b8913358135210131a99c598cf2145ba
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
Both trusted-vm and secure-camera preview buffers uses the same
VMID_TVM. In primary-vm, the check is used to determine the camera
preview usecase and attach it to the correct device. This is not
necessary for trusted-vm as it can default to nested trusted-vm
context bank. Avoid the check while its in trusted-vm.
Change-Id: I4391a4a1da9dca5d1f4b1719733b8d4edc1900a8
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
During DP disable, it is possible for audio and display to race
causing the audio to send teardown notification after display driver
has disabled all the clocks. This change adds a check for panel state to
avoid accessing registers during this callback.
Change-Id: I6322726a04745bc6c73338cd33f65cfdbfe42ec7
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
Force max supported bpp to 24 to improve stability of MST usecases.
Change-Id: I5b0e6ad86df39915073f469ea67e6addea165965
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
The DP debugfs node for CRC read currently does not check
if the panel is enabled before attempting the read. This
could cause unclocked access of DP registers. This change
adds the necessary protection and bails out if the clocks
are not turned on.
Change-Id: Ia555e2473fc9f0f7434ee3665eb4fb7cfb4f97cf
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
Currently the ipc context for drm_dp_aux is being created
during dp_aux_init. This limits the IPC logs to be only
readable when the external display is in connected state
and it gets destroyed on unplug. This change moves the
context creation to probe time and the aux context will
be passed to the aux driver during initialization.
Change-Id: Id8d26c907c9cb2fd8c89b2842b98e7a908816abe
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
Some rate limited logs in dp aux and dp ctrl are using
pr_err_ratelimited function to print the logs instead of
the standard DP log macros. So this change adds a new
ratelimited DP log macro and make the logging consistent.
Change-Id: I75d7306d94c7c360783f39259c509c32fe59cdf5
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
PPB size programming checks for the max horizontal width of the
panel by checking all available modes. In some DP usecases,
it is possible that this information is not ready at this point.
However, this is not an error, as by default driver will set the
maximum size.
This change reduces the error log to a debug warning.
Change-Id: Ieb63524457db410a2569682f2c3863e082c60805
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
Some of the demura config parameters are single buffered. When demura
config is reprogrammed by user-space clients, single buffered updates
can cause artifacts on screen. Change splits the double buffered and
single buffered configs into different payloads to allow user-space
to update double buffered config.
Change-Id: I493b86944f7c2d630dcc1b863174e816cf8c82ed
Signed-off-by: Gopikrishnaiah Anand <quic_agopik@quicinc.com>
When the vblank event overflow error log occurs due to an inability
to handle incoming vblanks, it is posisble to continuously flood
with error print logs. This could cause the CPU to become further
blocked and creates a cycle of failed callbacks and error logging.
This change changes the overflow log in the crtc event thread to
rate limited.
Change-Id: Ie2d77689c8fa989cf3a294f973851b7dacef098b
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
During VM transition there should be no pending crtc event
thread operations in progress to avoid any resource access
after vm release. Flush the event thread worker in prerelease
to ensure it.
Change-Id: I51d6c78a702235ee926c9ff6415c8d69f74b5929
Signed-off-by: Raviteja Tamatam <quic_travitej@quicinc.com>
Large allocations using kvzalloc can lead to timeouts.
This updates the allocation calls accordingly to use
vzalloc to remove requirements on physically
contiguous memory.
Change-Id: I437913b3bf2e46bfeeb2c511bdfc153470fcbc24
Signed-off-by: Anjaneya Prasad Musunuri <quic_aprasad@quicinc.com>
Some monitors seem to be not enabling Sink CRC capability on first plugin
and therefore the CRC read returns all zeros. But on subsequent plugins
the capability is set properly and CRC values are calculated. To
workaround this quirk on the sink side, this change reenables sink CRC
if the values are read as zeros.
Change-Id: I67ace5c064b2b56d03732a78f334ea6b1b649608
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
Starting pineapple, the output_fence trigger_sel register is updated to be
more controllable. Instead of hardware choosing the output fence timing
based on detecting if panel is in video/cmd mode, this is explicitly set
by software. Add support in display driver for to correctly write to
trigger_sel register for video mode.
Change-Id: I76d8cfb644cebfd2f34f3017fc779b87fc52db1a
Signed-off-by: Grace An <quic_gracan@quicinc.com>
While same spinlock can be used to protect a critical section
in both irq-handler and in non-irq context, in non-irq context
it is mandatory to use irqsave version of locking api to disable
irqs locally on the particular cpu. Otherwise, this could lead
to a deadlock if a non-irq thread holding the spinlock and irq
handler is scheduled on same cpu.
This change replaces physical encoder spinlock locking with
irqsave version of locking api in the non-irq context.
Change-Id: If73b4c995b75e9499d79fbe969d426427fd3a9d1
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
Chaining of dma-fence need to be used for chaining fences of
buffer objects of each color plane. Max color planes currently
supported in upstrean is 4. Current logic incorrectly referring
drm-plane index instead of color plane index and fails to get
buffer object. This change fixes the buffer object indexing
beyond max color planes and dma-fence chain usage.
Change-Id: I20618d3617ee638432e4e2d68540e345c241ee97
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
