In some hardware, it is possible that global clear command on an
independent controller can clear relevant status bits of a dependent
controller due to the clear register being dirty. This commit
introduces lazy clear register sanitization.
In case of a dirty clear register in a dependent controller, the IRQ
controller waits till the next interrupt and checks if that clear
register is going to get updated. If not, that clear register is
sanitized (set to zero).
CRs-Fixed: 3152588
Change-Id: Ie94252fb378676481410759c8bc87088d27024dd
Signed-off-by: Anand Ravi <quic_ananravi@quicinc.com>
If an IRQ status register has not caused the interrupt to be triggered,
we can skip writing to the corresponding clear register as long as no
previous writes have been made to it that will cause bits of interest to
be cleared (i.e. clear register is dirty). For this, we maintain a dirty
flag for each clear register.
The dirty flag will never cause false negatives (i.e. valid writes to be
missed) since hardware cannot set any bits in the clear register to 1
and will only clear the entire register upon resetting the hardware.
CRs-Fixed: 3152588
Change-Id: I4f97bae0e3cd983ca66d5b89ffb2c16da7c25200
Signed-off-by: Anand Ravi <quic_ananravi@quicinc.com>
Due to delays, frame count may not be increamented. Sending such
notifications increase the number of invalid notifications in User
space. If the frame count is same, skip sending the timestamp
to userspace. This provides more time to recover from the delays.
CRs-Fixed: 3164368
Change-Id: I09a96bbafb80233e962304d9a82fde45233a5f89
Signed-off-by: Gaurav Jindal <quic_gjindal@quicinc.com>
This change adds a link properties opcode to get
the property level configuration, we can define
different properties and do some special process
per link in CRM.
Also add a new error code to indicate the error
of streaming off.
CRs-Fixed: 3163906
Change-Id: I7ebb54e5148fb10f74a710a95aeb7ca10d83be71
Signed-off-by: Depeng Shao <quic_depengs@quicinc.com>
In Non-SFE use cases, camif interrupts from CSID are sufficient to
run the state machine. In SFE cases, interrupts from VFE can be
used to drive the state machine.
This commit adds changes to subscribe the IRQs based on the
use case.
Change-Id: I75c2bc4f6e0754ef1e80a2d4f291b18f16900475
CRs-Fixed: 3153295
Signed-off-by: Gaurav Jindal <quic_gjindal@quicinc.com>
Add register header file for SFE 880 target. Modify
data structures, Macros in SFE top and SFE bus write/read files
accordingly. Update compatible dt match to include sfe 880.
CRs-Fixed: 3175256
Change-Id: I4205578ce473b69f01b3ce79b4f29547d957bb44
Signed-off-by: Sokchetra Eung <quic_eung@quicinc.com>
Add output port - HDR_STATS for SFE880 and update all mappings
associated with the port.
CRs-Fixed: 3175256
Change-Id: I1a856f3c705d651a486e0aba5a77ca73f0deb5a5
Signed-off-by: sokchetra eung <quic_eung@quicinc.com>
In case of bubble recovery stalling try internal recovery,
halt, reset and resume IFE pipeline. If internal recovery
succeeds skip notifying userland for pipeline recovery.
If the same slot [same request] is stalled again, it will
flag for userspace recovery.
CRs-Fixed: 3098892
Change-Id: I6fff844fecd653897451ab920ddf6c4d8ca2f49e
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
Add support to handle a variation of ICP V2 for lanai.
IRQ registers have been moved to a different reg space.
Some registers that are currently used for debug will
not be accessible by HLOS on lanai, remove usage of them.
The change also removes dependency on the reg base order
populated in the DTSI, irrespective of the order the driver
will parse and find the respective base indexes.
The change also adds register specific info per chipset.
CRs-Fixed: 3175809
Change-Id: I70d768a9c196c23f798f4f98a4be53ce12c7175b
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
Optimize the names of some functions and add declaration
for them in head file.
CRs-Fixed: 3164829
Change-Id: Ia10ab83e0b6164a82fdd21b351477294bf4bbe4b
Signed-off-by: mingpan <quic_mingpan@quicinc.com>
a4a4378 Merge "msm: camera: isp: Remove max sfe out res macro from UAPI" into camera-kernel.lnx.dev
437c3c2 Merge "msm: camera: isp: Add separate IRQ controller for each CSID register" into camera-kernel.lnx.dev
65c0346 Merge "msm: camera: uapi: Change uapi header for SAT switch latency optimization" into camera-kernel.lnx.dev
12ee746 Merge "msm: camera: isp: Extend SOF timestamp recovery to first frame" into camera-kernel.lnx.dev
4d0243d Merge "msm: camera: isp: Add hardware header files for VFE and VFE-Lite 880" into camera-kernel.lnx.dev
7184613 Merge "msm: camera: isp: Add new WM port for VFE880" into camera-kernel.lnx.dev
db64859 Merge "msm: camera: icp: Update BPS register SWI for lanai" into camera-kernel.lnx.dev
Change-Id: Ic97d8bed4a18508ccb70420704d63dfda9c21d22
Signed-off-by: Savita Patted <quic_spatted@quicinc.com>
Remove max sfe out resource macro from uapi. Remove all usages
of the macro in ife hw mgr and sfe bus write files. Instead, use
max_out_res from sfe header files and Ife hw mgr calls to queries
max sfe out res from sfe bus wr.
CRs-Fixed: 3176997
Change-Id: Ie3fc36f3003305eeebcc60ec9539ff2c6630e337
Signed-off-by: sokchetra eung <quic_eung@quicinc.com>
This commit adds new hardware header files for VFE 880 and VFE Lite 880.
It also adds support for loading the hardware structs defined in these
files during probe time.
CRs-Fixed: 3168484
Change-Id: I617cbc0fa6f1fa45b3ff4ba503a65d6eb2e265c0
Signed-off-by: Anand Ravi <quic_ananravi@quicinc.com>
Add output port for STATS_ALSC for VFE880 and update all mappings
associated with the port.
CRs-Fixed: 3168484
Change-Id: I0a674e7d2d6fe5fa5a51ff31e22f066fa222e5b7
Signed-off-by: Anand Ravi <quic_ananravi@quicinc.com>
In CSID v2, the top status register indicates which other status
registers have values of interest. Adding a separate IRQ controller for
each such register, and registering them as dependents of the top irq
controller allows optimization of register reads and writes.
CRs-Fixed: 3152588
Change-Id: I930f9b9c58da0f45fffabb2929062d721bb9bbda
Signed-off-by: Anand Ravi <quic_ananravi@quicinc.com>
Tweak SOF timestamp recovery logic to handle sending timestamp for
first frame. This is needed when due priority inversion, ISP context
notifies timestamp before SOF.
CRs-Fixed: 3085335
Change-Id: I9baea8d906bb8f820c7aeb2d7d4ae1c1c6f348b2
Signed-off-by: Anand Ravi <quic_ananravi@quicinc.com>
For SFE use-cases, update the hw_idx and paths acquired
for userspace to consume. Currently even in SFE use-cases,
only IFE info is returned which may not be right always.
CRs-Fixed: 3175210
Change-Id: Ice0816993a208965032a71a924cd53f7ebc02e89
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
Add new macro for RDI4 to append in acquired path output.
CRs-Fixed: 3175210
Change-Id: Ic3999d0e84e938bacc62134c96126c689d6bb893
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
Currently the assumption is the order of the comp groups
and buf done status bits are the same for SFE write clients.
This may not be true for different targets. Add per group
shift value in header, removes dependency on comp group type
and buf done mask.
CRs-Fixed: 3175210
Change-Id: I802fb2676c20847148c02c9a46766115511a2450
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
When the req id of a slot is -1, we don't update the
last applied idx for this slot, if a bubble issue is
reported on previous slot, then we won't reset its
status to ADDED, then we will force reset it during
moving to new slot, then this slot will be reset, its
status will be NO_REQ after reset, then wr idx will be
increased even though the wr idx isn't equal to rd idx.
This change updates the wr idx only when wr idx is equal
to rd idx, and always update last applied idx.
CRs-Fixed: 3157732
Change-Id: I9e6cae019f93c7c12e81708a84e1ac28bf64bbc8
Signed-off-by: Depeng Shao <quic_depengs@quicinc.com>
Rename all instances of a5 and lx7 to icp_v1 and icp_v2
respectively. Remove all mentions of lx7 or a5 in icp_hw_mgr.
Relocate lx7_hw and a5_hw directories to a new directory -
icp_proc which contains a new file to provide related a5 or lx7
interfaces to icp_hw_mgr. Thus, icp_hw_mgr is agnostic to icp proc.
Place common functions and common global constant into icp_proc_common
file. Remove a5/lx7 soc files and create a common soc file for both.
Modify kbuild file to account for directory or file changes.
CRs-Fixed: 3162183
Change-Id: I7e0cfd2a2917f129097a517af3bd39578f85293d
Signed-off-by: sokchetra eung <quic_eung@quicinc.com>
The index of sfe out res in bus_priv is based on
the sfe out type, rather than the out index, So
we need to get the sfe out type by the out index
first, then get the sfe out res by sfe out type.
CRs-Fixed: 3165425
Change-Id: Ic35f6b5b23a0997c2f05f8950d0a82f488185d39
Signed-off-by: Depeng Shao <quic_depengs@quicinc.com>
In rare scenarios, FD is getting released by userspace
before incrementing the ref count. We see failure in
dma_buf_get API as FD is released but we are still
tying to decrement ref count in case of dma
buf get failure.
We are seeing use-after-free as the buffer is released.
This fix includes get_file API to increment ref count
before dma_buf_fd.
CRs-Fixed: 3156174
Change-Id: Ie9588ec10e65cbb8fa155badda4f3e5fb81c0525
Signed-off-by: Chandan Kumar Jha <quic_cjha@quicinc.com>
Remove the redundant CDM Register Write to IRQ mask
register just before the CDM Reset command. Intention
behind this register right is to ensure that the cdm
IRQ for Reset Done is enabled before we issue a reset
command. However, the reset value of the IRQ Mask
register always enables the reset done IRQ. Therefore
we can remove this redundant Register Write.
CRs-Fixed: 3163466
Change-Id: Ibcf55d17bb42de6ff1ad15fb542d8f682158b609
Signed-off-by: Jigar Agrawal <quic_jigar@quicinc.com>
Add CDM Debug register dump when the Bubble is detected due
to cdm callback not received.
CRs-Fixed: 3163463
Change-Id: I028ac9216704d14cc51648b0a5a78b0a2a366f12
Signed-off-by: Jigar Agrawal <quic_jigar@quicinc.com>
This change does hw recovery and reapply all alive requests
for bus overflow issues.
When we face bus overflow KMD fatal errors, instead of
sending error to UMD, we will try internal recovery and
send a warn message to UMD once internal recovery happens,
if we fail to do recovery, then sending error to UMD.
CRs-Fixed: 3098892
Change-Id: Idee3679ff06227f985e106470bc1f5a14c9cb404
Signed-off-by: chengxue <quic_chengxue@quicinc.com>
Signed-off-by: Depeng Shao <quic_depengs@quicinc.com>
This change fix unused error in cpas during compile when enable
CONFIG_CAM_TEST_IRQ_LINE and CONFIG_CAM_TEST_IRQ_LINE_AT_PROBE
issue, also fix can not find cdm irq line test interface when only
enable CONFIG_CAM_TEST_IRQ_LINE issue.
CRs-Fixed: 3169889
Change-Id: I673b150508d38bcf71ad33a5a9b38c6dff9a9578
Signed-off-by: zhuo <quic_zhuo@quicinc.com>
Shared memory is initialized by CRM and used by
other drivers; with CRM not active other drivers
would fail to access the shared memory if
memory manager is deinit. Reader Writer locks can
prevent the open/close/ioctl calls from other drivers
if CRM open/close is already being processed.
Issue observed with the below sequence if drivers
are opened from UMD directly without this change.
CRM Open successful,ICP open successful,
CRM close in progress, ICP open successful,
mem mgr deinit and CRM close successful,
ICP tries to access HFI memory and result in crash.
This change helps to serialze the calls and prevents
issue.
CRs-Fixed: 3019488
Change-Id: I84d50918713686a067c0e3deb64c9c6ae9edfcb5
Signed-off-by: Tejas Prajapati <quic_tpraja@quicinc.com>
Added support for new cdm status register for SM8650.
CRs-Fixed: 3147223
Change-Id: I35392cfb35613a777664e1fae2c24b0150c5b8ef
Signed-off-by: Li Sha Lim <quic_lishlim@quicinc.com>
When validating input/output formats in CSID, if there
is an error, it is being dropped and returned as success.
Handle this to ensure error is propagated from CSID to
HW manager.
CRs-Fixed: 3163468
Change-Id: Ic822feb4ca7418a68ed10ab9a17f72c2408d4759
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
In case of multi vc-dt fetch engine use-cases, validate
the input format for each VC, they are expected to be the same.
Different input formats for each VC for SFE FE use-cases, is
not supported.
CRs-Fixed: 3163468
Change-Id: I73aab062bc316f01af4fdbf3eb0155c7e1b2719e
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
This change is to print log in rate limit on unified SOF v4l2
error.
CRs-Fixed: 3099416
Change-Id: I2fed0c05a8180527cf5870406c43c952505956c6
Signed-off-by: Ayush Kumar <quic_ayushkr@quicinc.com>
In case of HFR, align the frame increment to 256 to support
36 bit addresssing scheme on Kailua.
CRs-Fixed: 3150471
Change-Id: Ib71132a73a0d07a012ca960718be69a8456a07b8
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
Upon Page Fault, smmu driver invokes faulted client's callback
which looks for faulted buffer and context. The client driver
can be ISP, ICP, JPEG, IFE CDM and CPAS CDM. The driver then
fills PF msg struct, logs related info, and notify PF msg to
userspace. Userspace is expected to abort and calls to shut
down kernel drivers. When Titan powers on next session, CAMSS
undergoes async reset.
This change also ensures the page fault related changes added
to TFE, OPE, CRE do not break the drivers compilation.
CRs-Fixed: 3156671
Change-Id: Icd6c8c9a38cac206fe8260d374d03964fb280879
Signed-off-by: sokchetra eung <quic_eung@quicinc.com>
Currently the ope request timeout value for RT and NRT context
are same. In some usecases, NRT request processing takes more time.
Hence, initialize the RT and NRT request timeout value separately.
CRs-Fixed: 3082993
Change-Id: I17e86d26403fb21cdff518a81dee7a19c865144e
Signed-off-by: Alok Chauhan <quic_alokc@quicinc.com>
For IFE only use-cases bump up the max number of configs
from 25 to 30, to support dual IFE requirements on Kailua.
CRs-Fixed: 3163468
Change-Id: Iffa5735fba3f8271b47ad368437b9174244ef889
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
Due to the scheduling delay, We are seeing back to back
two top half for buff done for 2 different requests
but we were expecting the bottom half after 1st top half.
We update the last consumed address in the bottom half so
we have 2nd req buffer address in last consumed reg as
we received 2nd req top half before 1st req bottom half.
We increment num_ack variable of 2nd request in case
of 1st req buff-done as it had 2nd buffer address in
last consumed address.
Ack is going beyond during the 2nd req buff-done.
This check will prevent duplicate acknowledgment increment.
CRs-Fixed: 3165255
Change-Id: I9ea3bca2a782bae6017565f30162484adf2fc789
Signed-off-by: Chandan Kumar Jha <quic_cjha@quicinc.com>
