msm: camera: isp: Add separate IRQ controller for each CSID register

In CSID v2, the top status register indicates which other status
registers have values of interest. Adding a separate IRQ controller for
each such register, and registering them as dependents of the top irq
controller allows optimization of register reads and writes.

CRs-Fixed: 3152588
Change-Id: I930f9b9c58da0f45fffabb2929062d721bb9bbda
Signed-off-by: Anand Ravi <[email protected]>

drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller/cam_irq_controller.c

@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
  * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #include <linux/slab.h>
@@ -14,6 +15,8 @@
 #include "cam_common_util.h"
 
 #define CAM_IRQ_LINE_TEST_TIMEOUT_MS 1000
+#define CAM_IRQ_MAX_DEPENDENTS 9
+#define CAM_IRQ_CTRL_NAME_LEN 16
 
 /**
  * struct cam_irq_evt_handler:
@@ -114,7 +117,7 @@ struct cam_irq_register_obj {
  *                          and spinlock in regular case
  */
 struct cam_irq_controller {
-	const char                     *name;
+	char                            name[CAM_IRQ_CTRL_NAME_LEN];
 	void __iomem                   *mem_base;
 	uint32_t                        num_registers;
 	struct cam_irq_register_obj    *irq_register_arr;
@@ -386,7 +389,7 @@ int cam_irq_controller_init(const char       *name,
 		goto evt_mask_alloc_error;
 	}
 
-	controller->name = name;
+	strscpy(controller->name, name, CAM_IRQ_CTRL_NAME_LEN);
 
 	CAM_DBG(CAM_IRQ_CTRL, "num_registers: %d",
 		register_info->num_registers);

drivers/cam_isp/isp_hw_mgr/hw_utils/irq_controller/cam_irq_controller.h

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #ifndef _CAM_IRQ_CONTROLLER_H_
@@ -38,8 +39,6 @@ enum cam_irq_event_group {
 	CAM_IRQ_EVT_GROUP_2,
 };
 
-#define CAM_IRQ_MAX_DEPENDENTS 2
-
 /*
  * struct cam_irq_register_set:
  * @Brief:                  Structure containing offsets of IRQ related

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid680.h

@@ -309,15 +309,59 @@ static struct cam_irq_register_set cam_ife_csid_680_irq_reg_set[9] = {
 	},
 };
 
-static struct cam_irq_controller_reg_info cam_ife_csid_680_irq_reg_info = {
-	.num_registers = 9,
-	.irq_reg_set = cam_ife_csid_680_irq_reg_set,
+static struct cam_irq_controller_reg_info cam_ife_csid_680_top_irq_reg_info = {
+	.num_registers = 1,
+	.irq_reg_set = &cam_ife_csid_680_irq_reg_set[CAM_IFE_CSID_IRQ_REG_TOP],
 	.global_irq_cmd_offset = 0x00000014,
 	.global_clear_bitmask  = 0x00000001,
 	.global_set_bitmask    = 0x00000010,
 	.clear_all_bitmask     = 0xFFFFFFFF,
 };
 
+static struct cam_irq_controller_reg_info cam_ife_csid_680_rx_irq_reg_info = {
+	.num_registers = 1,
+	.irq_reg_set = &cam_ife_csid_680_irq_reg_set[CAM_IFE_CSID_IRQ_REG_RX],
+	.global_irq_cmd_offset = 0, /* intentionally set to zero */
+};
+
+static struct cam_irq_controller_reg_info cam_ife_csid_680_path_irq_reg_info[7] = {
+	{
+		.num_registers = 1,
+		.irq_reg_set = &cam_ife_csid_680_irq_reg_set[CAM_IFE_CSID_IRQ_REG_RDI_0],
+		.global_irq_cmd_offset = 0, /* intentionally set to zero */
+	},
+	{
+		.num_registers = 1,
+		.irq_reg_set = &cam_ife_csid_680_irq_reg_set[CAM_IFE_CSID_IRQ_REG_RDI_1],
+		.global_irq_cmd_offset = 0, /* intentionally set to zero */
+	},
+	{
+		.num_registers = 1,
+		.irq_reg_set = &cam_ife_csid_680_irq_reg_set[CAM_IFE_CSID_IRQ_REG_RDI_2],
+		.global_irq_cmd_offset = 0, /* intentionally set to zero */
+	},
+	{
+		.num_registers = 1,
+		.irq_reg_set = &cam_ife_csid_680_irq_reg_set[CAM_IFE_CSID_IRQ_REG_RDI_3],
+		.global_irq_cmd_offset = 0, /* intentionally set to zero */
+	},
+	{
+		.num_registers = 1,
+		.irq_reg_set = &cam_ife_csid_680_irq_reg_set[CAM_IFE_CSID_IRQ_REG_RDI_4],
+		.global_irq_cmd_offset = 0, /* intentionally set to zero */
+	},
+	{
+		.num_registers = 1,
+		.irq_reg_set = &cam_ife_csid_680_irq_reg_set[CAM_IFE_CSID_IRQ_REG_IPP],
+		.global_irq_cmd_offset = 0, /* intentionally set to zero */
+	},
+	{
+		.num_registers = 1,
+		.irq_reg_set = &cam_ife_csid_680_irq_reg_set[CAM_IFE_CSID_IRQ_REG_PPP],
+		.global_irq_cmd_offset = 0, /* intentionally set to zero */
+	},
+};
+
 static struct cam_irq_register_set cam_ife_csid_680_buf_done_irq_reg_set[1] = {
 	{
 		.mask_reg_offset   = 0x00000090,
@@ -1202,11 +1246,20 @@ static struct cam_ife_csid_ver2_top_reg_info
 };
 
 static struct cam_ife_csid_ver2_reg_info cam_ife_csid_680_reg_info = {
-	.irq_reg_info                         = &cam_ife_csid_680_irq_reg_info,
+	.top_irq_reg_info      = &cam_ife_csid_680_top_irq_reg_info,
+	.rx_irq_reg_info       = &cam_ife_csid_680_rx_irq_reg_info,
+	.path_irq_reg_info     = {
+		&cam_ife_csid_680_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_RDI_0],
+		&cam_ife_csid_680_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_RDI_1],
+		&cam_ife_csid_680_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_RDI_2],
+		&cam_ife_csid_680_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_RDI_3],
+		&cam_ife_csid_680_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_RDI_4],
+		&cam_ife_csid_680_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_IPP],
+		&cam_ife_csid_680_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_PPP],
+	},
+	.buf_done_irq_reg_info = &cam_ife_csid_680_buf_done_irq_reg_info,
 	.cmn_reg                              = &cam_ife_csid_680_cmn_reg_info,
 	.csi2_reg                             = &cam_ife_csid_680_csi2_reg_info,
-	.buf_done_irq_reg_info                =
-				    &cam_ife_csid_680_buf_done_irq_reg_info,
 	.path_reg[CAM_IFE_PIX_PATH_RES_IPP]   = &cam_ife_csid_680_ipp_reg_info,
 	.path_reg[CAM_IFE_PIX_PATH_RES_PPP]   = &cam_ife_csid_680_ppp_reg_info,
 	.path_reg[CAM_IFE_PIX_PATH_RES_RDI_0] = &cam_ife_csid_680_rdi_0_reg_info,

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid680_110.h

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #ifndef _CAM_IFE_CSID_680_110_H_
@@ -14,11 +15,20 @@
 #include "cam_irq_controller.h"
 
 static struct cam_ife_csid_ver2_reg_info cam_ife_csid_680_110_reg_info = {
-	.irq_reg_info                         = &cam_ife_csid_680_irq_reg_info,
+	.top_irq_reg_info      = &cam_ife_csid_680_top_irq_reg_info,
+	.rx_irq_reg_info       = &cam_ife_csid_680_rx_irq_reg_info,
+	.path_irq_reg_info     = {
+		&cam_ife_csid_680_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_RDI_0],
+		&cam_ife_csid_680_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_RDI_1],
+		&cam_ife_csid_680_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_RDI_2],
+		&cam_ife_csid_680_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_RDI_3],
+		&cam_ife_csid_680_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_RDI_4],
+		&cam_ife_csid_680_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_IPP],
+		&cam_ife_csid_680_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_PPP],
+	},
+	.buf_done_irq_reg_info = &cam_ife_csid_680_buf_done_irq_reg_info,
 	.cmn_reg                              = &cam_ife_csid_680_cmn_reg_info,
 	.csi2_reg                             = &cam_ife_csid_680_csi2_reg_info,
-	.buf_done_irq_reg_info                =
-				    &cam_ife_csid_680_buf_done_irq_reg_info,
 	.path_reg[CAM_IFE_PIX_PATH_RES_IPP]   = &cam_ife_csid_680_ipp_reg_info,
 	.path_reg[CAM_IFE_PIX_PATH_RES_PPP]   = &cam_ife_csid_680_ppp_reg_info,
 	.path_reg[CAM_IFE_PIX_PATH_RES_RDI_0] = &cam_ife_csid_680_rdi_0_reg_info,

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid780.h

@@ -339,15 +339,59 @@ static struct cam_irq_register_set cam_ife_csid_780_irq_reg_set[9] = {
 	},
 };
 
-static struct cam_irq_controller_reg_info cam_ife_csid_780_irq_reg_info = {
-	.num_registers = 9,
-	.irq_reg_set = cam_ife_csid_780_irq_reg_set,
+static struct cam_irq_controller_reg_info cam_ife_csid_780_top_irq_reg_info = {
+	.num_registers = 1,
+	.irq_reg_set = &cam_ife_csid_780_irq_reg_set[CAM_IFE_CSID_IRQ_REG_TOP],
 	.global_irq_cmd_offset = 0x00000014,
 	.global_clear_bitmask  = 0x00000001,
 	.global_set_bitmask    = 0x00000010,
 	.clear_all_bitmask     = 0xFFFFFFFF,
 };
 
+static struct cam_irq_controller_reg_info cam_ife_csid_780_rx_irq_reg_info = {
+	.num_registers = 1,
+	.irq_reg_set = &cam_ife_csid_780_irq_reg_set[CAM_IFE_CSID_IRQ_REG_RX],
+	.global_irq_cmd_offset = 0, /* intentionally set to zero */
+};
+
+static struct cam_irq_controller_reg_info cam_ife_csid_780_path_irq_reg_info[7] = {
+	{
+		.num_registers = 1,
+		.irq_reg_set = &cam_ife_csid_780_irq_reg_set[CAM_IFE_CSID_IRQ_REG_RDI_0],
+		.global_irq_cmd_offset = 0, /* intentionally set to zero */
+	},
+	{
+		.num_registers = 1,
+		.irq_reg_set = &cam_ife_csid_780_irq_reg_set[CAM_IFE_CSID_IRQ_REG_RDI_1],
+		.global_irq_cmd_offset = 0, /* intentionally set to zero */
+	},
+	{
+		.num_registers = 1,
+		.irq_reg_set = &cam_ife_csid_780_irq_reg_set[CAM_IFE_CSID_IRQ_REG_RDI_2],
+		.global_irq_cmd_offset = 0, /* intentionally set to zero */
+	},
+	{
+		.num_registers = 1,
+		.irq_reg_set = &cam_ife_csid_780_irq_reg_set[CAM_IFE_CSID_IRQ_REG_RDI_3],
+		.global_irq_cmd_offset = 0, /* intentionally set to zero */
+	},
+	{
+		.num_registers = 1,
+		.irq_reg_set = &cam_ife_csid_780_irq_reg_set[CAM_IFE_CSID_IRQ_REG_RDI_4],
+		.global_irq_cmd_offset = 0, /* intentionally set to zero */
+	},
+	{
+		.num_registers = 1,
+		.irq_reg_set = &cam_ife_csid_780_irq_reg_set[CAM_IFE_CSID_IRQ_REG_IPP],
+		.global_irq_cmd_offset = 0, /* intentionally set to zero */
+	},
+	{
+		.num_registers = 1,
+		.irq_reg_set = &cam_ife_csid_780_irq_reg_set[CAM_IFE_CSID_IRQ_REG_PPP],
+		.global_irq_cmd_offset = 0, /* intentionally set to zero */
+	},
+};
+
 static struct cam_irq_register_set cam_ife_csid_780_buf_done_irq_reg_set[1] = {
 	{
 		.mask_reg_offset   = 0x00000090,
@@ -1271,11 +1315,20 @@ static struct cam_ife_csid_ver2_top_reg_info
 };
 
 static struct cam_ife_csid_ver2_reg_info cam_ife_csid_780_reg_info = {
-	.irq_reg_info                         = &cam_ife_csid_780_irq_reg_info,
+	.top_irq_reg_info      = &cam_ife_csid_780_top_irq_reg_info,
+	.rx_irq_reg_info       = &cam_ife_csid_780_rx_irq_reg_info,
+	.path_irq_reg_info     = {
+		&cam_ife_csid_780_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_RDI_0],
+		&cam_ife_csid_780_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_RDI_1],
+		&cam_ife_csid_780_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_RDI_2],
+		&cam_ife_csid_780_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_RDI_3],
+		&cam_ife_csid_780_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_RDI_4],
+		&cam_ife_csid_780_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_IPP],
+		&cam_ife_csid_780_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_PPP],
+	},
+	.buf_done_irq_reg_info = &cam_ife_csid_780_buf_done_irq_reg_info,
 	.cmn_reg                              = &cam_ife_csid_780_cmn_reg_info,
 	.csi2_reg                             = &cam_ife_csid_780_csi2_reg_info,
-	.buf_done_irq_reg_info                =
-		&cam_ife_csid_780_buf_done_irq_reg_info,
 	.path_reg[CAM_IFE_PIX_PATH_RES_IPP]   = &cam_ife_csid_780_ipp_reg_info,
 	.path_reg[CAM_IFE_PIX_PATH_RES_PPP]   = &cam_ife_csid_780_ppp_reg_info,
 	.path_reg[CAM_IFE_PIX_PATH_RES_RDI_0] = &cam_ife_csid_780_rdi_0_reg_info,

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_common.h

@@ -382,6 +382,7 @@ struct cam_ife_csid_rx_cfg  {
 	uint32_t                        tpg_num_sel;
 	uint32_t                        mup;
 	uint32_t                        epd_supported;
+	uint32_t                        top_irq_handle;
 	uint32_t                        irq_handle;
 	uint32_t                        err_irq_handle;
 	bool                            dynamic_sensor_switch_en;

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_hw_ver2.h

@@ -76,8 +76,6 @@
 #define IFE_CSID_VER2_CUST_NODE_IDX_1                      0x2
 #define IFE_CSID_VER2_CUST_NODE_IDX_2                      0x4
 
-#define IFE_CSID_VER2_TOP_IRQ_STATUS_BUF_DONE                    BIT(13)
-
 enum cam_ife_csid_ver2_input_core_sel {
 	CAM_IFE_CSID_INPUT_CORE_SEL_NONE,
 	CAM_IFE_CSID_INPUT_CORE_SEL_INTERNAL,
@@ -114,7 +112,7 @@ struct cam_ife_csid_ver2_top_cfg {
 
 struct cam_ife_csid_ver2_evt_payload {
 	struct list_head            list;
-	uint32_t                    irq_reg_val[CAM_IFE_CSID_IRQ_REG_MAX];
+	uint32_t                    irq_reg_val;
 };
 
 /*
@@ -193,6 +191,7 @@ struct cam_ife_csid_ver2_path_cfg {
 	uint32_t                             qcfa_bin;
 	uint32_t                             hor_ver_bin;
 	uint32_t                             num_bytes_out;
+	uint32_t                             top_irq_handle;
 	uint32_t                             irq_handle;
 	uint32_t                             err_irq_handle;
 	uint32_t                             discard_irq_handle;
@@ -498,8 +497,11 @@ struct cam_ife_csid_ver2_common_reg_info {
 };
 
 struct cam_ife_csid_ver2_reg_info {
-	struct cam_irq_controller_reg_info               *irq_reg_info;
+	struct cam_irq_controller_reg_info               *top_irq_reg_info;
+	struct cam_irq_controller_reg_info               *rx_irq_reg_info;
 	struct cam_irq_controller_reg_info               *buf_done_irq_reg_info;
+	struct cam_irq_controller_reg_info               *path_irq_reg_info[
+		CAM_IFE_PIX_PATH_RES_MAX];
 	const struct cam_ife_csid_ver2_common_reg_info   *cmn_reg;
 	const struct cam_ife_csid_csi2_rx_reg_info       *csi2_reg;
 	const struct cam_ife_csid_ver2_path_reg_info     *path_reg[
@@ -572,7 +574,9 @@ struct cam_ife_csid_ver2_hw {
 	spinlock_t                             lock_state;
 	spinlock_t                             path_payload_lock;
 	spinlock_t                             rx_payload_lock;
-	void                                  *csid_irq_controller;
+	void                                  *top_irq_controller;
+	void                                  *rx_irq_controller;
+	void                                  *path_irq_controller[CAM_IFE_PIX_PATH_RES_MAX];
 	void                                  *buf_done_irq_controller;
 	struct cam_hw_intf                    *hw_intf;
 	struct cam_hw_info                    *hw_info;

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_lite680.h

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #ifndef _CAM_IFE_CSID_LITE_680_H_
@@ -291,15 +292,50 @@ static struct cam_irq_register_set cam_ife_csid_lite_680_irq_reg_set[7] = {
 	},
 };
 
-static struct cam_irq_controller_reg_info cam_ife_csid_lite_680_irq_reg_info = {
-	.num_registers = 7,
-	.irq_reg_set = cam_ife_csid_lite_680_irq_reg_set,
+static struct cam_irq_controller_reg_info cam_ife_csid_lite_680_top_irq_reg_info = {
+	.num_registers = 1,
+	.irq_reg_set = &cam_ife_csid_lite_680_irq_reg_set[CAM_IFE_CSID_IRQ_REG_TOP],
 	.global_irq_cmd_offset = 0x00000014,
-	.global_clear_bitmask  = 0x00000001,
 	.global_set_bitmask    = 0x00000010,
+	.global_clear_bitmask  = 0x00000001,
 	.clear_all_bitmask     = 0xFFFFFFFF,
 };
 
+static struct cam_irq_controller_reg_info cam_ife_csid_lite_680_rx_irq_reg_info = {
+	.num_registers = 1,
+	.irq_reg_set = &cam_ife_csid_lite_680_irq_reg_set[CAM_IFE_CSID_IRQ_REG_RX], /* RX */
+	.global_irq_cmd_offset = 0,
+};
+
+static struct cam_irq_controller_reg_info cam_ife_csid_lite_680_path_irq_reg_info[6] = {
+	{
+		.num_registers = 1,
+		.irq_reg_set = &cam_ife_csid_lite_680_irq_reg_set[CAM_IFE_CSID_IRQ_REG_RDI_0],
+		.global_irq_cmd_offset = 0,
+	},
+	{
+		.num_registers = 1,
+		.irq_reg_set = &cam_ife_csid_lite_680_irq_reg_set[CAM_IFE_CSID_IRQ_REG_RDI_1],
+		.global_irq_cmd_offset = 0,
+	},
+	{
+		.num_registers = 1,
+		.irq_reg_set = &cam_ife_csid_lite_680_irq_reg_set[CAM_IFE_CSID_IRQ_REG_RDI_2],
+		.global_irq_cmd_offset = 0,
+	},
+	{
+		.num_registers = 1,
+		.irq_reg_set = &cam_ife_csid_lite_680_irq_reg_set[CAM_IFE_CSID_IRQ_REG_RDI_3],
+		.global_irq_cmd_offset = 0,
+	},
+	{}, /* no RDI4 */
+	{
+		.num_registers = 1,
+		.irq_reg_set = &cam_ife_csid_lite_680_irq_reg_set[CAM_IFE_CSID_IRQ_REG_IPP],
+		.global_irq_cmd_offset = 0,
+	},
+};
+
 static struct cam_irq_register_set cam_ife_csid_lite_680_buf_done_irq_reg_set[1] = {
 	{
 		.mask_reg_offset   = 0x00000090,
@@ -312,7 +348,7 @@ static struct cam_irq_controller_reg_info
 	cam_ife_csid_lite_680_buf_done_irq_reg_info = {
 	.num_registers = 1,
 	.irq_reg_set = cam_ife_csid_lite_680_buf_done_irq_reg_set,
-	.global_irq_cmd_offset  = 0, /* intentionally set to zero */
+	.global_irq_cmd_offset = 0, /* intentionally set to zero */
 };
 
 static struct cam_ife_csid_ver2_common_reg_info
@@ -914,11 +950,19 @@ static struct cam_ife_csid_ver2_path_reg_info
 };
 
 static struct cam_ife_csid_ver2_reg_info cam_ife_csid_lite_680_reg_info = {
-	.irq_reg_info                         = &cam_ife_csid_lite_680_irq_reg_info,
+	.top_irq_reg_info      = &cam_ife_csid_lite_680_top_irq_reg_info,
+	.rx_irq_reg_info       = &cam_ife_csid_lite_680_rx_irq_reg_info,
+	.path_irq_reg_info     = {
+		&cam_ife_csid_lite_680_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_RDI_0],
+		&cam_ife_csid_lite_680_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_RDI_1],
+		&cam_ife_csid_lite_680_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_RDI_2],
+		&cam_ife_csid_lite_680_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_RDI_3],
+		NULL,
+		&cam_ife_csid_lite_680_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_IPP],
+		},
+	.buf_done_irq_reg_info = &cam_ife_csid_lite_680_buf_done_irq_reg_info,
 	.cmn_reg                              = &cam_ife_csid_lite_680_cmn_reg_info,
 	.csi2_reg                             = &cam_ife_csid_lite_680_csi2_reg_info,
-	.buf_done_irq_reg_info                =
-		&cam_ife_csid_lite_680_buf_done_irq_reg_info,
 	.path_reg[CAM_IFE_PIX_PATH_RES_IPP]   = &cam_ife_csid_lite_680_ipp_reg_info,
 	.path_reg[CAM_IFE_PIX_PATH_RES_PPP]   = NULL,
 	.path_reg[CAM_IFE_PIX_PATH_RES_RDI_0] = &cam_ife_csid_lite_680_rdi_0_reg_info,

drivers/cam_isp/isp_hw_mgr/isp_hw/ife_csid_hw/cam_ife_csid_lite780.h

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 /*
  * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
  */
 
 #ifndef _CAM_IFE_CSID_LITE_780_H_
@@ -322,15 +323,51 @@ static struct cam_irq_register_set cam_ife_csid_lite_780_irq_reg_set[7] = {
 	},
 };
 
-static struct cam_irq_controller_reg_info cam_ife_csid_lite_780_irq_reg_info = {
-	.num_registers = 7,
-	.irq_reg_set = cam_ife_csid_lite_780_irq_reg_set,
+static struct cam_irq_controller_reg_info cam_ife_csid_lite_780_top_irq_reg_info = {
+	.num_registers = 1,
+	.irq_reg_set = &cam_ife_csid_lite_780_irq_reg_set[CAM_IFE_CSID_IRQ_REG_TOP],
 	.global_irq_cmd_offset = 0x00000014,
-	.global_clear_bitmask  = 0x00000001,
 	.global_set_bitmask    = 0x00000010,
+	.global_clear_bitmask  = 0x00000001,
 	.clear_all_bitmask     = 0xFFFFFFFF,
 };
 
+static struct cam_irq_controller_reg_info cam_ife_csid_lite_780_rx_irq_reg_info = {
+	.num_registers = 1,
+	.irq_reg_set = &cam_ife_csid_lite_780_irq_reg_set[CAM_IFE_CSID_IRQ_REG_RX], /* RX */
+	.global_irq_cmd_offset = 0,
+};
+
+static struct cam_irq_controller_reg_info cam_ife_csid_lite_780_path_irq_reg_info[6] = {
+	{
+		.num_registers = 1,
+		.irq_reg_set = &cam_ife_csid_lite_780_irq_reg_set[CAM_IFE_CSID_IRQ_REG_RDI_0],
+		.global_irq_cmd_offset = 0,
+	},
+	{
+		.num_registers = 1,
+		.irq_reg_set = &cam_ife_csid_lite_780_irq_reg_set[CAM_IFE_CSID_IRQ_REG_RDI_1],
+		.global_irq_cmd_offset = 0,
+	},
+	{
+		.num_registers = 1,
+		.irq_reg_set = &cam_ife_csid_lite_780_irq_reg_set[CAM_IFE_CSID_IRQ_REG_RDI_2],
+		.global_irq_cmd_offset = 0,
+	},
+	{
+		.num_registers = 1,
+		.irq_reg_set = &cam_ife_csid_lite_780_irq_reg_set[CAM_IFE_CSID_IRQ_REG_RDI_3],
+		.global_irq_cmd_offset = 0,
+	},
+	{}, /* no RDI4 */
+	{
+		.num_registers = 1,
+		.irq_reg_set = &cam_ife_csid_lite_780_irq_reg_set[CAM_IFE_CSID_IRQ_REG_IPP],
+		.global_irq_cmd_offset = 0,
+	},
+};
+
+
 static struct cam_irq_register_set cam_ife_csid_lite_780_buf_done_irq_reg_set[1] = {
 	{
 		.mask_reg_offset   = 0x00000090,
@@ -943,7 +980,17 @@ static struct cam_ife_csid_ver2_path_reg_info
 };
 
 static struct cam_ife_csid_ver2_reg_info cam_ife_csid_lite_780_reg_info = {
-	.irq_reg_info          = &cam_ife_csid_lite_780_irq_reg_info,
+	.top_irq_reg_info      = &cam_ife_csid_lite_780_top_irq_reg_info,
+	.rx_irq_reg_info       = &cam_ife_csid_lite_780_rx_irq_reg_info,
+	.path_irq_reg_info     = {
+		&cam_ife_csid_lite_780_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_RDI_0],
+		&cam_ife_csid_lite_780_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_RDI_1],
+		&cam_ife_csid_lite_780_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_RDI_2],
+		&cam_ife_csid_lite_780_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_RDI_3],
+		NULL,
+		&cam_ife_csid_lite_780_path_irq_reg_info[CAM_IFE_PIX_PATH_RES_IPP],
+		},
+	.buf_done_irq_reg_info = &cam_ife_csid_lite_780_buf_done_irq_reg_info,
 	.cmn_reg               = &cam_ife_csid_lite_780_cmn_reg_info,
 	.csi2_reg              = &cam_ife_csid_lite_780_csi2_reg_info,
 	.buf_done_irq_reg_info = &cam_ife_csid_lite_780_buf_done_irq_reg_info,

drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_isp_hw.h

@@ -28,6 +28,9 @@
  */
 #define CAM_ISP_RES_NAME_LEN      16
 
+/* Access core_info of isp resource node */
+#define cam_isp_res_core_info(res) (((struct cam_hw_info *)res->hw_intf->hw_priv)->core_info)
+
 enum cam_isp_bw_control_action {
 	CAM_ISP_BW_CONTROL_EXCLUDE       = 0,
 	CAM_ISP_BW_CONTROL_INCLUDE       = 1