Add support for sw2rxdma_link_ring size cfg ini.
Also add wrapper function to get the sw2rxdma_link_ring size.
Change-Id: Ic5b17f029fe6c735785701801b75284dd489ac1e
CRs-Fixed: 3525040
Include Umac reset irq line in the mask table only
when it is enabled for 8 msi group to make sure
the legacy devices are not impacted.
Change-Id: If8f6b7f948a7c9f45247e8ff934642f0a532ff0d
CRs-Fixed: 3499500
add multiple history array to keep track of mem allocation and
deallocation for qref table.
Change-Id: I9fa97fbe5a5c36509cbb5a458851a152200318a5
CRs-Fixed: 3475981
Add new set and get APIs for cfg items so that
those cfg items can be managed from the external
components.
Change-Id: I52eb747fc6c544cfe43273c3b8b0fcc27b5a4a5f
CRs-Fixed: 3502582
As part of CPE V2 or split phy board, IPA will start using
two TX ring and for the same disable the DP interrupt mask
assignment.
Change-Id: Ia676bfa6a8b89274f5dfd313f73761132bb7909c
CRs-Fixed: 3445325
1. Add ini configuration for enabling round robin flows to
core distribution in FSE
2. Register FSE APIs to CDP FSE ops
Change-Id: Ic61c44eb9bc68a8c1a0116d4e6aa1d54cf489b62
CRs-Fixed: 3505287
ppe2tcl and Umac reset interrupts need dedicated irq lines.
Hence, group some of the existing dp groups togeather
to share MSI lines to make space for ppe2tcl and Umac reset
dedicated irqs.
Change-Id: I5181caeaeb4d0107b62e7ac812c2f829fd8215a2
CRs-Fixed: 3423553
This code helps to initialize and deinitialize new SOFTUMAC
based Rhine architecture.
Change-Id: I374140ccb3b31e9351c6e683c77d81a5a876472a
CRs-Fixed: 3382913
Support REO2SW ring pointer update threshold configuration,
it is helpful for PCIe utilization improvement.
timer based threshold - M: issue pointer updates when M micro
seconds has elapsed.
number based threshold - N: issue pointer updates when N entries
updates occur.
Change-Id: I49ed388520fd52e97e303d6ea9c04ced6cb5cf5f
CRs-Fixed: 3420101
Add support to enable/disable MLO Link Peer stats through
ini and cfg80211tool enable_ol stats command
Change-Id: Id1229a149befa416d060e1b07eee150e6b295abf
CRs-Fixed: 3397721
Enable or Disable PPEDS for specific
WLAN Soc.
usage:
add "ppeds_wifi_soc_cfg=0x02"
in /ini/global_i.ini to enable
PPEDS only for second WLAN SoC.
Change-Id: I65f138cf37298feac70e76b95c22507e58394618
CRs-Fixed: 3408439
Reuse the tx descriptors released in tx completions
without releasing the associated skbs to reduce
the cpu utilization in direct switch mode.
Change-Id: I4ab3ac58977a626344877b8a818a4dbc4864aaf3
CRs-Fixed: 3393968
Make DP changes for handling umac reset in QCA5332.
Changes are done to program msi_data value of the IPC interrupt to FW.
Change-Id: Ib6453755e191da655b87b528a7cef38a464f316b
CRs-Fixed: 3401146
If TX data is TCP ACK, configure TX flow index 3 in
SW2TCL data cmd ring descriptor.
Change-Id: Ibd08b13ba8f0481aa11cd9c3dc54a49cd73674fb
CRs-Fixed: 3368303
An INI dp_tx_spl_device_limit is defined and can be used to configure the
limit of TX descriptors that can reserved on the SOC to handle
special frames like EAPOL.
CRs-Fixed: 3343207
Change-Id: Ic84a11249880a3541749a72ac6d60df548f2bc5c
An INI dp_tx_spl_desc is defined and can be used to configure the
limit of TX descriptors that can reserved on the pdev to handle
special frames like EAPOL.
CRs-Fixed: 3343209
Change-Id: I6578bddd1f4ea07528c9f66f778b113ec6fb9e61
1. Change the names of parameters and functions related
to direct switch feature from ppe to ppeds
2. Remove the unused ppe_release_ring
Change-Id: I5a95b1273e338f354903af98158578ac65758a8a
CRs-Fixed: 3345097
The kernel-doc script identified a multitude of documentation issues
in the wlan_cfg folder, so fix them.
Change-Id: Id6bfb397608de6b858e448a867a3c21dffc9a178
CRs-Fixed: 3352408
Enable and register PPE2TCL and REO2PPE ring interrupts
for direct switch
Set interrupt timer threshold for ppe2tcl ring as 30 us.
Change-Id: Ida1ff6c3c2000f16f07960f7eae0d10edc337dc0
CRs-Fixed: 3341790
Add ini configuration to disable invalid decap type handling
during rx mon tlv processing. This is a temporary change for
debugging purpose and will be removed once HW issue is resolved.
Change-Id: I75eb53170833224ddd144baf1b1d8034f988dd3c
CRs-Fixed: 3308998
Add ini param "dp_disable_rx_buf_low_threshold" to disable
low threshold interrupts on regular rx refill ring. Default
it is enabled.
Change-Id: Ie471a4dc6862cbfe8b1eafe7c7d2ce2e0a7fcb7a
CRs-Fixed: 3313885
Update the prealloc size for RXDMA_BUF and REO_DST
rings using the ini values which have been configured.
Change-Id: Id47fbca3a79b37bba902d1b5bd0bf8c6073648cc
CRs-Fixed: 3283986
add debug prints and a custom timer for how long to wait to receive next
bk pressure event message.
Change-Id: I5a736b0f134cd179990de536da02967db3e39774
CRs-Fixed: 3273427
Add framework to use different RX hash values and ring masks
for ML and non-ML peers
Change-Id: I098cb50b8873eb137ce096011d01a5c21aaf854f
CRs-Fixed: 3269916
Currently in monitor mode for KIWI, interrupt for RXDMA2HOST is
enabled to process both monitor status srng and montior destination
srng, but low threshold interrupt for monitor status srng is also
enabled. so when available RX buffer in monitor status srng is less
then low threshold, it is possible that two kind of interrupt from
RXDMA2HOST ring and monitor status ring will call
dp_rx_mon_status_process_tlv() in different context and access to
mon_pdev->rx_status_q at the same time, this will lead to skb
double free issue.
solution:
(1) disable RXDMA2HOST srng interrupt in monitor mode.
(2) enable monitor status srng batch count interrupt for monitor
processing.
Change-Id: I1df8830cb7cc55468e5df5e49045c3d96f7c29a8
CRs-Fixed: 3245393
With KIWI_V2, wbm_ring_num for WBM2SW5 and WBM2SW6 have been changed
to 5 and 6. Hence properly update them in g_tcl_wbm_map_array. At the
same time, tx_ring_mask_msi and tx_ring_near_full_irq_mask are also
updated.
With IPA_OFFLOAD enabled soc->tcl_data_ring[0|1|2] is used by HOST
and the other two rings are allocated to IPA usage.
Change-Id: I4c13d0787e46be667c3a5a0ae624df8c2b2b354e
CRs-Fixed: 3229375
UMAC HW reset feature will be using the last interrupt context in each
DP interrupt combination i.e., on a system with more than 8 MSIs for DP,
UMAC HW reset will be assigned a dedicated interrupt context.
Add the necessary support for the same.
CRs-Fixed: 3163900
Change-Id: I26abd01e4261661ed95e1aa3cb2a774e78b50d9f
Increase the number of DP interrupts to 16. The interrupt assignment
table is updated to add new values for different MSI interrupts
available. 9, 10 and 11 MSIs configuration will take the same
configuration as that of 8 MSI. 13, 14 and 15 MSIs configuration
will take the same configuration as that of 12 MSI. New MSI assignment
configuration is introduced for 12 and 16 MSIs.
Change-Id: I82af75b21c793a62fc8f0bd5515e1160b601c0c2
CRs-Fixed: 3209397
