Support 8bit and 10bit bpp switch for display.
Change-Id: Ia5fcb330df95618596377773d0598be2b5609de1
Signed-off-by: Yahui Wang <quic_yahuiw@quicinc.com>
Disable CWB in quad pipe for quad LM CWB not supported
to avoid out of bound access.
Change-Id: I7e64cf132489401f91621ccde31cba68c8076d28
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
CPU qos_mask populated from devicetree can have defective cpu cores
included. This change identifies and replaces the defective cores
in the qos mask with the next possible working cpu cores.
Change-Id: Ie6bad11ff36f8e2486ef568b67b3fe024f9786c7
Signed-off-by: Andhavarapu Karthik <quic_kartkart@quicinc.com>
Remove the validation check that rejects the concurrency of
Expected Present Time update during modeswitch, as it is
expected to get an updated EPT value during the switch.
Change-Id: Ia94aedc4ea39b9c72fb0db17e91a09a77086563b
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Move Expected Preset Time delay from prepare_for_kickoff phase to
just before encoder kickoff. This will ensure the delay is done
towards the end of frame trigger and keeps minimal s/w programming
after the delay. This will help in cases where other unexpected
system delays occur, while coming out of sleep.
Change-Id: Ia04a9ab0455db8082b3f9f03d02db2cec5e17db5
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Sets DSI priority level to 7 before any commands are triggered.
This DSI priority setting is recommended by systems team as DSI
and Lutdma uses same Xin for fetch.
Change-Id: Ife6dee5ed51874818168d92728f76108495b8727
Signed-off-by: Rohith Iyer <quic_rohiiyer@quicinc.com>
Add a new clear_flush_mask ops in sde_hw_ctl_ops.
Flush mask update to cancel the fence error frame with
the new ops.
Change-Id: I8d03d8e83a05a652789fb38e885a3c8497e4d262
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
Fence error handling for wb and cwb retire fence.
Signal the retire fence for the fence error frame.
Change-Id: I0f73195c50edab4b8aefb58cea342214be87584c
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
Reset lut dma when fence error is seen to reset the already
submitted queue.
Change-Id: Iba9ab33a2e80bdaba6b1d4ccff086e3a46f8374d
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
Add framework for display submodules like PP, DSI, DP to register
for fence error and call the client callback funtion when fence
error occurs.
Change-Id: I70cc6b01907177e6c4238c4398fe2c085a000322
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
Sw fence error handling addresses following:
a. out of order handling
- For cmd panel, signal the release fence and retire fence once
sw fence error detected.
- For vid panel, signal the fence error frame release fence and
retire fence once sw fence error detected, hold the release
fence of last good frame till next good frame.
b. avoid BW decrease vote
c. lut dma reset
d. cancel kickoff
Change-Id: Ic496c532a26d80e0ef0074624ef6ace01c4ab2f0
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
Each rectangle is listed as an individual DRM plane, and since
they share a common VBIF register, there is no need to re
program the QOS remapper for the virtual plane.
Change-Id: I7af6aca1953cd61e622ef5b15353d5ea20fd73cd
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
Handle out of order dma fence signalling and propagation of fence
error. Out of order fence signaling is required only in Video mode.
For example, in case of N, N+1, N+2 frames where N, N+2 are good
frames and N+1 is frame with fence error. The release fence signal
sequence in video mode would be N+1, N, N+2.
Change-Id: I8b6f88cfeee945e28571b765f24ffea22fad23b8
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
Register callback function to hw fence driver and implement the
callback funtion.
As part of fence error handling, address out of ordering of HW
fences, SW override for release fence signal and handle BW voting
in both cmd and video mode.
Change-Id: I22902762b4cc09a5f5a20cf0dd01fc336a0f0cb4
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
Add a new property CRTC_PROP_HANDLE_FENCE_ERROR for userspace
to enable or disable fence error handling.
Change-Id: I72370f405c5299c603b0d673720c28a68c00807a
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
When IRQ HPD is simulated for DP MST, the driver updates the EDID in port context
for all the ports in an effort to refresh the context with the new port count.
But currently this operation is not synchronized with other debugfs operations
and also the edid read operations on the existing port. This can cause the
sim driver to update or delete the edid data while the edid data is being
read on an existing port, which would result in an edid read failure on the
DRM driver.
This change synchronizes these operations to avoid these race conditions.
Change-Id: I692af092583ed12b3da8c6587a74ec97d98fdfec
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
While clearing all blend stages, avoid writing blend config
registers for invalid dummy layer mixers introduced for dcwb.
These dummy mixers are SW only representation, these mixers
do not have respective blend config register space defined in HW.
Currently blend stage clear logic clears other undefined and
some valid registers like CTL_x_SW_RESET_OVERRIDE which is not
intended. This change limits accessing blend config registers
based on actual HW layer mixer count by ignoring dummy mixers.
Change-Id: I3a61fb6d5522b041fd6f10305b84dae449b4f2c7
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
In Current SDE driver, perf update check avoids bw update
in RSC state transitioning from CLOCK to SOLVER and updating
cached cur_perf bw values with out actual update to bus causes
bw update miss until usecase change trigger a new bw values
from client.
Below is the sequence of events in issue scenario.
-> wakeup frame from suspend, start with max bw voting and
framedone successful
-> RSC state updates to CLOCK state because of delay in next
incoming frame
-> Next frame perf update with paramschange, bw update is
skipped as new bw < cur bw and RSC is in CLOCK state
-> RSC updates SOLVER state after above step and commit is flushed
-> Bw update after frame is also avoided because RSC is in SOLVER
but cur_perf is updated with new bw value.
-> from next frame if bw is same as perevious frame, voting is skipped.
until change in bw values, vote of max bw in first frame is left.
This change fixes updating cur_perf values only when actual
bus update is intended.
Change-Id: If3ea4f178b94e9e59cd8ca563fa3510dffcc15a5
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
In non-qsync panels when min FPS is not published in DT,
the default min fps is set to 10 FPS. This change handles mode
switch cases, when panel FPS drops below 10 FPS by updating
min FPS to panel FPS for Expected Present Time calculations.
As part of the change, reduce 2ms from EPT to account for
scheduling delays after schedule_timeout.
Change-Id: Idc206f39adfb3517b4ea2cfa303fe53182a8e63e
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
The driver currently does not cache the current status of the aux switch
and calls the switch configure on any hpd event. So when there are
back to back disconnect notifications, it ends up calling switch
disconnect multiple times. But this is disrupting other operations
since the switch driver restores default settings on any call to
update settings.
This change caches the switch state and reconfigures it only on a
configuration change.
Change-Id: Ieeeaf5ac3bf8a7771b3118735422365cf2ee1f7b
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
Currently we are always doing command transfer cleanup which includes
disabling command engine, clocks, gdsc and unmasking overflow interrupt
as part of post command transfer function only after CMD DMA wait is
done. Cleanup should also be done if an ESD failure happens before
kickoff of a batch command. Organize code so that command transfer
cleanup can be done irrespective of whether command kickoff is done
or not.
Change-Id: Ieb92daa7f5da62c16c71f1b23ceff20adfbf3621
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
Reset number of bytes read from panel to the expected value when panel
sends more bytes than requested during DSI read. This can otherwise lead
to negative value of repeated bytes and array out of bounds access.
Change-Id: I9310c521a862108940142ba7c1a8c39838be0f79
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
This change checks if the mst panel is still valid before
accessing them when MST specific debugfs nodes are used.
Change-Id: I45f63009c1bff6a83e7af60a85f953674fef6797
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
Qsync ON/OFF commands have to be sent to the panel before connector
kickoff and sending them in the commit thread blocks it for few
millliseconds, and can lead to frame drops. Avoid this by sending
them asyncronously.
Change-Id: Ia7bc694871faf02b7c1a068b3d0ee7056c272506
Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com>
Update DP PHY tx drive level and pre-emphasis information
for mainlink training.
Move parameters from code to dtsi and add parameter parsing.
Change-Id: I7527327e39952d76184ea22adade7949c64d3734
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
Propagate error in case the number of active displays is greater
than 1, in dual display scenario to fail the validate.
Change-Id: I04250af8d7a6b0c290132abbaed2ed8e5e311a4f
Signed-off-by: Raviteja Tamatam <quic_travitej@quicinc.com>
From MSSS 10.x, the src_en bits needs to be set appropriately for
vid/cmd mode for getting the vsync timestamp. Program it based
on the new feature flag SDE_INTF_VSYNC_TS_SRC_EN.
Change-Id: Ia9c59d66afb436f082c7ebe6bf28e3953fde27a5
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Replaced lane swap register for lane swap in DSI controller.
Added check for where to perform lane swap based on DSI controller
version. Replaced function to parse device tree data for lane swap,
as previous function did not work.
Change-Id: I5e50a761b6ac0d2658ba73a5648e2f80f3470b96
Signed-off-by: Rohith Iyer <quic_rohiiyer@quicinc.com>
With DP plug-ins, it is possible for the connector fill modes API
to be called to update available modes on the connector and at the
same time have the commit thread calculate the max mode width
on the available modes. As a result, it is possible to access
pruned modes from the modelist.
This change moves the calculation into the fill modes call-flow,
so that the max mode width is determined once, and stored to be
used during virt enable.
Change-Id: I6c332c57e6e98ed98444a303add97d163a2031bf
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
This change updates the hw-fence QOS priority level.
Change-Id: I61e832f15d060cd563986dbd7135c00fce9dd5c9
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
Signed-off-by: Grace An <quic_gracan@quicinc.com>
