PLL codes from devicetree are only required if dynamic clock is enabled
for video mode panels. This change ensures that unnecessary error logs are
not seen for all other panels, by parsing the data only if the panel property
is set.
Change-Id: I206520aab65b7a5613909c8ff527e88303533617
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
This change avoids hardcoding the PLL_LOCKDET_RATE_1 register
value, rather using the variable with the same name that has
been initialized in dsi_pll_regs.
Change-Id: Ideb2c2b593156a4361feeb071df41f65e52c3beb
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
While recalculating VCO rate, currently the frac_bits value
is being hardcoded. The change instead uses the initialized
value from the 5nm PLL configuration.
Change-Id: I245574f4810a7b036d512ff1a347aa7e296702d1
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
The DMA buffer allocation for DSI happens during the first
command transfer. This change moves this allocation to happen during
bind.
Change-Id: I7969a019a8b84282e8a153f5393c9a3de5a28043
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
The change updates DSI DPHY and CPHY programming for
PHY version 4_3.
Change-Id: Id6b5cfefdce9530891e1e0f5a34814606954d843
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
The maximum value of backlight scaling property is enlarged
from 65535 to U32_MAX. Change supports DRE feature to
increase backlight level through backlight scaling property.
Change-Id: Ibe929308faf8c6f94bacbec7f58cc4ffe8133a85
Signed-off-by: Xu Yang <yangxu@codeaurora.org>
Change rounds up the calculated byte clock rate to the nearest
even number.
Change-Id: Iea6d3121343f1b2cb6d0a06cd47a84b050d55ac1
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Change updates the pclk divider calculation to ensure
more accurate pclk rate for DSI.
Change-Id: Iaf3a5b6e4b10ac751b3a80e2c3041ab8260b21e5
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
For DPHY, DSI byte clock is used to derive the byte interface clock through
a DIV_2 divider. While setting the rate for byte interface clock, if the byte
clock rate is odd the recalculation of byte interface clock will fail. This
can further lead to recalculation of byte clock and result in unexpected
value for byte clock. The change ensures that for DPHY, the byte clock rate is
always even to avoid such issues.
Change-Id: I0a0371af75e5819ed1283b52b4681e70f55d66e0
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
HW recommendation is to park the DSI byte clock and pixel clock at XO
before turning them off. The change parses XO from the DT and sets the
clock source as XO while turning off the PLL.
Change-Id: I788951d6341149300e80e8db4a5a3fd2c4eb3e03
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Change adds the new compatible version strings for DSI PHY and DSI CTRL
for waipio.
Change-Id: I1073034e608cace9d41cc04a9854f15f56828dfe
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Change removes the use of custom MSM DSI flags that will not be
available as part of GKI.2.0
Change-Id: I2337a54b1d6346ebdc18e9e6c3c8e7a07f421bdd
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Add Android make files and Kbuild files to support dlkm
for display driver. Also resolve header and config issues
to allow successful compilation of display driver.
Change-Id: I04d6233864ea54c0a808b295fbdccb83058f1fd2
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org>
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
Use of drm_display_mode vrefresh is being deprecated in
upstream DRM framework. Downstream driver need to use
drm_mode_vrefresh API from now on.
This change removes dependency on drm_display_mode vrefresh
and replaces it with drm_mode_vrefresh API in SDE, DSI and
DP driver. In addition, it also modifies drm_display_mode clock
to align with upstream approach where an uncompressed mode clock
is required to match drm_mode_vrefresh API.
Change-Id: Ie972a2e140adfd81c4e68df8e7bc69feaaca22e1
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
Update panel commands to support panel operating mode switch in
one timing node.
Change-Id: Ieb8303cebe78c699dfd5f274830418e87655ff56
Signed-off-by: Lei Chen <chenlei@codeaurora.org>
Expose panel mode from kernel to SDM with SDE connector property
CONNECTOR_PROP_MODE_INFO and set panel mode from SDM to kernel
with SDE connector property CONNECTOR_PROP_SET_PANEL_MODE for
avoiding private change in upstream code in QGKI kernel.
Change-Id: I0629dad9399967cc1118ac02ce30597076ca367d
Signed-off-by: Lei Chen <chenlei@codeaurora.org>
Change avoids clock framework APIs to configure the DSI PHY
PLL. It follows HW recommendation to set the byte and pclk
dividers.
Change-Id: I8c110f3997e4ec4c2eaa28778b70091855725ab8
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Move away from the private and private_flags fields from drm_mode,
as it is being deprecated in latest kernel version. Instead, Add
msm_display_mode as a wrapper to be used in downstream to store these
parameters. Also, store msm_mode in connector_state to be accessed
in commit path.
Change-Id: Ia5bdebe75f00aa15fb7db4dc3a0d50c30894a95c
Signed-off-by: Orion Brody <obrody@codeaurora.org>
This change replaces kzfree with kfree as kzfree has been
renamed.
While moving to the latest 5.10 tip, additional small changes
were required to resolve compilation issues:
set_dma_ops has moved from dma-mapping to dma-map-ops header.
This change includes the new header file required.
drm_panel_add returns void, this change removes the expected
return value check.
drm_prime_pages_to_sg takes an additional parameter. This change
passes in the drm_device pointer the function is looking for.
Remove an unused variable in sde_crtc vblank function.
Change-Id: I47c085c0cb64432873c2e750ae64cbdc2b5340da
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
This change adds DRM_MODE_SEAMLESS to private flags downstream,
as it was deprecated from drm UAPI. Additionally, this will
update the is_mode_seamless function to access the seamless
flag from private flags.
Change-Id: Idea0b4ac8e71063c000f582d3228bc0a50a6a8e6
Signed-off-by: orion brody <obrody@codeaurora.org>
Commit 62afb4ad425a ("drm/connector: Allow max possible encoders
to attach to a connector") enables additional encoders per
connector through use of a mask rather than encoder ids.
This change updates the driver when looking for an encoder
for the connector to look through the list of all possible encoders.
Change-Id: I69cc7c38cd0a9842ed2f15712feeb3c6b88daadf
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
Commit 2b07021a940c ("debugfs: remove return value
of debugfs_create_u32()") removes the return value
from debugfs_create_u32. This change updates the msm
driver to remove cehcks on this return and corrects
for unnecessary line wraps.
Change-Id: I8d50dd7168921edfb2d5edad13941f91117d3c30
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
Commit a25b988ff83f ("drm/bridge: Extend bridge API to
disable connector creation") and commit ee68c743f8d0 ("drm: Stop
including drm_bridge.h from drm_crtc.h) add additional input flags.
This change adds fixes to the drm bridge attach API and includes
relevant drm_bridge header files.
Change-Id: I85e84eaff7df2995243896108a217fae81716b63
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
Commit 6dbe0c4b0fc0 ("drm/panel: Initialise panel dev and funcs
through drm_panel_init()") and commit ba2fad4c9648 ("drm/panel:
Add and fill drm_panel type field") modify input parameters for
drm_panel_init. This change updates the relevant changes to the
dsi driver by passing in the device and panel type.
Change-Id: I76a271fea08190bd8633831442ca48882f8a97e6
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
Commit 05193dc38197 ("drm/bridge: Make the bridge chain
a double-linked list") creates a bridge chain linked
list. This change updates the relevant changes to msm
driver to use the list to find the bridge associated to
the encoder.
Change-Id: I59eb2910be96f4fff7bdbeb040d6ad204c41d747
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
Commit 12c683e12cd8 ("drm: bridge: Pass drm_display_info to
drm_bridge_funcs .mode_valid()") passes the drm_display_info to
mode valid. This change updates relevant changes to dsi display,
that will make it available during bridge validation.
Change-Id: I2772e9e3920de940f22341be5019213d562352ff
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
This change moves the backlight update operation from
drm bridge enable to connector post kickoff.
When timing engine is enabled with programmable fetch
enabled, the timing engine will start counting from
the prog_fetch_start point (which is somewhere in VFP).
It’s a grey area from that point to the actual panel
vsync and SW should not trigger DMA command during that
time.
During display resume, sometimes the INTF timing engine
do not get enabled completely at the first vblank irq.
The backlight update cmd transfer trigger as part of the
drm bridge enable can also take place at the same time,
that may cause DSI cmd transfer failure.
Change-Id: I2722d3c23012ef0e7bcc7f728ec5658318ce4e60
Signed-off-by: Rajeev Nandan <rajeevny@codeaurora.org>
This change enables the DMA CMD scheduling as default for
video mode panels.
In video mode panel, if the DMA is triggered very close to
the beginning of the active window and the DMA transfer
happens in the last line of VBP, then the HW state will
stay in ‘wait’ and return to ‘idle’ in the first line of VFP.
But somewhere in the middle of the active window, if SW
disables DSI command mode engine while the HW is still
waiting and re-enable after timing engine is OFF. So the
HW never ‘sees’ another vblank line and hence it gets
stuck in the ‘wait’ state.
Scheduling the DMA cmd to the first line in VFP fixes
this issue.
Change-Id: If9e5bd1923c012f10dee50c791a2b2b001d97553
Signed-off-by: Rajeev Nandan <rajeevny@codeaurora.org>
Add support for 5nm DSI PLL C-PHY shadow clocks, which
will be used during dynamic dsi clock switch.
Change-Id: I55b11f2d0cffd8494d4641e9b2de0b88e7229978
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
As per the HW requirements it is highly recommended to use DMA start
window to trigger broadcast commands. If not used then it can
result in a hardware hang with the DSI controllers going out
of sync. This behavior is even more prominent in cases of higher
refresh rates. As part of the change we change the default DMA
scheduling behavior to default to maximum possible DMA window
in case it is not specified in the panel device tree.
Change-Id: Ied4df9063664cedbc18ce009054d4e5ecae30ab2
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
