When switching between 2 dongles/adapters it is possible
to have the same resolution with different link configuration.
Even though the pixel clock could be the same on replug, the
vco clock could be different depending on the link
configuration. Since the dp driver only exposes limited clocks
to the clock framework, in this specific scenario, the clock
driver is unable to recognize the change in source clock rate
and ends up skipping the clock reconfiguration.
This change adds support to park the pixel clocks on disable,
thereby forcing a reconfiguration on subsequent replug even
if the pixel clocks are the same.
Change-Id: If90b37d6285f6cad23cf1c11a7d6ccd6b4cf850c
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
The divider value for vco clock is only dependent on the link rate
and is known during pll configure. Instead of depending on the
clock framework to program this divider as part of stream clock
enable, this change moves the configuration to pll configuration
and removes the set rate call on the vco clock.
Change-Id: If687a8ab057fdfd6c3b3ad2bd1c51663d9182ff4
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
Disable vsync counter before single buffer tear check
update. It allows to trigger the resolution switch
frame as posted start frame.
Change-Id: I2726372fd0e6d14ab0f79e3e3b0731a074158682
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
On an MST unplug, the MST topology manager state needs to be cleared
so it can properly destroy the current topology. But since the mst
active state is cleared prematurely in the driver, this call is
skipped and on a subsequent plug-in, the topology manager ends up
using stale topology from previous configuration. Incorrect RAD
values are used for sideband, causing them to fail.
This change fixes the order of operations, so the topology manager
state is properly updated on unplug. It also removes a duplicate
hpd notification to usermode.
Change-Id: Idcff17be113a361a0b58e54d85957f30d1d4e2d6
Signed-off-by: Sandeep Gangadharaiah <sandgang@codeaurora.org>
Move thread priority call to kernel worker thread because
component bind API may run from vendor_modeprobe process
context when all drivers probe succeed. Thread priority
update is not allowed from vendor_modeprobe process
context.
Change-Id: Iafac97ce02942d6a2134495232f3c395ba4a362f
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Currently the bit clk rate is overridden by cached clock rate
even in dynamic clock disabled usecase where it is not configured.
Avoid this override by retaining calculated bit clock rate for respective
mode in such usecase.
Change-Id: Ib159219fd50ab977edb8332c83bc8b34aee2dc0f
Signed-off-by: Shashank Babu Chinta Venkata <sbchin@codeaurora.org>
On reclaim error, mem handle is still valid and reclaim
should be retried on next commit. This change keeps the
mem_handle valid.
Change-Id: Ie3e0cc3d37c7f1f260a7655f48a6aadece65a1ca
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
Alter allocation method from kzalloc to kvzalloc since virtually
contiguous allocation should suffice requirement. This will avoid
unnecessary invocation of OOO handlers.
Change-Id: I8291ddae08f6427478cdd9b88d6148e02d7ab002
Signed-off-by: Shashank Babu Chinta Venkata <sbchin@codeaurora.org>
When validating panel resource, no need to check reset gpio if using
ext bridge mode.
Change-Id: Id0df84b9e0d8b10f4dd6851d5b3ab31b220f8622
Signed-off-by: Yu Wu <zwy@codeaurora.org>
Commit b67da33a6307 ("trigger tx_wait if panel
resolution switch") increases the mode switch latency.
Alternatively, single buffer tear check registers can be
updated when vsync_in is disabled. It allows mode switch
frame trigger as posted start frame trigger.
Change-Id: I8068736b2ea01f6e4160e765fc39d7fc2a8590c9
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Wait for asynchronous DSI DCS command transfers to complete
before disabling DSI interrupts during pre-release. This is
required to resolve a race condition where dsi worker threads
can trigger HW access while a VM lend/release is occurring on
the CRTC commit thread.
Change-Id: Ia1f153a2cd008c617dba274473e7678b01a38d29
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
The ROI commands are sent with an asynchronous command transfer wait.
If the queued CMD DMA wait for done gets scheduled before the DSI
controller timing engine programming, the later will be blocked waiting
on the ctrl_lock, which was acquired by the queued DMA wait for done work.
This effectively negates any advantage of having the async wait flag for
ROI commands blocking the main commit thread.
The change swaps this order to ensure that such a scenario never happens.
Change-Id: I8a971c0c7733eea3d435b637ca41b34fa60adfc1
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
During display encoder disable, reset the dsc control
mux configuration during null commit to ensure dsc hw
blocks are cleanly freed up.
Change-Id: I02e2f074450e4d7b49dc8fec14777f380786c63e
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
While hw resources allocation for an active display during modeset, avoid
dsc hw allocation switch by finding which dsc encoders are allocated
previously and allocate same dsc hw encoders. This helps in fixing underrun
issues in below scenario of dual display power ON/OFF.
Use case: Dual DSI display setup, both are DSC enabled, primary in video mode.
--> when both displays are in powered off, all hw block are free.
--> enable second dsi display
Since LM 0/1 marked for primary, LM 2/3 allocated along with DSC 0/1
--> enable primary display
LM 0/1 allocated with DSC 2/3 encoders
--> Now power off secondary DSI
DSC 0/1 are freed up
--> Immediate modeset on primary, DSC allocation switched
LM 0/1 and DSC 0/1 allocated. DSC 2/3 are freed up as per RM but
decoupling DSC 2/3 blocks with respective pingpong or intf is not done.
This is causing underruns on primary.
Tracking which DSC blocks are freed during resource switch and programming the
respective DSC control mux configuration is not feasible and not scalable as
any other display can allocate those blocks and would require synchronizing
across display threads. So approach taken is avoid dsc resource switch itself.
Change-Id: I7f740722a52266740c4b168edc0c619e3cf68989
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
Adjust pll pclk rate to support non 1/1 dispcc MND
divider values by updating pclk div calculation.
Change-Id: I1972b536a109b97978e843f046b1db4ad6813a51
Signed-off-by: Srihitha Tangudu <tangudu@codeaurora.org>
Add new properties to support dynamically turning on and off digital
dimming and setting new minimum backlight.
Change-Id: I3b94190877d556768ba2c92ec59432dec44de0de
Signed-off-by: Ping Li <pingli@codeaurora.org>
Trigger tx_wait if command mode panel resolution
switches during mode switch to avoid early single buffer
tear check programming.
Change-Id: Ib747df8250c714248a44b596c2c8aeef006ea4fc
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
The parser is throwing warning for missing properties in device
tree, which might not be present in all variants. This warning
can be ignored and is downgraded as a debug log.
Change-Id: I1b3f6e9e3d21a0a84585ace4eba15710464d7b51
Signed-off-by: Sandeep Gangadharaiah <sandgang@codeaurora.org>
This change clear cached ROIs when rounded corner feature is
disabled to ensure full frame ROI for first frame when feature
is enabled again. This change depends on HAL change to disable PU
for one frame when RC mask config is set.
Change-Id: I4c48ccd3f64409d1b0fa19f0e6f92eab5f86d099
Signed-off-by: Anjaneya Prasad Musunuri <aprasad@codeaurora.org>
Userspace module may not trigger the atomic check and it
can cause the commit failure. In such case, always reserve
the minimum core clock rate on mmrm module for built-in
displays to avoid the power ON failure.
Change-Id: Iafd92a7b7d1b35befe70b041cbedaec2add40de4
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Reorder registration of various display drivers in the order of
dependency.
Change-Id: Idfa0616d3133f3b03c713e3c15a4fd3956ec2594
Signed-off-by: Shashank Babu Chinta Venkata <sbchin@codeaurora.org>
If an external display, such as DP, requests for the available
resources, resource manager (RM) will provide a count of all unused
mixers. If the primary/secondary display(s) are not active, the RM
will report the associated preferred mixers as free resources.
However, RM will not allow preferred mixers to be allocated to other
displays. DP driver could look at these available resources and assume
a high resolution mode is possible and fail during resource allocation.
This change updates the available resources info API to account for
primary/secondary preferences while exposing available resources.
Change-Id: I134a1047f24ac9f1fcee695aa14a1d3e43c1571f
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
MDSS INTF HW block does not generate vsync if controller
turns off the link clock prematurely. This leads to
frame trigger timeout and SDE driver triggers the retire
fence after 84ms to recover gracefully. A client may switch
source pipe from one CTL path to another CTL path based
on delayed retire fence. It can lead to other ctl path
hang. This can be resolved by resetting the lm blend
stages for each missing vsync frame trigger.
Change-Id: I5a6ed03afbdad83d8fd6decc593d39e04bef62e4
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
Commit Ie972a2e140adfd81c4e68df8e7bc69feaaca22e1 updated the dp
driver to extract the drm mode clock from timing parameters
instead of using the clock value provided by EDID to align the
behavior with DSI driver. But this results in incorrect clock
value if the refresh rate is not an integer value. For rates
such as 59.94 or 29.97, the calculated mode clock value would
be different from what is stipulated by EDID. This change
reverts the mode clock calculation to use the clock value
from EDID.
Change-Id: I3e192ef09d2456fbb1d22a0bf9474ac25ba86c72
Signed-off-by: Sandeep Gangadharaiah <sandgang@codeaurora.org>
Noise and attenuation layers are full screen layers. Top left coordinates
are not cleared in some use cases when same blend stage is assigned to
noise and attenuation layers. This change sets top left coordinates of noise
and attenuation layers.
Change-Id: I6af7a38d011d0bb642dc3d8a4aff338075524906
Signed-off-by: Anjaneya Prasad Musunuri <aprasad@codeaurora.org>
Power on reset value of DPTX_CONFIGURATION_CTRL.ASSR (alternate scrambler
seed reset) is high. Which will cause link training 2 to fail with TPS4 pattern.
Change disables this before link training starts.
Change-Id: Iee95de04625658254b242afdcbba6db24a52606d
Signed-off-by: Vara Reddy <varar@codeaurora.org>
DP driver is requesting USB to release SS lanes very early
during bootup even before USB has fully initialized. As a
result USB driver is returning -11 which will abort DP state
machine. This change will allow DP driver to retry USB request
whenever this error code is received.
Change-Id: I144d16ef4b07016569ba9c04df15610fe3b5e6fc
Signed-off-by: Sandeep Gangadharaiah <sandgang@codeaurora.org>
