Current implementation of hal_srng_access_start() reads the ring pointer
in the same byte-order as it is written by the target. This results in
byte-order mismatch on a big-endian Host because the WLAN target is
little-endian based. For most of the srngs, the target already takes of
this by converting the ring pointer to the host-order before writing to the
DDR. But for other srngs, the Host needs to handle the endianness
conversions. Add HAL APIs to do the same.
CRs-Fixed: 2844519
Change-Id: Ieb47391ac0acc3724e854f433915dd5b1219bebe
Use cache invalidate api instead of cache_sync since
cache_sync api is not available in MIPS platform.
Change-Id: I4b8e2fc3cb9055d1c392c2f6dbe7d6be7c66031b
Change the alternate indication_0 to WBM instead of
REO2TCL. This is done such that, WBM takes care of
the of the de-linking of the link descriptors and
release the buffers to the respective WBM rings.
WBM should take care of the NULL entries if present
in link descriptor as WBM internal errors.
Change-Id: Ie084e54861bb4611a45cd724bb32d211c62f4f21
Excessive logging is detected when force wake request
command fails.
Rate limit the logs in hif_force_wake_request and
hal_write32_mb.
Change-Id: I9b1166074dfdb2d58d811571c802a75a6dbc03c5
CRs-Fixed: 2823961
Add reo ring descrptor swap in case of big endian platform.
Convert msi_data into little endian format before writing into
MSI_DATA register. Also change into little endian format while accessing
the shared LMAC registers.
Change-Id: I07f4ae4e6df4608201b63d325c2cbc37436d1592
REO remap register direct writes as part of SAP stop could
result in a NOC error if the UMAC is in low power state.
Fix is to use shadow register writes for REO remap and
WBM HP registers.
Change-Id: Ie515c3d28f4ccdd99a3757808f1ab6c5cf373e3d
CRs-Fixed: 2813105
Currently, we decrement active_work_cnt in a while loop in delayed
register worker and later on make a "allow_l1" call to enable L1ss.
The bus suspend routine depends on the value of active_work_cnt to
determine if any register writes are pending. In case there are, bus
suspend is rejected.
As a result its possible that when bus suspend happens, the
delayed worker while processing the last remaining enqueued
write, makes the active_work_cnt to 0. This will allow the bus suspend
routine to continue to disable the bus, even before the
delayed-reg-worker has called allow_l1 and run to completion. This may
lead to a NOC error while calling "allow_l1" API from
delayed-reg-worker.
Hence, move the decrement of active_work_cnt to the very end in
hal_reg_write_work function.
Change-Id: Iec602f97c953df1c6a018310fd02ab458547ce3a
CRs-fixed: 2813733
Due to recent FW changes not filtering out BAR frames, redirect these
frames to REO exception ring and handle as normal data packets.
Change-Id: I4540929fddab14de57a23f6364fc916a70057cbe
CRs-Fixed: 2795499
This change fixed compilation error about implicit-fallthrough and
pointer to in cast.
Change-Id: Iea2c25d97d8a039ed0f8083078427a8f8de70cd1
CRs-Fixed: 2814658
Delayed register write work needs to be flushed before bus suspend to
make sure there are on pending writes after driver's bus suspend routine
exits. In case delayed work context is not able to finish before the bus
(PCI) is suspended (DRV), it may lead to a NOC error.
Change-Id: I40cbcec5d23ddd75ec87aed69ac45d95510fa880
CRs-Fixed: 2813733
Get reo destination indication from REO2SW ring descriptor,
store it to qdf_nbuf_cb of skb.
Change-Id: I5a4c504b2550229a77a435b1f5ddb78c4abe51aa
CRs-Fixed: 2809080
Add apis to map generic registers to shadow region. Existing
logic includes mapping only srng based regs to the shadow
region.
Add support to map REO control regs and WBM2SW2 rel
ring HP reg address to the shadow region in case the direct
reg writes in IPA enable/disable autonomy fail due to UMAC
block being in a power collapsed state.
Shadow reg mapping for these regs is provided to FW during
init. Add stat shadow_reg_write_fail to track shadow reg
write failure and shadow_reg_write_succ to track successful
shadow writes.
Change-Id: I04790765a3de80047689657e2cad0b73123440b9
CRs-Fixed: 2790321
In IPQ501x/QCN9100, the REO fragement destination ring
has moved from the REO GENERAL register to REO MISCELLANEOUS
register. Changes are added int HAL_REO_R0_CONFIG to set
the fragmentaion destination value for IPQ501x/QCN9100.
Change-Id: I868dd0ac5c24217f9778ab9da5c2a3d98d3ea302
Add hal_rx_msdu_get_reo_destination_indication API for QCA6750
target. Add NULL check to avoid possible null pointer dereference
for targets API is not supported.
Change-Id: I2c78e16a6796b0b09834cb91749244357f3de753
CRs-Fixed: 2793284
If frames from the same FISA flow goes into different REO2SW rings, it
will result in an unexpected FISA behavior. This can happen if the
frames have been reinjected from FW offload module since FW will select
REO2SW1 ring. If the same flow frames hash to other REO2SW rings, then
the same flow UDP frames will do to different rings.
Reo_destination_indication of 6 indicates if the frame has been
reinjected from FW. If so, then continue to deliver the packet without
FISA.
Change-Id: I14a17a10d04909adfb30557d58beb1610e59bf70
CRs-Fixed: 2790292
HW flow search table memory is not initialized to
zero due to incorrect argument order to qdf_mem_set.
This results in the possibility of HW flow entry
to be not configured properly even though SW flow
entry is configured properly.
Fix is to use the appropriate argument order to
qdf_mem_set so that HW FST memory is initialized
to zero.
Change-Id: If24f50c507392bd8d4974232d48d3af6f4f29b43
CRs-Fixed: 2773951
Reserve 128 bytes headroom for monitor status buffer
to accomadate feature specific radiotap header or any other info
in the headroom.
CRs-Fixed: 2775118
Change-Id: I2b1aba26e565b58c48a2e24ad17965aacd6b4526
Adding write/read APIs for accessing the CMEM.
Currently in QCA6750, UMAC and CE windows are statically mapped,
a new static window for CMEM is added for CMEM transactions.
Change-Id: Ie10b33a6f468c6e4db314ea85856414962ef29e3
CRs-Fixed: 2771193
If reo_dst_ctrl register writing failed, this is a fatal error for
IPA pipe going to down case as RX frames will still be routed to
IPA rings then hit NOC error. retry register writing to see any
chance to write successfully, if fail always, trigger SSR or panic.
Change-Id: I3c03faa28e6cc93f396944579a360d5405c8138e
CRs-Fixed: 2774789
The logging macros implicitly takes care of embedding function name
in the log, hence there is no need to include __func__ again.
Getting rid of redundant __func__ reduces driver memory footprint.
Change-Id: I6b5beea990e78486e1e5aab5a8df5fc2f1e5ab51
CRs-Fixed: 2774457
MSDU count is not reliable in all cases.Hence it is better
to check whether next_link_desc is valid or not and then
free the MSDUs in the next descriptor and subsequently
release both the current and next link descriptor back to HW.
Change-Id: Ie5ea3be547f9aed6673293221f6b47661cd92cce
STATUS_BUFFER_DONE tlv written in first word for a status
buffer indicates that DMA is done for that status ring entry.
In existing implementation, for a status ring entry if
STATUS_BUFFER_DONE tlv is not written by HW, we poll on to status ring
entry until DMA is done by HW.
During lmac reset it may happnen that HW will not write STATUS_BUFFER_DONE
tlv in status buffer, in that case we end up polling infinitely leading
to backpressure on monitor status ring.
As per MAC team's suggestion, when HP + 1 entry is peeked and if DMA
is not done and if HP + 2 entry's DMA done is set,
replenish HP + 1 entry and start processing in next interrupt.
If HP + 2 entry's DMA done is not set,
poll onto HP + 1 entry DMA done to be set.
CRs-Fixed: 2740988
Change-Id: Ieef667f0bb4a47e74fc320c93243c637409f47f0
HAL changes to fetch cfr information from
PHYRX_PPDU_END_TLV & RXPCU_PPDU_END TLV
Change-Id: I5817fdc5d17ebea3f2376b7bef9e58981198d1ec
CRs-Fixed: 2752943
Memory optimization of monitor status ring by allocating buffers during
replenish using alloc_skb (linux API).
It creates buffer of required size rather than 4k size(dev_alloc_skb)
Change-Id: I3ae5e403de28c4570f8ac3b50d3ca878a9e4b2f9
CRs-Fixed: 2733931
When matching ppdu_id is detected during HAL processing, then print the
error message instead of going for assert.
Change-Id: I8f58359a66fbeaf2ebc98477f65bab446c0a784b
CRs-Fixed: 2747953
In monitor mode, radiotap header contains VHT/HE information in management
and control frames after association of STA to AP.For this,reset of
ppdu_info is required before processing of ppdu in order to avoid reuse
of ppdu_info.
Change-Id: Ia36ec2664f79d645ff76db016f986dfb92ec8bbd
CRs-Fixed: 2734804
In QC9000, the channel capture status gets update in reserved_8
field's lower 2 bits only. Remaining bits are used for debug.
CRs-Fixed: 2740908
Change-Id: I97321addb18f8e5944f5f58d670dfa9858dca4ec
Before accessing any register on chip 6750, check if target is
ready or not.
Do not allow register access if target is not ready.
Change-Id: I41a604d04e861c97bdd676998222ccecbf12fd5a
CRs-Fixed: 2688920
On returning the msdu link descriptor to HW via WBM
release ring, the rx exception ring contents are not
zeroed. This could result in host reading stale ring
descriptor content in the scenario when HP is updated
even before the latest values are reflected in the ring
descriptor.
Fix is to set invalid bit in cookie for exception ring
descriptor and add cookie sanity check.
Change-Id: I01a294c92b260ebe8e584ef20e9550b1febec913
CRs-Fixed: 2730759
When an AP operates on a 6G channel. The channel frequency in the
radiotap header, in the beacon frame, shows an incorrect 6G frequency.
This is because, the function hal_rx_radiotap_num_to_freq is not updated
to handle the 6G channelization spec update ( IEEE 802.11 11AX Draft 6.1).
To fix this issue, update the function hal_rx_radiotap_num_to_freq to
handle the 6G channelization spec update (increase the 6G frequencies by
an offset of 10MHz).
Change-Id: I342dcb46b2627b3a2c3f12524077e63d811a5feb
CRs-Fixed: 2733367
For MCC, hash key related member in struct hal_rx_fst is not used,
it requires big chunk memory > 40K bytes that sometimes may fail to
allocate from system, wlan start up failed.
Remove hash key related member in hal_rx_fst by macro
WLAN_SUPPORT_RX_FISA for MCC.
Change-Id: I4214e18155c3ebc3dcc800c8c74f7eed16d580b4
CRs-Fixed: 2732990
Make sure to drop the raw Rx frames as both driver and stack
are not expected to handle them.
Add counter for invalid fisa flow_idx packet received.
Change-Id: I5107c554b8ce6a9a7973f2aeca44bb0f360dc2df
CRs-Fixed: 2733981
Currently all the rx ring descriptor contents are left
intact even after these entries are processed. This can,
at times, lead to stale entries being processed, if the
head pointer of any ring is updated before the updated
contents of the ring descriptor gets reflected in the memory.
This can lead to scenarios where the host driver reads a
stale value of sw_cookie, and free/unmap a currently in-use
buffer, thereby leading to the hardware accessing unmapped
memory region.
The sw_cookie is the integral part of al the rx ring
processing. Hence we always mark the sw_cookie as invalid
after dequeuing an entry from the REO2SW ring. Every time
we check for the validity of the sw_cookie before we try to
process an entry from REO2SW ring. if the invalid bit in the
sw_cookie is set, we just skip this entry and move on to the
next entry in the ring.
Change-Id: I0e78fa662b8ba33e64687a4dee4d1a5875ddb4bf
CRs-Fixed: 2730718
Remove uncessary msdu count check against msdu count in
mpdu desc info while processing REO Rx err pkts.
As per h/w team msdu count can be obtained from msdu link
desc instead of mpdu desc info.
SOC level Rx err stat rx.err.msdu_count_mismatch is
incremented to log this condition.
Change-Id: I4f7d2df7335778f2f2d28e542da17fc7f6970009
CRs-Fixed: 2729693
Rxdma decrypt errors are observed when the association
is in progress as AP sends encrypted data packets to
DUT-STA. As part of the rxdma error handling, excessive
prints are logged to console resulting in an assert.
Fix is to rate limit rxdma decrypt error related log
Change-Id: I2ef28c635d77e3acafd067b921cdb13c277756c7
CRs-Fixed: 2725335
Adding support for enabling ini config to remap reo destination rings
for HK v1, HK v2, maple and pine platforms.
Change-Id: Id9d304521f32497e3acd845ddd2973b96b641516
After enabling FISA, getting compilation issue in WHUNT due to
-Werror=maybe-uninitialized.
Fix this issue by initializing the uninitialized variables.
Change-Id: I4bdb76ba445630fb09df440f587291f0c3e382ec
CRs-Fixed: 2717632
