Commit Graph

2541 Commits

Author SHA1 Message Date
Sandeep Gangadharaiah
d3d3794b51 disp: msm: dp: destroy mst topology on unplug
On an MST unplug, the MST topology manager state needs to be cleared
so it can properly destroy the current topology. But since the mst
active state is cleared prematurely in the driver, this call is
skipped and on a subsequent plug-in, the topology manager ends up
using stale topology from previous configuration. Incorrect RAD 
values are used for sideband, causing them to fail.

This change fixes the order of operations, so the topology manager
state is properly updated on unplug. It also removes a duplicate
hpd notification to usermode.

Change-Id: Idcff17be113a361a0b58e54d85957f30d1d4e2d6
Signed-off-by: Sandeep Gangadharaiah <sandgang@codeaurora.org>
2021-10-15 10:02:01 -04:00
qctecmdr
5f5c61faa0 Merge "disp: msm: dsi: reorder DSI registration" 2021-09-29 02:10:57 -07:00
qctecmdr
f96c6ed42d Merge "disp: msm: dp: set drm mode clock same as clock value from EDID" 2021-09-27 19:14:22 -07:00
Dhaval Patel
c281b3a879 disp: msm: reserve core clock rate during display disable
Userspace module may not trigger the atomic check and it
can cause the commit failure. In such case, always reserve
the minimum core clock rate on mmrm module for built-in
displays to avoid the power ON failure.

Change-Id: Iafd92a7b7d1b35befe70b041cbedaec2add40de4
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
2021-09-27 13:44:12 -07:00
Shashank Babu Chinta Venkata
1263b4cabc disp: msm: dsi: reorder DSI registration
Reorder registration of various display drivers in the order of
dependency.

Change-Id: Idfa0616d3133f3b03c713e3c15a4fd3956ec2594
Signed-off-by: Shashank Babu Chinta Venkata <sbchin@codeaurora.org>
2021-09-27 11:22:08 -07:00
Nilaan Gunabalachandran
711eabbf43 disp: msm: sde: account for pref lm when exposing avail resources
If an external display, such as DP, requests for the available
resources, resource manager (RM) will provide a count of all unused
mixers. If the primary/secondary display(s) are not active, the RM
will report the associated preferred mixers as free resources.
However, RM will not allow preferred mixers to be allocated to other
displays. DP driver could look at these available resources and assume
a high resolution mode is possible and fail during resource allocation.

This change updates the available resources info API to account for
primary/secondary preferences while exposing available resources.

Change-Id: I134a1047f24ac9f1fcee695aa14a1d3e43c1571f
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
2021-09-27 12:13:37 -04:00
qctecmdr
f1ae36dfab Merge "disp: msm: reset lm blend stages for missing vsync" 2021-09-24 00:47:23 -07:00
qctecmdr
efebe33c3e Merge "disp: msm: sde: set top left coordinates for noise and attenuation layers" 2021-09-22 09:59:18 -07:00
Dhaval Patel
fc2226ea25 disp: msm: reset lm blend stages for missing vsync
MDSS INTF HW block does not generate vsync if controller
turns off the link clock prematurely. This leads to
frame trigger timeout and SDE driver triggers the retire
fence after 84ms to recover gracefully. A client may switch
source pipe from one CTL path to another CTL path based
on delayed retire fence. It can lead to other ctl path
hang. This can be resolved by resetting the lm blend
stages for each missing vsync frame trigger.

Change-Id: I5a6ed03afbdad83d8fd6decc593d39e04bef62e4
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
2021-09-22 09:46:32 -07:00
Sandeep Gangadharaiah
e3927fdfaa disp: msm: dp: set drm mode clock same as clock value from EDID
Commit Ie972a2e140adfd81c4e68df8e7bc69feaaca22e1 updated the dp
driver to extract the drm mode clock from timing parameters
instead of using the clock value provided by EDID to align the
behavior with DSI driver. But this results in incorrect clock
value if the refresh rate is not an integer value. For rates
such as 59.94 or 29.97, the calculated mode clock value would
be different from what is stipulated by EDID. This change
reverts the mode clock calculation to use the clock value
from EDID.

Change-Id: I3e192ef09d2456fbb1d22a0bf9474ac25ba86c72
Signed-off-by: Sandeep Gangadharaiah <sandgang@codeaurora.org>
2021-09-21 18:06:57 -04:00
Anjaneya Prasad Musunuri
0a214e5d4a disp: msm: sde: set top left coordinates for noise and attenuation layers
Noise and attenuation layers are full screen layers. Top left coordinates
are not cleared in some use cases when same blend stage is assigned to
noise and attenuation layers. This change sets top left coordinates of noise
and attenuation layers.

Change-Id: I6af7a38d011d0bb642dc3d8a4aff338075524906
Signed-off-by: Anjaneya Prasad Musunuri <aprasad@codeaurora.org>
2021-09-21 23:01:35 +05:30
qctecmdr
e5ed14f97d Merge "disp: msm: dp: disable ASSR before link training" 2021-09-21 10:25:33 -07:00
Vara Reddy
087390da0d disp: msm: dp: disable ASSR before link training
Power on reset value of DPTX_CONFIGURATION_CTRL.ASSR (alternate scrambler
seed reset) is high. Which will cause link training 2 to fail with TPS4 pattern.
Change disables this before link training starts.

Change-Id: Iee95de04625658254b242afdcbba6db24a52606d
Signed-off-by: Vara Reddy <varar@codeaurora.org>
2021-09-21 00:02:58 -07:00
qctecmdr
9acf478553 Merge "disp: msm: dp: retry the request to set USB mode during bootup" 2021-09-20 22:29:36 -07:00
Sandeep Gangadharaiah
edd46a2a54 disp: msm: dp: retry the request to set USB mode during bootup
DP driver is requesting USB to release SS lanes very early
during bootup even before USB has fully initialized. As a
result USB driver is returning -11 which will abort DP state
machine. This change will allow DP driver to retry USB request
whenever this error code is received.

Change-Id: I144d16ef4b07016569ba9c04df15610fe3b5e6fc
Signed-off-by: Sandeep Gangadharaiah <sandgang@codeaurora.org>
2021-09-20 13:03:45 -07:00
qctecmdr
958acc9e7c Merge "disp: msm: retry dma buf attach on msm_gem_delayed_import error" 2021-09-20 12:59:46 -07:00
Nilaan Gunabalachandran
95a41081eb disp: msm: sde: clear intf mux select on slave encoders
When disabling an encoder with multiple physical encoders, the
intf mux must be cleared on all interfaces. Currently only the master
physical encoder is being cleared, leading to possible DSI
underflow errors. This change ensures that the mux is cleared
on all interface blocks.

Change-Id: Idb1b96fd65545e3599100e70ace22bc3837d7233
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
2021-09-17 17:11:19 -04:00
qctecmdr
785cde38ef Merge "disp: msm: dsi: mark signature for stub appropriately" 2021-09-17 03:46:41 -07:00
qctecmdr
0a9759ec0d Merge "disp: msm: dp: read DPCD registers using debugfs" 2021-09-17 03:46:41 -07:00
qctecmdr
c0dad8fa08 Merge "disp: msm: dsi: add qsync min fps val in dsi display mode priv info" 2021-09-17 03:46:41 -07:00
qctecmdr
7edd9e5faa Merge "disp: msm: dp: check for DP stream during audio teardown" 2021-09-17 03:46:41 -07:00
qctecmdr
0d46a03da7 Merge "display: msm: sde: reduce dbg mem usage for tui vm" 2021-09-17 03:46:41 -07:00
Linux Build Service Account
254160dcc0 Merge "disp: msm: dp: check for aux abort in sim mode" into display-kernel.lnx.5.10 2021-09-17 00:36:49 -07:00
Samantha Tran
8c62ff4082 disp: msm: retry dma buf attach on msm_gem_delayed_import error
In the event when msm_gem_delayed_import returns an error, reset
the obj_dirty property to true to allow the buffer to detach and
attach again.

Change-Id: Ib8da8f237c5a4ab696675cbcf66f1a3dfae02639
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2021-09-16 14:14:02 -07:00
Rajkumar Subbiah
fba8d96566 disp: msm: dp: check for aux abort in sim mode
In sim mode, the dp driver is not checking for the aux state before
processing an aux request. This ends up causing the drm framework to
unnecessarily wait for 4 seconds while destroying a stream.

This change adds the check for aux state to align with the behavior
of a real sink.

Change-Id: I81900018ac1b403bb1e03fe26206e145694fefbd
Signed-off-by: Rajkumar Subbiah <rsubbia@codeaurora.org>
2021-09-15 13:00:58 -04:00
Yashwanth
6619470eb6 disp: msm: dsi: add qsync min fps val in dsi display mode priv info
In the current code for finding the qsync min fps for a
mode, entire mode list is iterated which involves acquiring
dsi display_lock. During conn tx debugfs commands, if
qsync min fps is required, we try to acquire dsi
display_lock twice which results in hang state. This change
adds qsync min fps value in dsi_display_mode_priv_info
struct in order to get the qsync fps from the
msm_display_mode present in connector state instead of
looping through all the modes to find the mode qsync fps.

Change-Id: Ifded40d1f12462bb50fc7bdafb746ae5b8d9512a
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
2021-09-15 12:09:35 +05:30
Vara Reddy
655dd3b302 disp: msm: add support to notify trustzone ops TA
Change adds support to notify TZ ops TA for any HDCP 1.4
authentication state changes, so that TZ can optimize their
code for better performance.

Change-Id: I62f47e2e3fc102cb51cf695daa5f6b798f65781a
Signed-off-by: Vara Reddy <varar@codeaurora.org>
2021-09-14 10:10:36 -07:00
qctecmdr
00d92ec8d6 Merge "disp: msm: dsi: remove vote on refgen when PHY is turned off" 2021-09-10 17:10:28 -07:00
qctecmdr
e37f6a901f Merge "disp: msm: sde: remove redundant backlight update" 2021-09-10 14:04:54 -07:00
qctecmdr
16d516dc35 Merge "disp: msm: dsi: add support for setting backlight min level" 2021-09-10 14:04:54 -07:00
qctecmdr
82a8d86c9a Merge "disp: msm: sde: avoid mis-allocating dummy mixers" 2021-09-10 14:04:54 -07:00
qctecmdr
a3fc520ea7 Merge "disp: msm: sde: hold vmlock only during transition in check phase" 2021-09-10 14:04:54 -07:00
qctecmdr
42ec97efd5 Merge "msm: sde: disp: Set merge_mode after vlut and hist enable" 2021-09-10 14:04:54 -07:00
Shashank Babu Chinta Venkata
6fc34a0613 disp: msm: dsi: remove vote on refgen when PHY is turned off
Remove vote on refgen during display off usecase.

Change-Id: I4d618569c4e03c1b6dca637179053ee812b1d5d9
Signed-off-by: Shashank Babu Chinta Venkata <sbchin@codeaurora.org>
2021-09-10 13:39:51 -07:00
Alex Danila
d521b12b69 disp: msm: dp: read DPCD registers using debugfs
This change adds support for reading the byte at specific DPCD
addresses for physical monitors, similar to the way it is already done in
sim mode.

The read address is taken to be the last written address. Reads return a
single byte unless the address is 0, in which case 20 bytes are returned
to preserve the original functionality.

Change-Id: I43c44d81758c156257bd5dba6bb8f9c08ac948eb
Signed-off-by: Alex Danila <eadanila@codeaurora.org>
2021-09-10 16:36:18 -04:00
qctecmdr
b9c52b603e Merge "disp: msm: dsi: allow CMD engine enable for cont-splash" 2021-09-10 00:47:16 -07:00
Yahui Wang
23582c4de3 disp: msm: dsi: add support for setting backlight min level
Current display driver can't support kernel dts property
qcom,mdss-dsi-bl-min-level to adjust backlight min level,
so adding this change to make it work well if user wants to
increase the backlight min level of display panel.

Change-Id: Iac74ee44aafac88548ceba6b221d13251dc3d5ef
Signed-off-by: Yahui Wang <yahuiw@codeaurora.org>
2021-09-10 15:08:34 +08:00
Nilaan Gunabalachandran
3b303c57de disp: msm: sde: avoid mis-allocating dummy mixers
Dummy mixers for dedicated concurrent writeback can be allocated
as valid mixers. However, they should only be allocated for DCWB
usecases. Allocating these virtual resources incorrectly can lead
to underrun on external monitors. These dummy mixers should not
be tracked as available resources and exposed to dp for
mode validation.

Change-Id: I04f583d5b722e0a384a5446e3a8a2313a338aa12
Signed-off-by: Nilaan Gunabalachandran <ngunabal@codeaurora.org>
2021-09-09 09:48:08 -07:00
Yashwanth
811402fc83 disp: msm: sde: hold vmlock only during transition in check phase
In the current code, vmlock is always acquired in check
phase even if there is no transition between vm's. This
might result in janks if vmlock is held concurrently by
other processes such as backlight update. This change
ensures that vmlock is held only if there is a valid
transition request between vm's in check phase.

[cohens@codeauarora.org] Resolved trivial merge conflict
and refactored the code to reduce the code complexity.

Change-Id: I022f04c19ba04fdd5494580cc1436747620b9354
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
2021-09-09 01:45:18 -04:00
Ping Li
25f9e738ee msm: sde: disp: Set merge_mode after vlut and hist enable
To ensure that set merge_mode after vlut and hist enable, move merge_mode
enable from ltm_init to ltm_vlut.
Redefine the OP_MASK of LTM_INIT_ENABLE and LTM_VLUT_ENABLE, in order to
write the merge_mode bits correctly.

Change-Id: I5258e7f545e265b114098e46d31986274127e962
Signed-off-by: Ping Li <pingli@codeaurora.org>
Signed-off-by: Yuchao Ma <yuchaom@codeaurora.org>
2021-09-08 17:47:29 -07:00
Samantha Tran
dff7057a41 disp: msm: sde: remove redundant backlight update
Current logic will unnecessarily call backlight update
twice in cases where backlight level is changing. When
this happens, there is a potential delay waiting for the
first command to complete before sending the second
backlight update with the same value. This change removes
one backlight call and now only calls update if the
property is marked as dirty.

Change-Id: I260f0d73b3a5af9ced7ae261d247595f965a8d9e
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2021-09-08 16:07:31 -07:00
Shashank Babu Chinta Venkata
d38a8c0c19 disp: msm: dsi: mark signature for stub appropriately
DSI parser utils are enabled through kernel config
CONFIG_DSI_PARSER. The stubs for disabled case do not
have appropriate storage class. This change alters the
stubs to be static inline which is appropriate storage
class.

Change-Id: I692b792cc3e8a8340245ee5f356e1f6281276a59
Signed-off-by: Shashank Babu Chinta Venkata <sbchin@codeaurora.org>
2021-09-08 09:33:53 -07:00
Sandeep Gangadharaiah
cda8e4b1dd disp: msm: dp: check for DP stream during audio teardown
Verify if DP stream is still active before accessing dp audio
registers. This would prevent a scenario where audio teardown
flow is trying to access dp audio config registers after dp
has completed the deinit process.

Change-Id: Icbcaa19529fc2fb34e079231c9ef24e15aa7e4f2
Signed-off-by: Sandeep Gangadharaiah <sandgang@codeaurora.org>
2021-09-08 10:58:24 -04:00
qctecmdr
f04eb4120c Merge "disp: msm: dp: use 3dmux when dsc is not available" 2021-09-07 07:12:22 -07:00
Samantha Tran
19979de0af disp: msm: sde: update IB vote to include AB factor
With this change, the IB vote will be based on the following:

IB = AB_aggregated / number of DDR Channels / DRAM efficiency factor

Number of DDR Channels and DRAM efficiency factor are now device tree
properties which can be modified and parsed at boot up.

Change-Id: I298043807150faec1cbc0d74eefcdd1a534b460a
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2021-09-02 21:04:40 -07:00
qctecmdr
6e4731175f Merge "disp: msm: avoid begin/end cpu_access calls based on dma-coherent attribute" 2021-09-02 14:49:31 -07:00
qctecmdr
f192f6d6dc Merge "disp: msm: dsi: reset the DSI command ctrl flags for every command" 2021-09-01 18:19:24 -07:00
qctecmdr
187dbfdc65 Merge "disp: msm: sde: allow spec fence signaled with PENDING_ERROR as non fatal" 2021-09-01 13:38:33 -07:00
Rajat Gupta
7f0f23c35f disp: msm: dp: fix to handle host ready failures
Handle host_ready failures and try to initialize host if not already.
Sometimes customizations for customers causes NOC error as host_ready
doesn't return early upon failure and the customer customization
tries to access aux register to reconfig upon aux failure while
reading EDID. Adding fix will make driver more robust to handle such
cases.

Change-Id: Ifa5c56daa32c4ef366a0e05718495ffcb40b96b3
Signed-off-by: Rajat Gupta <rajatgu@codeaurora.org>
Signed-off-by: Sandeep Gangadharaiah <sandgang@codeaurora.org>
2021-09-01 14:05:43 -04:00
Satya Rama Aditya Pinapala
b63a13c0b8 disp: msm: dsi: reset the DSI command ctrl flags for every command
The controller flags need to be reset for each command. On resetting
it only for a batch of commands, it may carry stale values and cause
unexpected behavior.

Change-Id: I8473be0c4361965a58c33a3d45420c533d48646b
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
2021-09-01 10:14:31 -07:00