Acquire dsi_ctrl->ctrl_lock lock before programming dsi ctrl
registers. Failing this may lead to race conditions in register
programming.
Add missing mutex lock inside dsi_ctrl_host_timing_update().
Change-Id: Ic86cbe282333c0b4d63ae3d5b3356a5d24752203
Signed-off-by: Rajeev Nandan <quic_rajeevny@quicinc.com>
Pass the DRM_BRIDGE_ATTACH_NO_CONNECTOR flag when attaching the
bridge so that the bridge driver would not create another
drm connector.
Change-Id: I838bd87c40d0eea3df36187befeb7195fb87d5b3
Signed-off-by: Rahul Sharma <quic_rahsha@quicinc.com>
Avoid various possible nullptr dereferences.
Addresses various issues highlighted by static analysis.
Change-Id: I36d34d610b37bf2799a7e34cd1de8b909b5c0ae4
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
To toggle error interrupts, we currently read the DSI_INT_CTRL register,
toggle the DSI_ERROR_MASK bit and write back to the register. While doing
so we are also writing back 1 to any status bits set by HW, thus clearing
the status interrupts. Clearing the status bits should always be done as
part of interrupt handling, which otherwise can lead to command transfer
failures.
Avoid clearing status interrupts while error interrupts are toggled.
Change-Id: Iaae10c279f2341269ed49074448167e68ab7e13c
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
Sim panels are not working well with video mode, parse panel ack
disabled property to fix sim video mode identification issue.
Change-Id: Ife3b533d5a6db97618459dacf1f7ce8d3fc896bf
Signed-off-by: Yahui Wang <quic_yahuiw@quicinc.com>
Add line insertion support for sspp, this is used to support
display with external splitter. Line insertion logic checks
the difference between screen logical height and physical
height. If any difference is observed adds dummy and active
lines on screen.
Change-Id: Ieec322273df000a53fb39e05174c2d67c3c2da81
Signed-off-by: Rajesh kv <quic_kvrajesh@quicinc.com>
In transfer-time calculation remove fixed prefill lines assumption
and consider max of default prefill lines, prefill lines
specified from the panel timing info and Vtotal. For panels with
higher porches exceeding default prefill lines, alternate framedrops
can occur if transfer-time exceeds RSC static waketup time
as actual prefill lines are considered in RSC static wakeup timer
calculation. This change ensures transfer-time is within
RSC static wakeup time.
Change-Id: Ic489d69cf99cfb6750e871c7fc8197243f61acf3
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
This change adds a connector OP, that will be used to update frame
transfer time dynamically at the request from user space.
It also adds parsing for new device tree entries that set the minimum
and maximum trasnfer times on a mode basis. These min and max transfer
times are also published to userspace through the connector mode info
capabilities blob.
Change-Id: I12aedf96a51ff7feb2c5b3b1353d3c4ec8dcb068
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
Add DSI CTL MISR support for ctl 2.2 version. Reuse the same
debugfs nodes to setup/collect misr.
Change-Id: I3d8dfab093659ce53817d9511999c0c03cc33f62
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Refactor the function 'dsi_display_get_modes' to
reduce its complexity.
Change-Id: I1a8ecaa780e5070bac7fa40404677c0a8a5d7cd8
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
Mitigate errors to debug logs on non-parsed regulator look ups. Callers
can make use of the return value to handle failures.
Change-Id: Ib0ed869e92104ac7e859484b247ac99bf332fa5c
Signed-off-by: Jeykumar Sankaran <quic_jeykumar@quicinc.com>
Fix the Watchdog timer load value calculation with jitter feature.
Change the long term jitter value check to have jitter < 10.
Change-Id: If834e16d3b8fad5009642e479f529fa5b7cf2d17
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
* quic/display-kernel.lnx.5.10:
disp: msm: sde: avoid error during fal10_veto override enablement
disp: msm: update copyright description
disp: msm: sde: configure dest_scaler op_mode for two independent displays
disp: msm: dp: updated copyright set for 4nm target
Revert "disp: msm: sde: consider max of actual and default prefill lines"
disp: msm: sde: Reset backlight scale when HWC is stopped
disp: msm: dp: avoid duplicate read of link status
disp: msm: dsi: update vreg_ctrl settings for cape
disp: msm: fail commit if drm_gem_obj was found attached to a sec CB
disp: msm: dp: updated register values for 4nm target
disp: msm: sde: update framedata event handling
disp: msm: dsi: Add new phy comaptible string for cape
disp: msm: sde: software override for fal10 in cwb enable
disp: msm: update cleanup during bind failure in msm_drm_component_init
disp: msm: sde: dump user input_fence info on spec fence timeout
disp: msm: sde: add null pointer check for encoder current master
disp: msm: dsi: enable DMA start window scheduling for broadcast commands
disp: msm: sde: avoid alignment checks for linear formats
disp: msm: reset thread priority work on every new run
disp: msm: sde: send power on event for cont. splash
disp: msm: sde: always set CTL_x_UIDLE_ACTIVE register to "1"
disp: msm: use vzalloc for large allocations
disp: msm: sde: Add support to limit DSC size to 10k
disp: msm: sde: add tx wait during DMS for sim panel
disp: msm: dsi: add check for any queued DSI CMDs before clock force update
disp: msm: sde: correct pp block allocation during dcwb dither programming
disp: msm: sde: avoid setting of max vblank count
disp: msm: sde: add cached lut flag in sde plane
disp: msm: sde: avoid use after free in msm_lastclose
disp: msm: sde: update TEAR_SYNC_WRCOUNT register before vsync counter
disp: msm: dsi: Support uncompressed rgb101010 format
disp: msm: sde: update idle_pc_enabled flag for all encoders
disp: msm: sde: flush esd work before disabling the encoder
disp: msm: sde: allow qsync update along with modeset
disp: msm: dp: avoid dp sw reset on disconnect path
disp: msm: sde: consider max of actual and default prefill lines
disp: msm: ensure vbif debugbus not in use is disabled
disp: msm: sde: update cached encoder mask if required
disp: msm: sde: while timing engine enabling poll for active region
disp: msm: enable cache flag for dumb buffer
disp: msm: sde: disable ot limit for cwb
disp: msm: sde: avoid race condition at vm release
disp: msm: dsi: set qsync min fps list length to zero
disp: msm: sde: reset mixers in crtc when ctl datapath switches
disp: msm: sde: update vm state atomic check for non-primary usecases
disp: msm: sde: reset CTL_UIDLE_ACTIVE register only if uidle is disabled
Change-Id: If480e7f33743eb4788549f853ba05e744ecb38d3
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
This change updates copyright description with correct
license marking as per the guidelines.
Change-Id: Ia74b721e78afcc7f8e88bcbccfcf15430111ec37
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
This reverts commit 6547137f7b.
This change can cause negative mdp_transfer_time_us for the panels with
VFP as big as panel active height.
Change-Id: Ibebfcacd9c4eddf80749fa55509821b332fba4cf
Signed-off-by: Rajeev Nandan <quic_rajeevny@quicinc.com>
This change updates vreg_ctrl_0 and vreg_ctrl_1 settings for
cape DPHY as per the HW recommendation.
Change-Id: Ide66c62d980b57de1f826ed24d1c0747d8fb6c77
Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
Cape uses phy version 4.3 but requires programming of
different values for vreg_ctrl_0 and vreg_ctrl_1 to
configure LDO setting. Add new phy compatible string
to distinguish cape from other chipsets and program
the registers accordingly.
Change-Id: I68b266cc6e179d211ee0fd05584a605f39b4d31d
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
Use #if IS_ENABLED() instead of #ifdef for configurations as vendor module
guidelines.
Use #if IS_ENABLED(CONFIG_XXX) instead of #ifdef CONFIG_XXX to ensure that
the code inside the #if block continues to compile if the config changes
to a tristate config in the future.
The differences are as follows:
1.#if IS_ENABLED(CONFIG_XXX) evaluates to true when CONFIG_XXX is set to
module (=m) or built-in (=y).
2.#ifdef CONFIG_XXX evaluates to true when CONFIG_XXX is set to
built-in(=y) , but doesn't when CONFIG_XXX is set to module(=m).
Use this only when you're certain you want to do the same thing
when the config is set to module or is disabled.
Change-Id: Ia806b9b01ad8414d0e4de027a382cb68e7fb4a6a
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
As per the HW requirements it is highly recommended to use DMA start window
to trigger broadcast commands. If not used then it can result in a hardware
hang with the DSI controllers going out of sync. This behavior is even more
prominent in cases of higher refresh rates.
Currently, reset_trigger_controls is called as part of next command.
Due to this, when unicast command is sent after broadcast command,
reset_trigger_controls does not get called for slave controller,
leading to issues.
As part of this change, DMA start window scheduling is enabled as default
for broadcast commands and reset_trigger_controls is done as part of
post_cmd_transfer operations.
Change-Id: I2402214ed79b376d102b88d4f7e6a06fcb5712d3
Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
msm/sde/sde_encoder.c
_sde_encoder_update_rsc_client()
sde_encoder_prepare_for_kickoff()
msm/dsi/dsi_drm.c
dsi_bridge_mode_fixup()
Lower the cyclomatic complexity for this function by splitting
the work into helper functions.
Change-Id: I2285809a33078e29989a6b44800c18342aa24170
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
Add HW recommended programming sequence for when PHY is allowed to turn
off during idle.
Change-Id: Iaeafa17d9821913b42ae669dbd21f244783f4cdd
Signed-off-by: Shashank Babu Chinta Venkata <quic_schintav@quicinc.com>
Change adds the new files for DSI PHY version 5 and 4nm
DSI PLL.
Change-Id: I97712d6ce53a60a6fae1c8331b6ba9a5d17b8d34
Signed-off-by: Shashank Babu Chinta Venkata <quic_schintav@quicinc.com>
pm_runtime_get_sync increases the usage_count refcount immaterial of
success/failure of the call, leading to invalid refcount on failures.
Use pm_runtime_resume_and_get instead, which takes care of reducing the
refcount on failure cases before returning from the function.
Change-Id: Ib96050d5d7ecbd717e58b8a0dde2d03312444e15
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
During a force update of DSI clocks, the state of the byte and pclks are
toggled irrespective of the ref-count. This in addition with ASYNC
command wait can result in interrupt storm, if and when the clocks are
being toggled a previous command that was triggered using the ASYNC
wait flag fires an ISR. The interrupt status doesn't get cleared if
the ISR is being serviced with the clocks are off.
The change adds a check for pending queued commands before any force
update of DSI clocks.
Change-Id: I4ca60d0ad43767791255f00c9af8e99e74786097
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Signed-off-by: Rajeev Nandan <quic_rajeevny@quicinc.com>
In transfer-time calculation remove fixed prefill lines assumption
and consider max of default prefill lines and prefill lines specified
from the panel timing info.
For panels with higher porches exceeding default prefill lines
alternate framedrops can occur if transfer-time exceeds RSC static
waketup time as actual prefill lines are considered in RSC static
wakeup timer calculation. This change ensures transfer-time is with
in RSC static wakeup time.
Change-Id: I3663f9c9179efb7225a748f456f2a2cf167d241e
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
In certain usecase where qsync is enabled without qsync
min fps list, incorrect list length might cause issues
while populating modes. This change sets qsync_min_fps
length to zero if its empty which resolves such issues.
Change-Id: I23083d8fd9610665dad63188f5d2db7eb6b23ee1
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
This change adds support in mdp and dsi driver to support
multiple SIS.
Change-Id: I432068cea17e1784d7570a472fbadaa86695df07
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
Signed-off-by: Amine Najahi <anajahi@codeaurora.org>
Commit bf0d220 ("disp: msm: dsi: add _NO_ to MIPI_DSI_* flags
disabling features") update names of DSI flags to follow upstream
convention. Purpose of the name change is to more clearly indicate
what is not supported when the flag is set.
This change puts macros around MIPI_DSI_* flags to adapt the name change
of flags for kernel version 5.10 and version 5.15..
Change-Id: I1c9a8da3819a6b641ca9b6d81191bc944913b49e
Signed-off-by: Bruce Hoo <bingchua@codeaurora.org>
Add dsi ctrl version 2.7 and dsi phy version 5.2 support for
Kalama hardware.
Change-Id: Ia7b4c8a2e1579458f114e466de8b24855e9251ce
Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org>
Currently, in dsi_display_get_modes, priv_info, rates,
front_porches and pixel_clks_khz memory is allocated for each
timing node and the same memory is copied for each supported fps.
The values of front porches calculated to maintain constant fps for
each bit clk rate gets overwritten with the values for last fps in
the dfps list. But the values of front porches should be different
in case where DFPS and dynamic clock are both supported either by
vfp approach or hfp approach. To fix this, allocate memory
separately for each fps.
Change-Id: Ibf753aa8cca8d77b02b20785b5435f1aba05106e
Signed-off-by: Kashish Jain <kashjain@codeaurora.org>
Add check to clip the sunlight visibility scale to an upper limit of
MAX_SV_BL_SCALE_LEVEL * 4.
Change-Id: I8cc7bf8fba90e115d046ec030983801ce6d93c1d
Signed-off-by: Ping Li <pingli@codeaurora.org>
Signed-off-by: Yuchao Ma <yuchaom@codeaurora.org>
This change adds additional logs in dsi driver for
easy debugging of issues related to command transfer.
Change-Id: Ica784bed6c360b2760d6606d625837e23a22410c
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
For read commands, wait_for_done() should be called in dsi_message_rx function.
Currently, its being called twice from dsi_message_rx and dsi_ctrl_post_cmd_transfer.
This change adds a check to skip wait_for_done() from dsi_ctrl_post_cmd_transfer.
Change-Id: Icb7ccd0f8dde24c6c26732f7cb92a20bebb26f5d
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
In ASYNC wait mode, next command kickoff can happen before previous command ISR execution is
completed in below sequence:
ASYNC command A -> triggered
dsi_ctrl_isr for command A -> fired and executed atomic_set(&dsi_ctrl->dma_irq_trig, 1);
wait_for_done for command A -> returns early as dsi_ctrl->dma_irq_trig is 1
ASYNC Command B -> triggered
wait_for_done for command B -> waiting for cmd_dma_done
dsi_ctrl_isr for command A -> executes complete_all(&dsi_ctrl->irq_info.cmd_dma_done);
wait_for_done for command B -> returns success incorrectly based on complete_all of previous
command isr and disable_status_interrupt() is not called.
This leads to refcount of dma_done going wrong and dsi_ctrl_isr is not enabled on suspend resume.
To fix this issue, mark command transfer successful only based on complete_all(cmd_dma_done). This
way disable_status_interrupt() will be always called either from dsi_ctrl_isr or wait_for_done().
Change-Id: I0379ea7ff82a1e077b95f6996d11d1722de00936
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
