Adds a check for rc in case of VFE process cmd failure
during cam_ife_mgr_start_hw function.
CRs-Fixed: 3317130
Change-Id: I686828ed5593aeaae6e00bb2435df32b27a2a9bd
Signed-off-by: Joshua Florez <quic_jflorez@quicinc.com>
This commit adds missing break in switch while selecting
the phy values for CSID.
Change-Id: I901e8715861f70ec59e34d64b7d553ca9d747b8f
CRs-Fixed: 3307427
Signed-off-by: Gaurav Jindal <quic_gjindal@quicinc.com>
Adds a return condition for wm failure in vfe bus ver3.
CRs-Fixed: 3316560
Change-Id: I6e8792509b2a6f4276f15bce8bcf221a7bdfdcd7
Signed-off-by: Joshua Florez <quic_jflorez@quicinc.com>
Configure go_cmd once per CSID/IFE, irrespective of the base
index.
CRs-Fixed: 3309163
Change-Id: Iee2d876ff9351e92c96aecd8f12b968f56f01cde
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
Skip epoch height config from userland for CSID CAMIF, if
they are not subscribed for as primary events in non-SFE
use-cases.
CRs-Fixed: 3306019
Change-Id: I08546d568661cbf040dbb22c3bc9d4e92cec332b
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
Address enabling CSID IRQs on SOF freeze. Enable the input
IRQ events when state machine encounters congestion as well.
CRs-Fixed: 3309151
Change-Id: Ib7611167444a795dd14339cb689a0e116e30b5fd
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
Fix return conditions leading to structurally dead code in csid.
CRs-Fixed: 3306112, 3306117
Change-Id: Id6716f970186756be4c6d879335f2630cecf403c
Signed-off-by: Mukund Madhusudan Atre <quic_matre@quicinc.com>
Add precision to nanosecond part of monotonic timestamps.
Update delimiters between second and nanosecond values.
CRs-Fixed: 3307225
Change-Id: I4e7aab0ea9256c2ff769a87c3873002d715ed3c9
Signed-off-by: Mukund Madhusudan Atre <quic_matre@quicinc.com>
Update register offset for CSID and CSID-Lite 880.
Discarding CSID secure register offset which is beginning
of reg space and not accessible from HLOS.
CRs-Fixed: 3291241
Change-Id: I693f85ef4f824e159f3fb0589b7d4bfc2148d000
Signed-off-by: Chandan Kumar Jha <quic_cjha@quicinc.com>
Instead of caching packet address pointer, store packet handle
in page fault req info structutre to obtain packet address through
mem manager to avoid potential access to dangling packet pointer which
resulted from UMD called to free the packet buffer before kernel finishes
handling page fault. If the packet was freed, then querying to get packet
address from memory manager will fail since the mem handle is invalid.
If it is invalid, the page fault handler will return before accessing
the dangling packet.
CRs-Fixed: 3287554
Change-Id: I02bc0c706b64f1dc0d098d8189f2f129a91efba7
Signed-off-by: Sokchetra Eung <quic_eung@quicinc.com>
Update the correct WM idx for ALSC client for v880. The
change also removes dependency on comp group type for
buf done irq masking. The order is not maintained in HW
so breaking that assumption in SW, and making the buf done
irq bit mask as an array for comp groups.
CRs-Fixed: 3254772
Change-Id: I7ac1dcf4150761b2f6f124e389a5e5b1ea67bd83
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
For SFE enabled usecase, if the RDI0 is an input image stream
for SFE IPP, we doesn't flag the global value acquired rdi res,
if PDAF stream is enabled, the RDI0 will be acquired again, and
reserve another CSID set, and the stream on fail.
CRs-Fixed: 3288480
Change-Id: I2a6b2363c5cc6bff27736e6848686781cba3f560
Signed-off-by: chengxue <quic_chengxue@quicinc.com>
Update register offset for VFE-Lite 880.
Discarding csid secure register offset which is beginning
of reg space and not accesable from HLOS.
CRs-Fixed: 3263421
Change-Id: Ib10a9b54057f262a92612e3a53bc29dd8afb5fe3
Signed-off-by: zhuo <quic_zhuo@quicinc.com>
In HW, the rup_aup latching scheme is enabled for dynamic switch
use-cases. The feature is to handle delayed rup_aup programming
between CSID SOF and CAMIF SOF. On Kailua with this feature enabled
we seem to be encountering CCIF protocol violations on IPP/PPP paths.
Disabling the feature, for now. The issue this feature is trying
to address is SW programming in a narrow window of 4 CSID clock cycles,
which is really small in SW.
CRs-Fixed: 3247669
Change-Id: I7678174541e8dd6b533eb95922e0814035811258
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
In function cam_ife_hw_mgr_acquire_res_ife_csid_pxl, if csid_res is added
to res_list_ife_csid, and if no_res_acquired is true, the csid_res will be
add to free_res_list without list delete operation, this will damage the
res_list_ife_csid.
CRs-Fixed: 3272891
Change-Id: Ic6ee6edeed8dce82fb7a2907daf5fa634cca8a7f
Signed-off-by: mingpan <quic_mingpan@quicinc.com>
This change adds domain-id support for new
targets. This change involves adding information
to the SCM call currently in use such that it is
a superset, and the additional fields needed are
the IFE and CDM number being used, and VC mask.
These are in addition to existing PHY mask selection,
and lane/trio mask selection.
All the information above will be sent over from CSID
to the PHY driver, and the PHY driver will pack the
information in a generic format before sending it
over in an SCM call. Where previously, this information
is packed in format that matches the register, this
will be sent generically moving forward.
Given that there are multiple instances per physical
PHY hardware, and that the usual dev_handle used by
userspace to identify them are not accessible CSID
side, the lane_assign/lane_cfg parameter is used to find
the specific PHY instance used in conjunction with the
CSID instance in a session. lane_assign from PHY driver
and lane_cfg from CSID have the same values.
CRs-Fixed: 3259706
Change-Id: Ie050b1b9e742c6a63812eb38db7eca76db24667f
Signed-off-by: Li Sha Lim <quic_lishlim@quicinc.com>
Starting from Kailua, for LCR-PD use-cases HW expects certain
timing constraints to be met by the 2 paths(RDI0/PPP).
On flush/resume scenarios where the sensor continues to stream, and
if we do an independent path resume it is possible that
due to intrinsic SW/AHB latencies the two paths might latch
at different times. In order to overcome such issues, we
enable sync between RDI0 & PPP, RDI0 being the master and issue
a global resume cmd. With global resume all paths will resume
at the same time, and with the sync enabled we are certain that
RDI0/PPP will be resumed in sync as well. This change configures
global resume for single IFE lcr use-cases.
CRs-Fixed: 3233582
Change-Id: I034b1a491afa951298e2cb63e6242dcbd499b19e
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
Irrespective of kernel debugfs, if there is a regdump
buffer provided for INIT packet trigger the dump.
CRs-Fixed: 3258552
Change-Id: I96d79ff6956ad567e526524500bf37f83e23908b
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
In case of dual CSID acquire, if the acquire fails
for the second CSID, we fail to free the first one.
The change addresses this issue.
CRs-Fixed: 3253317
Change-Id: I3fd8e7b7c38a3fa31fd93f281f2afdd98b9994a6
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
This commit saves the timestamp for CSID CAMIF IRQs and
print in case of overflow. In case of IFE, it avoids
dumping timestamps if no IRQ are subsribed.
CRs-Fixed: 3249483
Change-Id: Icac71f60f0616fc14aeb5e5b6efd5d203b27ddcc
Signed-off-by: Gaurav Jindal <quic_gjindal@quicinc.com>
RDI WMs are no exception to period/pattern config. Just like other WMs
RDIs can be configured to any period/pattern. This change is only
for bus ver3, for which address increment register exists for all
RDIs, so we can remove any limitation checks.
CRs-Fixed: 3249063
Change-Id: Ib24a7178e2a3ca6e56898ed1ff57331fed270222
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
Add debug drv flag to enable info logging for drv.
CRs-Fixed: 3065551
Change-Id: Ief9e2a84a379b9f0261567bcf13e2405f3c97d15
Signed-off-by: Mukund Madhusudan Atre <quic_matre@quicinc.com>
This change extends internal scheme for certain specific
scenarios. If the mode switch is applied in between exposures
it could potentially lead to out_of_sync/hang. On the switching
frame if there is no sufficient common blanking among different
exposures, CSID HW flags it, internal recovery is triggered for this.
Also it's possible that due to packet delays, IFE & sensor go out of sync,
we can try internal recovery in this case as well on receiving
out of sync error consecutively for 3 frames.
CRs-Fixed: 3254775
Change-Id: I56b40bb9f73959e66174af382025c897c18ffed4
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
Null pointer might be used uninitialized in case param input is null,
now we will return with -EINVAL directly to avoid passing null pointer
to other function.
CRs-Fixed: 3250360
Change-Id: I19bd6f83d2f6315f55f05559b6984e721ca3d143
Signed-off-by: Stark Lin <quic_starlin@quicinc.com>
Signed-off-by: Depeng Shao <quic_depengs@quicinc.com>
Remove unnecessary memsets of the structure variables
whose fields are assigned prior to their usage or they
are dynamically allocated with calls that set the memory
to 0. This memset usage optimization is to improve
performance.
CRs-Fixed: 3228092
Change-Id: Iec68c6d072863627959ce603cff28afd26a1c408
Signed-off-by: Sokchetra Eung <quic_eung@quicinc.com>
Send ife process frame event from IFE HW manager for presil
which pchost depends on to start IFE frame runcore or regdump.
CRs-Fixed: 3212166
Change-Id: I268059ec490b2a95f0626045eed26192eb0a42a2
Signed-off-by: Joshua Florez <quic_jflorez@quicinc.com>
Signed-off-by: Suraj Dongre <quic_sdongre@quicinc.com>
LCR enabled flag is not reset during flush and the corresponding
register is also not reset. It could cause random behavior after
flush.
This commit resets LCR flags during flush.
CRs-Fixed: 3241884
Change-Id: I8821656ae7baf97a59cdc57bb79ded9552185f08
Signed-off-by: Gaurav Jindal <quic_gjindal@quicinc.com>
The core info in hw info structure pointer to
csid hw, we need to get correct core info from
the private data of match dev.
CRs-Fixed: 3234793
Change-Id: I4f295c6eb206a0a61fb923b1e04bd00786dbfccf
Signed-off-by: Depeng Shao <quic_depengs@quicinc.com>
SFE resource count isn't fixed, it is less than the max
supported resource, we need to use actual resource count
to release the resource.
CRs-Fixed: 3234791
Change-Id: I7cb16f3d8120451cac1bfc226f6849268f3b5c46
Signed-off-by: Depeng Shao <quic_depengs@quicinc.com>
Fix the argument order for SFE bus deinit calls.
CRs-Fixed: 3218412
Change-Id: I7ecda25aae455e0d9302b7f379ec019053a34e92
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
The drv and bw voting blobs are handled by isp generic blob
handler, so need to skip for sfe blob handler.
CRs-Fixed: 3065551
Change-Id: I467d16818d2807194e3c7b62bd6b2b1eb06b4759
Signed-off-by: Mukund Madhusudan Atre <quic_matre@quicinc.com>
Get the shift mask from the corresponding chipset header.
CRs-Fixed: 3226910
Change-Id: I45f439e7b7ec23096ecb31f2b94cf76189669e7f
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
Due to timing protocol constraints between LCR and PD resources and
sof retiminig disabled, PPP resource should be enabled after RDI0
whenever LCR is enabled.
This commit changes the order during the CSID start to enable PPP
after RDI0.
CRs-Fixed: 3222469
Change-Id: I11371ea4602ff4bd72e690453103bd6a18ba836a
Signed-off-by: Gaurav Jindal <quic_gjindal@quicinc.com>
Other than stat WMs, all other clients can run in secure mode.
CRs-Fixed: 3208187
Change-Id: I17956a4815a56eacbaa14e08db98fde681a6d9d6
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
Add error handling and information logging for drv error and
info irqs for drv. Also, add debugfs for vote up and down irqs.
Add ddr and mnoc register value logging in vote up and down
irq bottom half.
CRs-Fixed: 3065551
Change-Id: I5332658924762a528625e628c3fa5d5dec07da62
Signed-off-by: Mukund Madhusudan Atre <quic_matre@quicinc.com>
Add support for bw update version 3. Add provision to
maintain cpas per path bw info internally in drivers.
CRs-Fixed: 3065551
Change-Id: I65e97c6e41f933818f1211bbc27651842e93c028
Signed-off-by: Mukund Madhusudan Atre <quic_matre@quicinc.com>
Top debug cfg register is getting reset while starting RDI resources.
This commit adds the register data to RDI resources and reads back
the register before updating the register.
CRs-Fixed: 3207575
Change-Id: I4e149fc81cbfc60adb6d3bb842a1057e8202903f
Signed-off-by: Gaurav Jindal <quic_gjindal@quicinc.com>
Removes IFE HW manager reference from ISP context and moves some
LDAR dump functionality for stream info to IFE HW manager.
CRs-Fixed: 3210247
Change-Id: I311c7cd8d8684a68ba0bfbe279ef9ba55cfbbe82
Signed-off-by: Joshua Florez <quic_jflorez@quicinc.com>
In some cases while using scratch buffer UBWC registers are not
configured even after receiving the update blob from Userland.
This results in constraint errors at bus side.
This commit configures the UBWC registers at stream on if the
blob was received for the ports which are UBWC enabled.
Change-Id: Icf9a66808432052c84f52bbf470880fde082cee3
CRs-Fixed: 3108015
Signed-off-by: Gaurav Jindal <quic_gjindal@quicinc.com>
Only for FE use-cases, allow SFE pix ports to be acquired when the
input resource is RDI0-2.
CRs-Fixed: 3207073
Change-Id: Ic190d6ba1fb8cb63db5fef63bda05a7cac9c0c51
Signed-off-by: Karthik Anantha Ram <quic_kartanan@quicinc.com>
