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@@ -13,6 +13,8 @@
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#include "cam_irq_controller.h"
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#include "cam_isp_hw_mgr_intf.h"
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+/* Offsets might not match due to csid secure regs at beginning of reg space */
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+
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static const struct cam_ife_csid_irq_desc cam_ife_csid_lite_880_rx_irq_desc[] = {
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{
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.bitmask = BIT(0),
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@@ -286,49 +288,49 @@ static const struct cam_ife_csid_top_irq_desc cam_ife_csid_lite_880_top_irq_desc
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static struct cam_irq_register_set cam_ife_csid_lite_880_irq_reg_set[9] = {
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/* Top */
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{
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- .mask_reg_offset = 0x00001080,
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- .clear_reg_offset = 0x00001084,
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- .status_reg_offset = 0x0000107C,
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- .set_reg_offset = 0x00001088,
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+ .mask_reg_offset = 0x00000080,
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+ .clear_reg_offset = 0x00000084,
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+ .status_reg_offset = 0x0000007C,
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+ .set_reg_offset = 0x00000088,
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.test_set_val = BIT(0),
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.test_sub_val = BIT(0),
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},
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/* RX */
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{
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- .mask_reg_offset = 0x000010A0,
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- .clear_reg_offset = 0x000010A4,
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- .status_reg_offset = 0x0000109C,
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+ .mask_reg_offset = 0x000000A0,
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+ .clear_reg_offset = 0x000000A4,
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+ .status_reg_offset = 0x0000009C,
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},
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/* RDI0 */
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{
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- .mask_reg_offset = 0x000010F0,
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- .clear_reg_offset = 0x000010F4,
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- .status_reg_offset = 0x000010EC,
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+ .mask_reg_offset = 0x000000F0,
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+ .clear_reg_offset = 0x000000F4,
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+ .status_reg_offset = 0x000000EC,
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},
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/* RDI1 */
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{
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- .mask_reg_offset = 0x00001100,
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- .clear_reg_offset = 0x00001104,
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- .status_reg_offset = 0x000010FC,
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+ .mask_reg_offset = 0x00000100,
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+ .clear_reg_offset = 0x00000104,
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+ .status_reg_offset = 0x000000FC,
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},
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/* RDI2 */
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{
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- .mask_reg_offset = 0x00001110,
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- .clear_reg_offset = 0x00001114,
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- .status_reg_offset = 0x0000110C,
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+ .mask_reg_offset = 0x00000110,
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+ .clear_reg_offset = 0x00000114,
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+ .status_reg_offset = 0x0000010C,
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},
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/* RDI3 */
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{
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- .mask_reg_offset = 0x00001120,
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- .clear_reg_offset = 0x00001124,
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- .status_reg_offset = 0x0000111C,
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+ .mask_reg_offset = 0x00000120,
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+ .clear_reg_offset = 0x00000124,
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+ .status_reg_offset = 0x0000011C,
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},
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{}, /* no RDI4 */
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/* IPP */
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{
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- .mask_reg_offset = 0x000010B0,
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- .clear_reg_offset = 0x000010B4,
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- .status_reg_offset = 0x000010AC,
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+ .mask_reg_offset = 0x000000B0,
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+ .clear_reg_offset = 0x000000B4,
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+ .status_reg_offset = 0x000000AC,
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},
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{}, /* no PPP */
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};
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@@ -336,7 +338,7 @@ static struct cam_irq_register_set cam_ife_csid_lite_880_irq_reg_set[9] = {
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static struct cam_irq_controller_reg_info cam_ife_csid_lite_880_top_irq_reg_info = {
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.num_registers = 1,
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.irq_reg_set = &cam_ife_csid_lite_880_irq_reg_set[CAM_IFE_CSID_IRQ_REG_TOP],
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- .global_irq_cmd_offset = 0x00001014,
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+ .global_irq_cmd_offset = 0x00000014,
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.global_set_bitmask = 0x00000010,
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.global_clear_bitmask = 0x00000001,
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.clear_all_bitmask = 0xFFFFFFFF,
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@@ -379,9 +381,9 @@ static struct cam_irq_controller_reg_info cam_ife_csid_lite_880_path_irq_reg_inf
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static struct cam_irq_register_set cam_ife_csid_lite_880_buf_done_irq_reg_set[1] = {
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{
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- .mask_reg_offset = 0x00001090,
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- .clear_reg_offset = 0x00001094,
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- .status_reg_offset = 0x0000108C,
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+ .mask_reg_offset = 0x00000090,
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+ .clear_reg_offset = 0x00000094,
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+ .status_reg_offset = 0x0000008C,
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},
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};
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@@ -394,25 +396,23 @@ static struct cam_irq_controller_reg_info
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static struct cam_ife_csid_ver2_common_reg_info
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cam_ife_csid_lite_880_cmn_reg_info = {
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- .hw_version_addr = 0x1000,
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- .cfg0_addr = 0x1004,
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- .global_cmd_addr = 0x1008,
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- .reset_cfg_addr = 0x100c,
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- .reset_cmd_addr = 0x1010,
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- .irq_cmd_addr = 0x1014,
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- .rup_aup_cmd_addr = 0x1018,
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- .offline_cmd_addr = 0x101C,
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- .shdr_master_slave_cfg_addr = 0x1020,
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- .top_irq_status_addr = 0x107C,
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- .top_irq_mask_addr = 0x1080,
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- .top_irq_clear_addr = 0x1084,
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- .top_irq_set_addr = 0x1088,
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- .buf_done_irq_status_addr = 0x108C,
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- .buf_done_irq_mask_addr = 0x1090,
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- .buf_done_irq_clear_addr = 0x1094,
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- .buf_done_irq_set_addr = 0x1098,
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- .path_domain_id_cfg0 = 0x0,
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- .path_domain_id_cfg1 = 0x4,
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+ .hw_version_addr = 0x0000,
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+ .cfg0_addr = 0x0004,
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+ .global_cmd_addr = 0x0008,
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+ .reset_cfg_addr = 0x000c,
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+ .reset_cmd_addr = 0x0010,
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+ .irq_cmd_addr = 0x0014,
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+ .rup_aup_cmd_addr = 0x0018,
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+ .offline_cmd_addr = 0x001C,
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+ .shdr_master_slave_cfg_addr = 0x0020,
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+ .top_irq_status_addr = 0x007C,
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+ .top_irq_mask_addr = 0x0080,
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+ .top_irq_clear_addr = 0x0084,
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+ .top_irq_set_addr = 0x0088,
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+ .buf_done_irq_status_addr = 0x008C,
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+ .buf_done_irq_mask_addr = 0x0090,
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+ .buf_done_irq_clear_addr = 0x0094,
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+ .buf_done_irq_set_addr = 0x0098,
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/*configurations */
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.major_version = 6,
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@@ -473,40 +473,38 @@ static struct cam_ife_csid_ver2_common_reg_info
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static struct cam_ife_csid_csi2_rx_reg_info
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cam_ife_csid_lite_880_csi2_reg_info = {
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- .irq_status_addr = 0x109C,
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- .irq_mask_addr = 0x10A0,
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- .irq_clear_addr = 0x10A4,
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- .irq_set_addr = 0x10A8,
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+ .irq_status_addr = 0x009C,
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+ .irq_mask_addr = 0x00A0,
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+ .irq_clear_addr = 0x00A4,
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+ .irq_set_addr = 0x00A8,
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/*CSI2 rx control */
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- .cfg0_addr = 0x1200,
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- .cfg1_addr = 0x1204,
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- .capture_ctrl_addr = 0x1208,
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- .rst_strobes_addr = 0x120C,
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- .cap_unmap_long_pkt_hdr_0_addr = 0x1210,
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- .cap_unmap_long_pkt_hdr_1_addr = 0x1214,
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- .captured_short_pkt_0_addr = 0x1218,
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- .captured_short_pkt_1_addr = 0x121c,
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- .captured_long_pkt_0_addr = 0x1220,
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- .captured_long_pkt_1_addr = 0x1224,
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- .captured_long_pkt_ftr_addr = 0x1228,
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- .captured_cphy_pkt_hdr_addr = 0x122c,
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- .lane0_misr_addr = 0x1230,
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- .lane1_misr_addr = 0x1234,
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- .lane2_misr_addr = 0x1238,
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- .lane3_misr_addr = 0x123c,
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- .total_pkts_rcvd_addr = 0x1240,
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- .stats_ecc_addr = 0x1244,
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- .total_crc_err_addr = 0x1248,
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- .de_scramble_type3_cfg0_addr = 0x124C,
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- .de_scramble_type3_cfg1_addr = 0x1250,
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- .de_scramble_type2_cfg0_addr = 0x1254,
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- .de_scramble_type2_cfg1_addr = 0x1258,
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- .de_scramble_type1_cfg0_addr = 0x125C,
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- .de_scramble_type1_cfg1_addr = 0x1260,
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- .de_scramble_type0_cfg0_addr = 0x1264,
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- .de_scramble_type0_cfg1_addr = 0x1268,
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- .secure_cfg0 = 0x8,
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- .secure_mask_cfg0 = 0xC,
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+ .cfg0_addr = 0x0200,
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+ .cfg1_addr = 0x0204,
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+ .capture_ctrl_addr = 0x0208,
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+ .rst_strobes_addr = 0x020C,
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+ .cap_unmap_long_pkt_hdr_0_addr = 0x0210,
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+ .cap_unmap_long_pkt_hdr_1_addr = 0x0214,
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+ .captured_short_pkt_0_addr = 0x0218,
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+ .captured_short_pkt_1_addr = 0x021c,
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+ .captured_long_pkt_0_addr = 0x0220,
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+ .captured_long_pkt_1_addr = 0x0224,
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+ .captured_long_pkt_ftr_addr = 0x0228,
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+ .captured_cphy_pkt_hdr_addr = 0x022c,
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+ .lane0_misr_addr = 0x0230,
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+ .lane1_misr_addr = 0x0234,
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+ .lane2_misr_addr = 0x0238,
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+ .lane3_misr_addr = 0x023c,
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+ .total_pkts_rcvd_addr = 0x0240,
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+ .stats_ecc_addr = 0x0244,
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+ .total_crc_err_addr = 0x0248,
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+ .de_scramble_type3_cfg0_addr = 0x024C,
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+ .de_scramble_type3_cfg1_addr = 0x0250,
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+ .de_scramble_type2_cfg0_addr = 0x0254,
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+ .de_scramble_type2_cfg1_addr = 0x0258,
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+ .de_scramble_type1_cfg0_addr = 0x025C,
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+ .de_scramble_type1_cfg1_addr = 0x0260,
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+ .de_scramble_type0_cfg0_addr = 0x0264,
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+ .de_scramble_type0_cfg1_addr = 0x0268,
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.rst_done_shift_val = 27,
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.irq_mask_all = 0xFFFFFFF,
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@@ -554,67 +552,66 @@ static struct cam_ife_csid_csi2_rx_reg_info
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static struct cam_ife_csid_ver2_path_reg_info
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cam_ife_csid_lite_880_ipp_reg_info = {
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- .irq_status_addr = 0x10AC,
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- .irq_mask_addr = 0x10B0,
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- .irq_clear_addr = 0x10B4,
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- .irq_set_addr = 0x10B8,
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- .cfg0_addr = 0x1300,
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- .ctrl_addr = 0x1304,
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- .debug_clr_cmd_addr = 0x1308,
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- .multi_vcdt_cfg0_addr = 0x130c,
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- .cfg1_addr = 0x1310,
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- .err_recovery_cfg0_addr = 0x1318,
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- .err_recovery_cfg1_addr = 0x131C,
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- .err_recovery_cfg2_addr = 0x1320,
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- .camif_frame_cfg_addr = 0x1330,
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- .epoch_irq_cfg_addr = 0x1334,
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- .epoch0_subsample_ptrn_addr = 0x1338,
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- .epoch1_subsample_ptrn_addr = 0x133C,
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- .debug_camif_1_addr = 0x1340,
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- .debug_camif_0_addr = 0x1344,
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- .debug_halt_status_addr = 0x1348,
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- .debug_misr_val0_addr = 0x134C,
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- .debug_misr_val1_addr = 0x1350,
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- .debug_misr_val2_addr = 0x1354,
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- .debug_misr_val3_addr = 0x1358,
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- .hcrop_addr = 0x135c,
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- .vcrop_addr = 0x1360,
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- .pix_drop_pattern_addr = 0x1364,
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- .pix_drop_period_addr = 0x1368,
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- .line_drop_pattern_addr = 0x136C,
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- .line_drop_period_addr = 0x1370,
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- .frm_drop_pattern_addr = 0x1374,
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- .frm_drop_period_addr = 0x1378,
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- .irq_subsample_pattern_addr = 0x137C,
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- .irq_subsample_period_addr = 0x1380,
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- .format_measure_cfg0_addr = 0x1384,
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- .format_measure_cfg1_addr = 0x1388,
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- .format_measure0_addr = 0x138C,
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- .format_measure1_addr = 0x1390,
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- .format_measure2_addr = 0x1394,
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- .timestamp_curr0_sof_addr = 0x1398,
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- .timestamp_curr1_sof_addr = 0x139C,
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- .timestamp_perv0_sof_addr = 0x13A0,
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- .timestamp_perv1_sof_addr = 0x13A4,
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- .timestamp_curr0_eof_addr = 0x13A8,
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- .timestamp_curr1_eof_addr = 0x13AC,
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- .timestamp_perv0_eof_addr = 0x13B0,
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- .timestamp_perv1_eof_addr = 0x13B4,
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- .batch_period_cfg_addr = 0x13C4,
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- .batch_stream_id_cfg_addr = 0x13C8,
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- .epoch0_cfg_batch_id0_addr = 0x13CC,
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- .epoch1_cfg_batch_id0_addr = 0x13D0,
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- .epoch0_cfg_batch_id1_addr = 0x13D4,
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- .epoch1_cfg_batch_id1_addr = 0x13D8,
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- .epoch0_cfg_batch_id2_addr = 0x13DC,
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- .epoch1_cfg_batch_id2_addr = 0x13E0,
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- .epoch0_cfg_batch_id3_addr = 0x13E4,
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- .epoch1_cfg_batch_id3_addr = 0x13E8,
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- .epoch0_cfg_batch_id4_addr = 0x13EC,
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- .epoch1_cfg_batch_id4_addr = 0x13F0,
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- .epoch0_cfg_batch_id5_addr = 0x13F4,
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- .epoch1_cfg_batch_id5_addr = 0x13F8,
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- .secure_mask_cfg0 = 0x10,
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+ .irq_status_addr = 0x00AC,
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+ .irq_mask_addr = 0x00B0,
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+ .irq_clear_addr = 0x00B4,
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+ .irq_set_addr = 0x00B8,
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+ .cfg0_addr = 0x0300,
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+ .ctrl_addr = 0x0304,
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+ .debug_clr_cmd_addr = 0x0308,
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+ .multi_vcdt_cfg0_addr = 0x030c,
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+ .cfg1_addr = 0x0310,
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+ .err_recovery_cfg0_addr = 0x0318,
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+ .err_recovery_cfg1_addr = 0x031C,
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+ .err_recovery_cfg2_addr = 0x0320,
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+ .camif_frame_cfg_addr = 0x0330,
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+ .epoch_irq_cfg_addr = 0x0334,
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+ .epoch0_subsample_ptrn_addr = 0x0338,
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+ .epoch1_subsample_ptrn_addr = 0x033C,
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+ .debug_camif_1_addr = 0x0340,
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+ .debug_camif_0_addr = 0x0344,
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+ .debug_halt_status_addr = 0x0348,
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+ .debug_misr_val0_addr = 0x034C,
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+ .debug_misr_val1_addr = 0x0350,
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+ .debug_misr_val2_addr = 0x0354,
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+ .debug_misr_val3_addr = 0x0358,
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+ .hcrop_addr = 0x035c,
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+ .vcrop_addr = 0x0360,
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+ .pix_drop_pattern_addr = 0x0364,
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+ .pix_drop_period_addr = 0x0368,
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+ .line_drop_pattern_addr = 0x036C,
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+ .line_drop_period_addr = 0x0370,
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+ .frm_drop_pattern_addr = 0x0374,
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+ .frm_drop_period_addr = 0x0378,
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+ .irq_subsample_pattern_addr = 0x037C,
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+ .irq_subsample_period_addr = 0x0380,
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+ .format_measure_cfg0_addr = 0x0384,
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+ .format_measure_cfg1_addr = 0x0388,
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+ .format_measure0_addr = 0x038C,
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+ .format_measure1_addr = 0x0390,
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+ .format_measure2_addr = 0x0394,
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+ .timestamp_curr0_sof_addr = 0x0398,
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|
+ .timestamp_curr1_sof_addr = 0x039C,
|
|
|
+ .timestamp_perv0_sof_addr = 0x03A0,
|
|
|
+ .timestamp_perv1_sof_addr = 0x03A4,
|
|
|
+ .timestamp_curr0_eof_addr = 0x03A8,
|
|
|
+ .timestamp_curr1_eof_addr = 0x03AC,
|
|
|
+ .timestamp_perv0_eof_addr = 0x03B0,
|
|
|
+ .timestamp_perv1_eof_addr = 0x03B4,
|
|
|
+ .batch_period_cfg_addr = 0x03C4,
|
|
|
+ .batch_stream_id_cfg_addr = 0x03C8,
|
|
|
+ .epoch0_cfg_batch_id0_addr = 0x03CC,
|
|
|
+ .epoch1_cfg_batch_id0_addr = 0x03D0,
|
|
|
+ .epoch0_cfg_batch_id1_addr = 0x03D4,
|
|
|
+ .epoch1_cfg_batch_id1_addr = 0x03D8,
|
|
|
+ .epoch0_cfg_batch_id2_addr = 0x03DC,
|
|
|
+ .epoch1_cfg_batch_id2_addr = 0x03E0,
|
|
|
+ .epoch0_cfg_batch_id3_addr = 0x03E4,
|
|
|
+ .epoch1_cfg_batch_id3_addr = 0x03E8,
|
|
|
+ .epoch0_cfg_batch_id4_addr = 0x03EC,
|
|
|
+ .epoch1_cfg_batch_id4_addr = 0x03F0,
|
|
|
+ .epoch0_cfg_batch_id5_addr = 0x03F4,
|
|
|
+ .epoch1_cfg_batch_id5_addr = 0x03F8,
|
|
|
|
|
|
/* configurations */
|
|
|
.start_mode_internal = 0x0,
|
|
|
@@ -650,69 +647,68 @@ static struct cam_ife_csid_ver2_path_reg_info
|
|
|
|
|
|
static struct cam_ife_csid_ver2_path_reg_info
|
|
|
cam_ife_csid_lite_880_rdi_0_reg_info = {
|
|
|
- .irq_status_addr = 0x10EC,
|
|
|
- .irq_mask_addr = 0x10F0,
|
|
|
- .irq_clear_addr = 0x10F4,
|
|
|
- .irq_set_addr = 0x10F8,
|
|
|
- .cfg0_addr = 0x1500,
|
|
|
- .ctrl_addr = 0x1504,
|
|
|
- .debug_clr_cmd_addr = 0x1508,
|
|
|
- .multi_vcdt_cfg0_addr = 0x150c,
|
|
|
- .cfg1_addr = 0x1510,
|
|
|
- .err_recovery_cfg0_addr = 0x1514,
|
|
|
- .err_recovery_cfg1_addr = 0x1518,
|
|
|
- .err_recovery_cfg2_addr = 0x151C,
|
|
|
- .debug_byte_cntr_ping_addr = 0x1520,
|
|
|
- .debug_byte_cntr_pong_addr = 0x1524,
|
|
|
- .camif_frame_cfg_addr = 0x1528,
|
|
|
- .epoch_irq_cfg_addr = 0x152C,
|
|
|
- .epoch0_subsample_ptrn_addr = 0x1530,
|
|
|
- .epoch1_subsample_ptrn_addr = 0x1534,
|
|
|
- .debug_camif_1_addr = 0x1538,
|
|
|
- .debug_camif_0_addr = 0x153C,
|
|
|
- .frm_drop_pattern_addr = 0x1540,
|
|
|
- .frm_drop_period_addr = 0x1540,
|
|
|
- .irq_subsample_pattern_addr = 0x1548,
|
|
|
- .irq_subsample_period_addr = 0x154C,
|
|
|
- .hcrop_addr = 0x1550,
|
|
|
- .vcrop_addr = 0x1554,
|
|
|
- .pix_drop_pattern_addr = 0x1558,
|
|
|
- .pix_drop_period_addr = 0x155C,
|
|
|
- .line_drop_pattern_addr = 0x1560,
|
|
|
- .line_drop_period_addr = 0x1564,
|
|
|
- .debug_halt_status_addr = 0x1568,
|
|
|
- .debug_misr_val0_addr = 0x1570,
|
|
|
- .debug_misr_val1_addr = 0x1574,
|
|
|
- .debug_misr_val2_addr = 0x1578,
|
|
|
- .debug_misr_val3_addr = 0x157C,
|
|
|
- .format_measure_cfg0_addr = 0x1580,
|
|
|
- .format_measure_cfg1_addr = 0x1584,
|
|
|
- .format_measure0_addr = 0x1588,
|
|
|
- .format_measure1_addr = 0x158C,
|
|
|
- .format_measure2_addr = 0x1590,
|
|
|
- .timestamp_curr0_sof_addr = 0x1594,
|
|
|
- .timestamp_curr1_sof_addr = 0x1598,
|
|
|
- .timestamp_perv0_sof_addr = 0x159C,
|
|
|
- .timestamp_perv1_sof_addr = 0x15A0,
|
|
|
- .timestamp_curr0_eof_addr = 0x15A4,
|
|
|
- .timestamp_curr1_eof_addr = 0x15A8,
|
|
|
- .timestamp_perv0_eof_addr = 0x15AC,
|
|
|
- .timestamp_perv1_eof_addr = 0x15B0,
|
|
|
- .batch_period_cfg_addr = 0x15BC,
|
|
|
- .batch_stream_id_cfg_addr = 0x15C0,
|
|
|
- .epoch0_cfg_batch_id0_addr = 0x15C4,
|
|
|
- .epoch1_cfg_batch_id0_addr = 0x15C8,
|
|
|
- .epoch0_cfg_batch_id1_addr = 0x15CC,
|
|
|
- .epoch1_cfg_batch_id1_addr = 0x15D0,
|
|
|
- .epoch0_cfg_batch_id2_addr = 0x15D4,
|
|
|
- .epoch1_cfg_batch_id2_addr = 0x15D8,
|
|
|
- .epoch0_cfg_batch_id3_addr = 0x15DC,
|
|
|
- .epoch1_cfg_batch_id3_addr = 0x15E0,
|
|
|
- .epoch0_cfg_batch_id4_addr = 0x15E4,
|
|
|
- .epoch1_cfg_batch_id4_addr = 0x15E8,
|
|
|
- .epoch0_cfg_batch_id5_addr = 0x15EC,
|
|
|
- .epoch1_cfg_batch_id5_addr = 0x15F0,
|
|
|
- .secure_mask_cfg0 = 0x18,
|
|
|
+ .irq_status_addr = 0x00EC,
|
|
|
+ .irq_mask_addr = 0x00F0,
|
|
|
+ .irq_clear_addr = 0x00F4,
|
|
|
+ .irq_set_addr = 0x00F8,
|
|
|
+ .cfg0_addr = 0x0500,
|
|
|
+ .ctrl_addr = 0x0504,
|
|
|
+ .debug_clr_cmd_addr = 0x0508,
|
|
|
+ .multi_vcdt_cfg0_addr = 0x050c,
|
|
|
+ .cfg1_addr = 0x0510,
|
|
|
+ .err_recovery_cfg0_addr = 0x0514,
|
|
|
+ .err_recovery_cfg1_addr = 0x0518,
|
|
|
+ .err_recovery_cfg2_addr = 0x051C,
|
|
|
+ .debug_byte_cntr_ping_addr = 0x0520,
|
|
|
+ .debug_byte_cntr_pong_addr = 0x0524,
|
|
|
+ .camif_frame_cfg_addr = 0x0528,
|
|
|
+ .epoch_irq_cfg_addr = 0x052C,
|
|
|
+ .epoch0_subsample_ptrn_addr = 0x0530,
|
|
|
+ .epoch1_subsample_ptrn_addr = 0x0534,
|
|
|
+ .debug_camif_1_addr = 0x0538,
|
|
|
+ .debug_camif_0_addr = 0x053C,
|
|
|
+ .frm_drop_pattern_addr = 0x0540,
|
|
|
+ .frm_drop_period_addr = 0x0540,
|
|
|
+ .irq_subsample_pattern_addr = 0x0548,
|
|
|
+ .irq_subsample_period_addr = 0x054C,
|
|
|
+ .hcrop_addr = 0x0550,
|
|
|
+ .vcrop_addr = 0x0554,
|
|
|
+ .pix_drop_pattern_addr = 0x0558,
|
|
|
+ .pix_drop_period_addr = 0x055C,
|
|
|
+ .line_drop_pattern_addr = 0x0560,
|
|
|
+ .line_drop_period_addr = 0x0564,
|
|
|
+ .debug_halt_status_addr = 0x0568,
|
|
|
+ .debug_misr_val0_addr = 0x0570,
|
|
|
+ .debug_misr_val1_addr = 0x0574,
|
|
|
+ .debug_misr_val2_addr = 0x0578,
|
|
|
+ .debug_misr_val3_addr = 0x057C,
|
|
|
+ .format_measure_cfg0_addr = 0x0580,
|
|
|
+ .format_measure_cfg1_addr = 0x0584,
|
|
|
+ .format_measure0_addr = 0x0588,
|
|
|
+ .format_measure1_addr = 0x058C,
|
|
|
+ .format_measure2_addr = 0x0590,
|
|
|
+ .timestamp_curr0_sof_addr = 0x0594,
|
|
|
+ .timestamp_curr1_sof_addr = 0x0598,
|
|
|
+ .timestamp_perv0_sof_addr = 0x059C,
|
|
|
+ .timestamp_perv1_sof_addr = 0x05A0,
|
|
|
+ .timestamp_curr0_eof_addr = 0x05A4,
|
|
|
+ .timestamp_curr1_eof_addr = 0x05A8,
|
|
|
+ .timestamp_perv0_eof_addr = 0x05AC,
|
|
|
+ .timestamp_perv1_eof_addr = 0x05B0,
|
|
|
+ .batch_period_cfg_addr = 0x05BC,
|
|
|
+ .batch_stream_id_cfg_addr = 0x05C0,
|
|
|
+ .epoch0_cfg_batch_id0_addr = 0x05C4,
|
|
|
+ .epoch1_cfg_batch_id0_addr = 0x05C8,
|
|
|
+ .epoch0_cfg_batch_id1_addr = 0x05CC,
|
|
|
+ .epoch1_cfg_batch_id1_addr = 0x05D0,
|
|
|
+ .epoch0_cfg_batch_id2_addr = 0x05D4,
|
|
|
+ .epoch1_cfg_batch_id2_addr = 0x05D8,
|
|
|
+ .epoch0_cfg_batch_id3_addr = 0x05DC,
|
|
|
+ .epoch1_cfg_batch_id3_addr = 0x05E0,
|
|
|
+ .epoch0_cfg_batch_id4_addr = 0x05E4,
|
|
|
+ .epoch1_cfg_batch_id4_addr = 0x05E8,
|
|
|
+ .epoch0_cfg_batch_id5_addr = 0x05EC,
|
|
|
+ .epoch1_cfg_batch_id5_addr = 0x05F0,
|
|
|
|
|
|
/* configurations */
|
|
|
.resume_frame_boundary = 1,
|
|
|
@@ -744,69 +740,68 @@ static struct cam_ife_csid_ver2_path_reg_info
|
|
|
|
|
|
static struct cam_ife_csid_ver2_path_reg_info
|
|
|
cam_ife_csid_lite_880_rdi_1_reg_info = {
|
|
|
- .irq_status_addr = 0x10FC,
|
|
|
- .irq_mask_addr = 0x1100,
|
|
|
- .irq_clear_addr = 0x1104,
|
|
|
- .irq_set_addr = 0x1108,
|
|
|
- .cfg0_addr = 0x1600,
|
|
|
- .ctrl_addr = 0x1604,
|
|
|
- .debug_clr_cmd_addr = 0x1608,
|
|
|
- .multi_vcdt_cfg0_addr = 0x160c,
|
|
|
- .cfg1_addr = 0x1610,
|
|
|
- .err_recovery_cfg0_addr = 0x1614,
|
|
|
- .err_recovery_cfg1_addr = 0x1618,
|
|
|
- .err_recovery_cfg2_addr = 0x161C,
|
|
|
- .debug_byte_cntr_ping_addr = 0x1620,
|
|
|
- .debug_byte_cntr_pong_addr = 0x1624,
|
|
|
- .camif_frame_cfg_addr = 0x1628,
|
|
|
- .epoch_irq_cfg_addr = 0x162C,
|
|
|
- .epoch0_subsample_ptrn_addr = 0x1630,
|
|
|
- .epoch1_subsample_ptrn_addr = 0x1634,
|
|
|
- .debug_camif_1_addr = 0x1638,
|
|
|
- .debug_camif_0_addr = 0x163C,
|
|
|
- .frm_drop_pattern_addr = 0x1640,
|
|
|
- .frm_drop_period_addr = 0x1644,
|
|
|
- .irq_subsample_pattern_addr = 0x1648,
|
|
|
- .irq_subsample_period_addr = 0x164C,
|
|
|
- .hcrop_addr = 0x1650,
|
|
|
- .vcrop_addr = 0x1654,
|
|
|
- .pix_drop_pattern_addr = 0x1658,
|
|
|
- .pix_drop_period_addr = 0x165C,
|
|
|
- .line_drop_pattern_addr = 0x1660,
|
|
|
- .line_drop_period_addr = 0x1664,
|
|
|
- .debug_halt_status_addr = 0x166C,
|
|
|
- .debug_misr_val0_addr = 0x1670,
|
|
|
- .debug_misr_val1_addr = 0x1674,
|
|
|
- .debug_misr_val2_addr = 0x1678,
|
|
|
- .debug_misr_val3_addr = 0x167C,
|
|
|
- .format_measure_cfg0_addr = 0x1680,
|
|
|
- .format_measure_cfg1_addr = 0x1684,
|
|
|
- .format_measure0_addr = 0x1688,
|
|
|
- .format_measure1_addr = 0x168C,
|
|
|
- .format_measure2_addr = 0x1690,
|
|
|
- .timestamp_curr0_sof_addr = 0x1694,
|
|
|
- .timestamp_curr1_sof_addr = 0x1698,
|
|
|
- .timestamp_perv0_sof_addr = 0x169C,
|
|
|
- .timestamp_perv1_sof_addr = 0x16A0,
|
|
|
- .timestamp_curr0_eof_addr = 0x16A4,
|
|
|
- .timestamp_curr1_eof_addr = 0x16A8,
|
|
|
- .timestamp_perv0_eof_addr = 0x16AC,
|
|
|
- .timestamp_perv1_eof_addr = 0x16B0,
|
|
|
- .batch_period_cfg_addr = 0x16BC,
|
|
|
- .batch_stream_id_cfg_addr = 0x16C0,
|
|
|
- .epoch0_cfg_batch_id0_addr = 0x16C4,
|
|
|
- .epoch1_cfg_batch_id0_addr = 0x16C8,
|
|
|
- .epoch0_cfg_batch_id1_addr = 0x16CC,
|
|
|
- .epoch1_cfg_batch_id1_addr = 0x16D0,
|
|
|
- .epoch0_cfg_batch_id2_addr = 0x16D4,
|
|
|
- .epoch1_cfg_batch_id2_addr = 0x16D8,
|
|
|
- .epoch0_cfg_batch_id3_addr = 0x16DC,
|
|
|
- .epoch1_cfg_batch_id3_addr = 0x16E0,
|
|
|
- .epoch0_cfg_batch_id4_addr = 0x16E4,
|
|
|
- .epoch1_cfg_batch_id4_addr = 0x16E8,
|
|
|
- .epoch0_cfg_batch_id5_addr = 0x16EC,
|
|
|
- .epoch1_cfg_batch_id5_addr = 0x16F0,
|
|
|
- .secure_mask_cfg0 = 0x1C,
|
|
|
+ .irq_status_addr = 0x00FC,
|
|
|
+ .irq_mask_addr = 0x0100,
|
|
|
+ .irq_clear_addr = 0x0104,
|
|
|
+ .irq_set_addr = 0x0108,
|
|
|
+ .cfg0_addr = 0x0600,
|
|
|
+ .ctrl_addr = 0x0604,
|
|
|
+ .debug_clr_cmd_addr = 0x0608,
|
|
|
+ .multi_vcdt_cfg0_addr = 0x060c,
|
|
|
+ .cfg1_addr = 0x0610,
|
|
|
+ .err_recovery_cfg0_addr = 0x0614,
|
|
|
+ .err_recovery_cfg1_addr = 0x0618,
|
|
|
+ .err_recovery_cfg2_addr = 0x061C,
|
|
|
+ .debug_byte_cntr_ping_addr = 0x0620,
|
|
|
+ .debug_byte_cntr_pong_addr = 0x0624,
|
|
|
+ .camif_frame_cfg_addr = 0x0628,
|
|
|
+ .epoch_irq_cfg_addr = 0x062C,
|
|
|
+ .epoch0_subsample_ptrn_addr = 0x0630,
|
|
|
+ .epoch1_subsample_ptrn_addr = 0x0634,
|
|
|
+ .debug_camif_1_addr = 0x0638,
|
|
|
+ .debug_camif_0_addr = 0x063C,
|
|
|
+ .frm_drop_pattern_addr = 0x0640,
|
|
|
+ .frm_drop_period_addr = 0x0644,
|
|
|
+ .irq_subsample_pattern_addr = 0x0648,
|
|
|
+ .irq_subsample_period_addr = 0x064C,
|
|
|
+ .hcrop_addr = 0x0650,
|
|
|
+ .vcrop_addr = 0x0654,
|
|
|
+ .pix_drop_pattern_addr = 0x0658,
|
|
|
+ .pix_drop_period_addr = 0x065C,
|
|
|
+ .line_drop_pattern_addr = 0x0660,
|
|
|
+ .line_drop_period_addr = 0x0664,
|
|
|
+ .debug_halt_status_addr = 0x066C,
|
|
|
+ .debug_misr_val0_addr = 0x0670,
|
|
|
+ .debug_misr_val1_addr = 0x0674,
|
|
|
+ .debug_misr_val2_addr = 0x0678,
|
|
|
+ .debug_misr_val3_addr = 0x067C,
|
|
|
+ .format_measure_cfg0_addr = 0x0680,
|
|
|
+ .format_measure_cfg1_addr = 0x0684,
|
|
|
+ .format_measure0_addr = 0x0688,
|
|
|
+ .format_measure1_addr = 0x068C,
|
|
|
+ .format_measure2_addr = 0x0690,
|
|
|
+ .timestamp_curr0_sof_addr = 0x0694,
|
|
|
+ .timestamp_curr1_sof_addr = 0x0698,
|
|
|
+ .timestamp_perv0_sof_addr = 0x069C,
|
|
|
+ .timestamp_perv1_sof_addr = 0x06A0,
|
|
|
+ .timestamp_curr0_eof_addr = 0x06A4,
|
|
|
+ .timestamp_curr1_eof_addr = 0x06A8,
|
|
|
+ .timestamp_perv0_eof_addr = 0x06AC,
|
|
|
+ .timestamp_perv1_eof_addr = 0x06B0,
|
|
|
+ .batch_period_cfg_addr = 0x06BC,
|
|
|
+ .batch_stream_id_cfg_addr = 0x06C0,
|
|
|
+ .epoch0_cfg_batch_id0_addr = 0x06C4,
|
|
|
+ .epoch1_cfg_batch_id0_addr = 0x06C8,
|
|
|
+ .epoch0_cfg_batch_id1_addr = 0x06CC,
|
|
|
+ .epoch1_cfg_batch_id1_addr = 0x06D0,
|
|
|
+ .epoch0_cfg_batch_id2_addr = 0x06D4,
|
|
|
+ .epoch1_cfg_batch_id2_addr = 0x06D8,
|
|
|
+ .epoch0_cfg_batch_id3_addr = 0x06DC,
|
|
|
+ .epoch1_cfg_batch_id3_addr = 0x06E0,
|
|
|
+ .epoch0_cfg_batch_id4_addr = 0x06E4,
|
|
|
+ .epoch1_cfg_batch_id4_addr = 0x06E8,
|
|
|
+ .epoch0_cfg_batch_id5_addr = 0x06EC,
|
|
|
+ .epoch1_cfg_batch_id5_addr = 0x06F0,
|
|
|
|
|
|
/* configurations */
|
|
|
.resume_frame_boundary = 1,
|
|
|
@@ -838,69 +833,68 @@ static struct cam_ife_csid_ver2_path_reg_info
|
|
|
|
|
|
static struct cam_ife_csid_ver2_path_reg_info
|
|
|
cam_ife_csid_lite_880_rdi_2_reg_info = {
|
|
|
- .irq_status_addr = 0x110C,
|
|
|
- .irq_mask_addr = 0x1110,
|
|
|
- .irq_clear_addr = 0x1114,
|
|
|
- .irq_set_addr = 0x1118,
|
|
|
- .cfg0_addr = 0x1700,
|
|
|
- .ctrl_addr = 0x1704,
|
|
|
- .debug_clr_cmd_addr = 0x1708,
|
|
|
- .multi_vcdt_cfg0_addr = 0x170c,
|
|
|
- .cfg1_addr = 0x1710,
|
|
|
- .err_recovery_cfg0_addr = 0x1714,
|
|
|
- .err_recovery_cfg1_addr = 0x1718,
|
|
|
- .err_recovery_cfg2_addr = 0x171C,
|
|
|
- .debug_byte_cntr_ping_addr = 0x1720,
|
|
|
- .debug_byte_cntr_pong_addr = 0x1724,
|
|
|
- .camif_frame_cfg_addr = 0x1728,
|
|
|
- .epoch_irq_cfg_addr = 0x172C,
|
|
|
- .epoch0_subsample_ptrn_addr = 0x1730,
|
|
|
- .epoch1_subsample_ptrn_addr = 0x1734,
|
|
|
- .debug_camif_1_addr = 0x1738,
|
|
|
- .debug_camif_0_addr = 0x173C,
|
|
|
- .frm_drop_pattern_addr = 0x1740,
|
|
|
- .frm_drop_period_addr = 0x1744,
|
|
|
- .irq_subsample_pattern_addr = 0x1748,
|
|
|
- .irq_subsample_period_addr = 0x174C,
|
|
|
- .hcrop_addr = 0x1750,
|
|
|
- .vcrop_addr = 0x1754,
|
|
|
- .pix_drop_pattern_addr = 0x1758,
|
|
|
- .pix_drop_period_addr = 0x175C,
|
|
|
- .line_drop_pattern_addr = 0x1760,
|
|
|
- .line_drop_period_addr = 0x1764,
|
|
|
- .debug_halt_status_addr = 0x176C,
|
|
|
- .debug_misr_val0_addr = 0x1770,
|
|
|
- .debug_misr_val1_addr = 0x1774,
|
|
|
- .debug_misr_val2_addr = 0x1778,
|
|
|
- .debug_misr_val3_addr = 0x177C,
|
|
|
- .format_measure_cfg0_addr = 0x1780,
|
|
|
- .format_measure_cfg1_addr = 0x1784,
|
|
|
- .format_measure0_addr = 0x1788,
|
|
|
- .format_measure1_addr = 0x178C,
|
|
|
- .format_measure2_addr = 0x1790,
|
|
|
- .timestamp_curr0_sof_addr = 0x1794,
|
|
|
- .timestamp_curr1_sof_addr = 0x1798,
|
|
|
- .timestamp_perv0_sof_addr = 0x179C,
|
|
|
- .timestamp_perv1_sof_addr = 0x17A0,
|
|
|
- .timestamp_curr0_eof_addr = 0x17A4,
|
|
|
- .timestamp_curr1_eof_addr = 0x17A8,
|
|
|
- .timestamp_perv0_eof_addr = 0x17AC,
|
|
|
- .timestamp_perv1_eof_addr = 0x17B0,
|
|
|
- .batch_period_cfg_addr = 0x17BC,
|
|
|
- .batch_stream_id_cfg_addr = 0x17C0,
|
|
|
- .epoch0_cfg_batch_id0_addr = 0x17C4,
|
|
|
- .epoch1_cfg_batch_id0_addr = 0x17C8,
|
|
|
- .epoch0_cfg_batch_id1_addr = 0x17CC,
|
|
|
- .epoch1_cfg_batch_id1_addr = 0x17D0,
|
|
|
- .epoch0_cfg_batch_id2_addr = 0x17D4,
|
|
|
- .epoch1_cfg_batch_id2_addr = 0x17D8,
|
|
|
- .epoch0_cfg_batch_id3_addr = 0x17DC,
|
|
|
- .epoch1_cfg_batch_id3_addr = 0x17E0,
|
|
|
- .epoch0_cfg_batch_id4_addr = 0x17E4,
|
|
|
- .epoch1_cfg_batch_id4_addr = 0x17E8,
|
|
|
- .epoch0_cfg_batch_id5_addr = 0x17EC,
|
|
|
- .epoch1_cfg_batch_id5_addr = 0x17F0,
|
|
|
- .secure_mask_cfg0 = 0x20,
|
|
|
+ .irq_status_addr = 0x010C,
|
|
|
+ .irq_mask_addr = 0x0110,
|
|
|
+ .irq_clear_addr = 0x0114,
|
|
|
+ .irq_set_addr = 0x0118,
|
|
|
+ .cfg0_addr = 0x0700,
|
|
|
+ .ctrl_addr = 0x0704,
|
|
|
+ .debug_clr_cmd_addr = 0x0708,
|
|
|
+ .multi_vcdt_cfg0_addr = 0x070c,
|
|
|
+ .cfg1_addr = 0x0710,
|
|
|
+ .err_recovery_cfg0_addr = 0x0714,
|
|
|
+ .err_recovery_cfg1_addr = 0x0718,
|
|
|
+ .err_recovery_cfg2_addr = 0x071C,
|
|
|
+ .debug_byte_cntr_ping_addr = 0x0720,
|
|
|
+ .debug_byte_cntr_pong_addr = 0x0724,
|
|
|
+ .camif_frame_cfg_addr = 0x0728,
|
|
|
+ .epoch_irq_cfg_addr = 0x072C,
|
|
|
+ .epoch0_subsample_ptrn_addr = 0x0730,
|
|
|
+ .epoch1_subsample_ptrn_addr = 0x0734,
|
|
|
+ .debug_camif_1_addr = 0x0738,
|
|
|
+ .debug_camif_0_addr = 0x073C,
|
|
|
+ .frm_drop_pattern_addr = 0x0740,
|
|
|
+ .frm_drop_period_addr = 0x0744,
|
|
|
+ .irq_subsample_pattern_addr = 0x0748,
|
|
|
+ .irq_subsample_period_addr = 0x074C,
|
|
|
+ .hcrop_addr = 0x0750,
|
|
|
+ .vcrop_addr = 0x0754,
|
|
|
+ .pix_drop_pattern_addr = 0x0758,
|
|
|
+ .pix_drop_period_addr = 0x075C,
|
|
|
+ .line_drop_pattern_addr = 0x0760,
|
|
|
+ .line_drop_period_addr = 0x0764,
|
|
|
+ .debug_halt_status_addr = 0x076C,
|
|
|
+ .debug_misr_val0_addr = 0x0770,
|
|
|
+ .debug_misr_val1_addr = 0x0774,
|
|
|
+ .debug_misr_val2_addr = 0x0778,
|
|
|
+ .debug_misr_val3_addr = 0x077C,
|
|
|
+ .format_measure_cfg0_addr = 0x0780,
|
|
|
+ .format_measure_cfg1_addr = 0x0784,
|
|
|
+ .format_measure0_addr = 0x0788,
|
|
|
+ .format_measure1_addr = 0x078C,
|
|
|
+ .format_measure2_addr = 0x0790,
|
|
|
+ .timestamp_curr0_sof_addr = 0x0794,
|
|
|
+ .timestamp_curr1_sof_addr = 0x0798,
|
|
|
+ .timestamp_perv0_sof_addr = 0x079C,
|
|
|
+ .timestamp_perv1_sof_addr = 0x07A0,
|
|
|
+ .timestamp_curr0_eof_addr = 0x07A4,
|
|
|
+ .timestamp_curr1_eof_addr = 0x07A8,
|
|
|
+ .timestamp_perv0_eof_addr = 0x07AC,
|
|
|
+ .timestamp_perv1_eof_addr = 0x07B0,
|
|
|
+ .batch_period_cfg_addr = 0x07BC,
|
|
|
+ .batch_stream_id_cfg_addr = 0x07C0,
|
|
|
+ .epoch0_cfg_batch_id0_addr = 0x07C4,
|
|
|
+ .epoch1_cfg_batch_id0_addr = 0x07C8,
|
|
|
+ .epoch0_cfg_batch_id1_addr = 0x07CC,
|
|
|
+ .epoch1_cfg_batch_id1_addr = 0x07D0,
|
|
|
+ .epoch0_cfg_batch_id2_addr = 0x07D4,
|
|
|
+ .epoch1_cfg_batch_id2_addr = 0x07D8,
|
|
|
+ .epoch0_cfg_batch_id3_addr = 0x07DC,
|
|
|
+ .epoch1_cfg_batch_id3_addr = 0x07E0,
|
|
|
+ .epoch0_cfg_batch_id4_addr = 0x07E4,
|
|
|
+ .epoch1_cfg_batch_id4_addr = 0x07E8,
|
|
|
+ .epoch0_cfg_batch_id5_addr = 0x07EC,
|
|
|
+ .epoch1_cfg_batch_id5_addr = 0x07F0,
|
|
|
|
|
|
/* configurations */
|
|
|
.resume_frame_boundary = 1,
|
|
|
@@ -932,69 +926,68 @@ static struct cam_ife_csid_ver2_path_reg_info
|
|
|
|
|
|
static struct cam_ife_csid_ver2_path_reg_info
|
|
|
cam_ife_csid_lite_880_rdi_3_reg_info = {
|
|
|
- .irq_status_addr = 0x111C,
|
|
|
- .irq_mask_addr = 0x1120,
|
|
|
- .irq_clear_addr = 0x1124,
|
|
|
- .irq_set_addr = 0x1128,
|
|
|
- .cfg0_addr = 0x1800,
|
|
|
- .ctrl_addr = 0x1804,
|
|
|
- .debug_clr_cmd_addr = 0x1808,
|
|
|
- .multi_vcdt_cfg0_addr = 0x180c,
|
|
|
- .cfg1_addr = 0x1810,
|
|
|
- .err_recovery_cfg0_addr = 0x1814,
|
|
|
- .err_recovery_cfg1_addr = 0x1818,
|
|
|
- .err_recovery_cfg2_addr = 0x181C,
|
|
|
- .debug_byte_cntr_ping_addr = 0x1820,
|
|
|
- .debug_byte_cntr_pong_addr = 0x1824,
|
|
|
- .camif_frame_cfg_addr = 0x1828,
|
|
|
- .epoch_irq_cfg_addr = 0x182C,
|
|
|
- .epoch0_subsample_ptrn_addr = 0x1830,
|
|
|
- .epoch1_subsample_ptrn_addr = 0x1834,
|
|
|
- .debug_camif_1_addr = 0x1838,
|
|
|
- .debug_camif_0_addr = 0x183C,
|
|
|
- .frm_drop_pattern_addr = 0x1840,
|
|
|
- .frm_drop_period_addr = 0x1840,
|
|
|
- .irq_subsample_pattern_addr = 0x1848,
|
|
|
- .irq_subsample_period_addr = 0x184C,
|
|
|
- .hcrop_addr = 0x1850,
|
|
|
- .vcrop_addr = 0x1854,
|
|
|
- .pix_drop_pattern_addr = 0x1858,
|
|
|
- .pix_drop_period_addr = 0x185C,
|
|
|
- .line_drop_pattern_addr = 0x1860,
|
|
|
- .line_drop_period_addr = 0x1864,
|
|
|
- .debug_halt_status_addr = 0x1868,
|
|
|
- .debug_misr_val0_addr = 0x1870,
|
|
|
- .debug_misr_val1_addr = 0x1874,
|
|
|
- .debug_misr_val2_addr = 0x1878,
|
|
|
- .debug_misr_val3_addr = 0x187C,
|
|
|
- .format_measure_cfg0_addr = 0x1880,
|
|
|
- .format_measure_cfg1_addr = 0x1884,
|
|
|
- .format_measure0_addr = 0x1888,
|
|
|
- .format_measure1_addr = 0x188C,
|
|
|
- .format_measure2_addr = 0x1890,
|
|
|
- .timestamp_curr0_sof_addr = 0x1894,
|
|
|
- .timestamp_curr1_sof_addr = 0x1898,
|
|
|
- .timestamp_perv0_sof_addr = 0x189C,
|
|
|
- .timestamp_perv1_sof_addr = 0x18A0,
|
|
|
- .timestamp_curr0_eof_addr = 0x18A4,
|
|
|
- .timestamp_curr1_eof_addr = 0x18A8,
|
|
|
- .timestamp_perv0_eof_addr = 0x18AC,
|
|
|
- .timestamp_perv1_eof_addr = 0x18B0,
|
|
|
- .batch_period_cfg_addr = 0x18BC,
|
|
|
- .batch_stream_id_cfg_addr = 0x18C0,
|
|
|
- .epoch0_cfg_batch_id0_addr = 0x18C4,
|
|
|
- .epoch1_cfg_batch_id0_addr = 0x18C8,
|
|
|
- .epoch0_cfg_batch_id1_addr = 0x18CC,
|
|
|
- .epoch1_cfg_batch_id1_addr = 0x18D0,
|
|
|
- .epoch0_cfg_batch_id2_addr = 0x18D4,
|
|
|
- .epoch1_cfg_batch_id2_addr = 0x18D8,
|
|
|
- .epoch0_cfg_batch_id3_addr = 0x18DC,
|
|
|
- .epoch1_cfg_batch_id3_addr = 0x18E0,
|
|
|
- .epoch0_cfg_batch_id4_addr = 0x18E4,
|
|
|
- .epoch1_cfg_batch_id4_addr = 0x18E8,
|
|
|
- .epoch0_cfg_batch_id5_addr = 0x18EC,
|
|
|
- .epoch1_cfg_batch_id5_addr = 0x18F0,
|
|
|
- .secure_mask_cfg0 = 0x24,
|
|
|
+ .irq_status_addr = 0x011C,
|
|
|
+ .irq_mask_addr = 0x0120,
|
|
|
+ .irq_clear_addr = 0x0124,
|
|
|
+ .irq_set_addr = 0x0128,
|
|
|
+ .cfg0_addr = 0x0800,
|
|
|
+ .ctrl_addr = 0x0804,
|
|
|
+ .debug_clr_cmd_addr = 0x0808,
|
|
|
+ .multi_vcdt_cfg0_addr = 0x080c,
|
|
|
+ .cfg1_addr = 0x0810,
|
|
|
+ .err_recovery_cfg0_addr = 0x0814,
|
|
|
+ .err_recovery_cfg1_addr = 0x0818,
|
|
|
+ .err_recovery_cfg2_addr = 0x081C,
|
|
|
+ .debug_byte_cntr_ping_addr = 0x0820,
|
|
|
+ .debug_byte_cntr_pong_addr = 0x0824,
|
|
|
+ .camif_frame_cfg_addr = 0x0828,
|
|
|
+ .epoch_irq_cfg_addr = 0x082C,
|
|
|
+ .epoch0_subsample_ptrn_addr = 0x0830,
|
|
|
+ .epoch1_subsample_ptrn_addr = 0x0834,
|
|
|
+ .debug_camif_1_addr = 0x0838,
|
|
|
+ .debug_camif_0_addr = 0x083C,
|
|
|
+ .frm_drop_pattern_addr = 0x0840,
|
|
|
+ .frm_drop_period_addr = 0x0840,
|
|
|
+ .irq_subsample_pattern_addr = 0x0848,
|
|
|
+ .irq_subsample_period_addr = 0x084C,
|
|
|
+ .hcrop_addr = 0x0850,
|
|
|
+ .vcrop_addr = 0x0854,
|
|
|
+ .pix_drop_pattern_addr = 0x0858,
|
|
|
+ .pix_drop_period_addr = 0x085C,
|
|
|
+ .line_drop_pattern_addr = 0x0860,
|
|
|
+ .line_drop_period_addr = 0x0864,
|
|
|
+ .debug_halt_status_addr = 0x0868,
|
|
|
+ .debug_misr_val0_addr = 0x0870,
|
|
|
+ .debug_misr_val1_addr = 0x0874,
|
|
|
+ .debug_misr_val2_addr = 0x0878,
|
|
|
+ .debug_misr_val3_addr = 0x087C,
|
|
|
+ .format_measure_cfg0_addr = 0x0880,
|
|
|
+ .format_measure_cfg1_addr = 0x0884,
|
|
|
+ .format_measure0_addr = 0x0888,
|
|
|
+ .format_measure1_addr = 0x088C,
|
|
|
+ .format_measure2_addr = 0x0890,
|
|
|
+ .timestamp_curr0_sof_addr = 0x0894,
|
|
|
+ .timestamp_curr1_sof_addr = 0x0898,
|
|
|
+ .timestamp_perv0_sof_addr = 0x089C,
|
|
|
+ .timestamp_perv1_sof_addr = 0x08A0,
|
|
|
+ .timestamp_curr0_eof_addr = 0x08A4,
|
|
|
+ .timestamp_curr1_eof_addr = 0x08A8,
|
|
|
+ .timestamp_perv0_eof_addr = 0x08AC,
|
|
|
+ .timestamp_perv1_eof_addr = 0x08B0,
|
|
|
+ .batch_period_cfg_addr = 0x08BC,
|
|
|
+ .batch_stream_id_cfg_addr = 0x08C0,
|
|
|
+ .epoch0_cfg_batch_id0_addr = 0x08C4,
|
|
|
+ .epoch1_cfg_batch_id0_addr = 0x08C8,
|
|
|
+ .epoch0_cfg_batch_id1_addr = 0x08CC,
|
|
|
+ .epoch1_cfg_batch_id1_addr = 0x08D0,
|
|
|
+ .epoch0_cfg_batch_id2_addr = 0x08D4,
|
|
|
+ .epoch1_cfg_batch_id2_addr = 0x08D8,
|
|
|
+ .epoch0_cfg_batch_id3_addr = 0x08DC,
|
|
|
+ .epoch1_cfg_batch_id3_addr = 0x08E0,
|
|
|
+ .epoch0_cfg_batch_id4_addr = 0x08E4,
|
|
|
+ .epoch1_cfg_batch_id4_addr = 0x08E8,
|
|
|
+ .epoch0_cfg_batch_id5_addr = 0x08EC,
|
|
|
+ .epoch1_cfg_batch_id5_addr = 0x08F0,
|
|
|
|
|
|
/* configurations */
|
|
|
.resume_frame_boundary = 1,
|
Chandan Kumar Jha