Enable SW2TCL_CMD ring for data on QCN9000, QCA8074 V2/V1
and IPQ6018 targets.
Enabled 4th Tx ring for data enqueue to HW.
Transmit completions for packets from CPU0 and CPU3 are routed to
WBM2SW Completion ring 2.
WB2SW completion ring2 is mapped to CPU3.
Change-Id: Ied4c4704e1f8623e909ad45c547a611de26c7ec5
This is to enhance statics for runtime put/get, which is
to detect if there is mismatch for usage_count.
Change-Id: I24cddb9d10e4cb675c8375cbd0f589c7718bd680
CRs-Fixed: 2647972
Function added to convert given channel number to correct
channel frequency using the Channel center frequency and
populate it correctly inside the radiotap header
Change-Id: Iea2a9ee7d496b2aa0dbf8d6741a32d2dbfa3503d
CRs-fixed: 2637424
The HE GI and HE LTF values are obtained from phy
TLVs in monitor path. The stats used in host have an
enum defined used by other upper layer code.
The radiotap spec defines different set of enums.
Add translation function to convert host stats enum
to radiotap defined enum for sniffer capture purpose.
Change-Id: I8c76adb42b0623e83958f7a37147b74e72b1ce74
CRs-Fixed: 2636051
Support RX 2K jump/OOR frame handling from REO2TCL ring.
(a) configure REO error destination ring register to route 2K jump
/OOR frame to REO2TCL ring.
(b) for 2K jump RX frame, only accept ARP frame and drop others,
meanwhile, send delba action frame to remote peer once receive first
2K jump data.
(c) for OOR RX frame, accept ARP/EAPOL/DHCP/IPV6_DHCP frame, otherwise
drop it.
Change-Id: I7cb33279a8ba543686da4eba547e40f86813e057
CRs-Fixed: 2631949
Fix macro name to enable delayed register writes.
Donot use delayed register writes for non fastpath access.
Change-Id: I235116ab3df5cb26bbfbb72de4ac6ed4b363a13a
CRs-Fixed: 2645865
As a part of enabling IPA pipes, the WBM2SW2 head
pointer register is written with the number of
buffers which have been allocated initially. This
register write is a critical one and failure in
writing this register can be fatal.
Confirm the written value, when initializing
the HP register for WBM2SW2 (for IPA).
Change-Id: Ib2da3a7aa6096375cf64857721619f47c50658de
CRs-Fixed: 2620750
Restrict lock hold time in transmit path to only ring access time.
Also store lmac_id in vdev to avoid multi indirection.
Arrange fields in data structure for better alignment in data path access.
Change-Id: I1d32880ed88be486171be46281ec180d2a4906bf
In QCN9000, wbm release ring has msdu continuation bit
support for invld peer MPDUs. Host needs to form SG
buffer for packets with msdu continuation bit set
Change-Id: Ica03c78068d32d2c8dc609b9a50298b91dd48c0a
Channel Frequency Response(CFR) feature requires PPDU information
for correlation with CFR data. Host subscribes for the relevant PPDU
status TLVs via the Host RX monitor status ring. During monitor status
ring reap, all information needed for CFR correlation is accumulated
in a HAL PPDU structure and delivered to WDI event subscribers. Add
this change for HSP.
Change-Id: If3060271cf2923171487d30f99f2ab5c55370601
CRs-Fixed: 2634766
In HSP platform, ring index 0 is for spectral scan, and ring idex 1 is
for CFR capture. Extend max rings to 2 and support CFR capture.
Change-Id: I02b39dd626b67172123bc5e77173d50a132fc735
CRs-Fixed: 2634636
Initial changes for ipq5018 compilation.
Added device ID and target type checks for ipq5018 traget.
Change-Id: Ib86a371fbe66749fcb6d114e7a4a9931b684e03d
Currently hal_info, hal_err etc are using QDF_MODULE_ID_TXRX to print.
Since HAL is a separte module, use QDF_MODULE_ID_HAL.
Change-Id: I2345e1b333ef1f7a4808f5417657ac58da071475
CRs-Fixed: 2636911
Add HAL layer changes for full monitor mode.
Define HAL API and Data structures to read sw_monitor_ring
descriptor.
CRs-Fixed: 2630982
Change-Id: I015fa106d9da74222bef092d50e96fc70a117a4a
Build failure happen when use the incorrect print format for
pointer. The timer type should not be used for time difference.
Use %pK for pointer format, and change the variable type to
uint64_t for delta_us.
Change-Id: I7da553ee2a770e4498a23f16d5187dec74357635
CRs-Fixed: 2639868
Fix the issue on block ACK on response to BAR frame.
Parse BAR frame received from monitor destination ring and
generate block ack frame from BAR frame and previous block
ACK frame.
Change-Id: Ifc242b3850630aa25827b003a1e2078a9228358a
In case the bus is in low power mode, the register writes (followed by a
memory barrier) may take a long time (~4ms). This can cause the caller
to block till the PCIe write is completed. Thus, even though PCI
writes are posted, it can still block the caller.
Hence, in case the bus is in low power mode (not in M0), or not in high
throughput scenarios, queue the register write in a workqueue. The
register write will happen in the delayed work context. In other cases,
i.e ,when the bus is not in low power mode or in high thoughput
scenarios, do the register writes in caller context.
Change-Id: Idf218e4581545bc6ac67b91d0f70d495387ca90e
CRs-Fixed: 2602029
For qca6750, update the SHADOW REGISTER OFFSET value and
fix the compilation issue.
Change-Id: Ic4b44c1c40e62ddcc50c0a66d37c0663a70b5c54
CRs-Fixed: 2633044
Write TID-no correctly for DSCP-value if
2 consecutive registers are needed to configure
the mapping.
Change-Id: I857f95e2d1bda0214a32b2802f1dcc460be87085
In current monitor status ring implementation,
on pdev_attach, (srng->num_entires – 1) entries
(to keep one entry slot between hp and tp)
are replenished and last entry is not replenished to HW.
With qcn9000 monitor mode HW enhancements, status and destination ring
can be made lock-stepped.
for qcn9000 lock step is achieved by making monitor status ring
follow the monitor destination reap for a PPDU
However in existing flow during attach monitor status replenish logic
do not fill last entry but is filled up during first subsequent reap.
for first ppdu, i.e. after reaping destination ring,
when status ring is reaped, as first entry (hp = srng->num_entires – 1)
in status ring is NULL, so lock-stepping is not achieved.
To address this issue for qcn9000 as well as HK:
a. Replenish last entry in monitor status ring during attach
b. Modify src srng peek API to peek it from hp+1 entry
c. Introduce new HAL API get cur desc and move next
CRs-Fixed: 2626049
Change-Id: I7da6cd6006243cbca2151da22a31a6f5ed0015f3
Intercept monitor destination path for NDPA frames,
use it to generate noack frames for tx capture.
Change-Id: Ia54196bd84729a7863954b6deec7e02b52f23556
CRs-Fixed: 2605672
Handle minidump logging using dynamic
configurablity options. Data structures
to be logged in minidump can be configured
using internal INI file.
Change-Id: I99f12b3f98c4a9c0e15c3e5d611019e6b8d0909a
Maintain a history of the register writes which
have failed. The failure of register write is
determined by reading back the register after
writing a value to that register. If the read
value does not match the value which was written
then it is termed as a failed register write.
Change-Id: Ic3423c2cbd74bf498c0d3dd8ee7ce4231054541a
CRs-Fixed: 2624475
Sometimes the register write in windowed region
are not going through, thereby retaining the
previous value, which can be incorrect for a
certain mode of operation for the driver.
This kind of incorrect register values, due to
a register write not succeeding, can lead to
unwanted issues. Also the simple logging of
any such occcurence can be over-written in the
logs, thereby going unnoticed.
Add a HAL level statistics to maintain the
count of such failed register writes.
Change-Id: Ib5e98705c23f0c916cb85f518576663710eb30e0
CRs-Fixed: 2611839
wifi load failed due to unknown symbol in qca_ol
Add export symbol inside compile time macro
Change-Id: If1bb24084a6f95678b51bb85aaa0b8a87df3d50b
CRs-Fixed: 2621904
Use static window for accessing UMAC and CE register in qca6750. For
UMAC and CE register access, separate static window is mapped. Host
accesses these registers using relative offset to window address.
Change-Id: I7940336579553f05a11f1379f635689d08508c56
CRs-Fixed: 2617684
Command ring is now renamed to credit ring on QCN9000
and used for credit based flow.
Renaming the ring to give meaningful name.
Change-Id: I726aed19477fcfb256e4e0cca8ddb9389035b58c
CRs-Fixed: 2562640
Update CE registers offset during hal srng configuration
and configure CE IRQ for qcac6750.
Change-Id: I4fd3d37783361f0029c7ef80e32425f8790d1250
CRs-Fixed: 2617699
For qcn9000, As part HW enhancements, PPDU_ID is sent
in reo_entrance_ring descriptor instead of RX_MPDU_START
tlv. Add support to read ppdu id from descriptor.
Modify existing hal API hal_rx_hw_desc_get_ppduid_get ()
arguments to pass RxDMA ring HW descriptor.
Usage:
a. Use hal_rx_hw_desc_get_ppduid_get () -
to get ppdu id from rx_tlv_hdr or hw descriptor based on target.
for qcn9000, this API gets ppdu_id from HW descriptor,
for other platforms, gets ppdu_id from rx_tv_hdr
b. Use hal_rx_get_ppdu_id () - to get ppdu_id from rx_tlv_hdr
Change-Id: I5838227c12cde50cbb2a9da7a0d8056b8b9b7ef5
Move flow learning and operation HAL macros from header file hal_rx_flow.h
to hal_rx_flow.c.
1) hal_rx_flow.c conditionally compiled in based on the feature
2) Function implementations are too big to be defined in hal_rx_flow.h
Replicate hal_rx_flow_setup_fse specific to FISA Flow programming.
Implement function to dump the FT entries.
Change-Id: I7db943495eecfc064c4b696939da83d1d8ed9280
CRs-Fixed: 2599917
Added new qca5018 hal folder to add ipq5018 specific changes.
This includes interface files to access ipq5018 hal registers.
Change-Id: I7e19dc7c8719fa175695b268dc904fb4521a3330
8074 and QCN9000 coexist, so make hal_rx_msdu_packet_metadata_get()
as chip specific
Change-Id: I5b0b5e7f8915d12d4b267d5f07b03b47bb49a83f
CRs-Fixed: 2595314
Move HAL_RX_MSDU_END_DA_IDX_GET macros to chip specific header file.
Fixing compilation failure for 6490 and 6750.
hal_rx_msdu_packet_metadata_get_generic need not be chip specific,
macros defining the function are already chip specific.
Change-Id: I940a289662bdeddfbf99fae2a80d7796334832e7
CRs-Fixed: 2595314
Rather than extracting msdu end pkt tlv information per field basis
during fast data path, extract msdu end pkt tlv information at once
and store in local structure.
Change-Id: I0877ba4f824d480cc0851c72090f010852d0d203
Add a framework to configure varying buffer size for both data and monitor
buffers.
For example, with this framework, the user can configure 2K SKB for Data
buffers, monitor status rings, monitor descriptor rings, monitor
destination rings and 4K SKB for monitor buffers through compile time.
Change-Id: I212d04ff6907e71e9c80b69834aa07ecc6db4d2e
CRs-Fixed: 2604646
fix the issue for block ack/ack for tx capture mode.
1. Hanndle BAR frame.
2. set rate for ACK frame.
3. Check block ack session and use block ack if block
ack session is established.
4. no ACK for broadcast probe request.
5. not ack if the ack policy is set to no ack in qos control.
Change-Id: I4f22c1c976334978fb971b42319fb3a6e43a00c2
Define shadow register value as 0 in else case where none
of the chips supporting SHADOW configuration are enabled. This
is needed for low memory configuration profiles where
QCN9000 and QCA6290 are undefined.
Change-Id: I6281568e830b506707aeb96d3ea03811cc1de8a7
Force wake request is sent before register write. If this req
fails check if FW is down or host is in recovery before
asserting.
Change-Id: I6d31b1f95b68ae4e462f59ed32ed933de55cacae
CRs-Fixed: 2601364
Add monitor mode support to capture packets over 6GHz frequencies by
getting capture frequency from pdev.
Change freq type to qdf_freq_t.
Change-Id: I7b6edc43e254dc98a3c2939c369874bec9d16ddd
CRs-Fixed: 2568970
the current HAL API is to read the WBM internal error
bit from the wbm release ring descriptor is always taking
HKv1 HW structure. But the wbm_internal_error bit
placement has changed from HKv2, for this reason we have
to use target specific HAL API.
Change-Id: I44789180754ca21ae59650b6d8620321a1f12569
