Add below change:
1 log level change from error to debug level in
hif_pci_runtime_pm_warn.
2 Change warn_on to bug_on in hif_pci_runtime_pm_warn.
3 change pm_stats to atomic
4 record last 128 caller both for get/put
Change-Id: I2dae883dfaed22812445c5d50920fb363b9e0ea7
CRs-Fixed: 2638863
Use pfrm_disable_irq_nosync/pfrm_enable_irq APIs inplace
of disable_irq_nosync/enable_irq to enable/disable IRQ.
Change-Id: I4002a0c8efddac7211ab0c7e8b92356b0c7bc7bf
CRs-Fixed: 2636512
From Genoa firmware request, in order to improve
the IPA througput, increasing the number of copy
engine 8 entries and other nbytes values.
Change-Id: Ib1ae170c3b3f5af61d03ad8a60bc616b7a58a725
Add HIF APIs to prevent or allow link to go into low power states. The
current implementation uses PLD APIs to make the needed configuration.
Change-Id: I22efb4bcf902f9aff674ed1872f4f23bef508aae
CRs-Fixed: 2602029
For qca6750, update the SHADOW REGISTER OFFSET value and
fix the compilation issue.
Change-Id: Ic4b44c1c40e62ddcc50c0a66d37c0663a70b5c54
CRs-Fixed: 2633044
Currently, Genoa CE4 is using interrupt mode. Host will not require
IRQ base on current CE configuration and change below:
"Change-Id: Icabe68298737dc412949484f6d3fdcd8c05910d5", which cause
no IRQ handle of tx completion and source ring full, blocking
TX finally. To unblock TX, correct configuration of CE4.
At the meanwhile, this issue expose another problem that the polling
mode seems doesn't work. Will scope it on another thread.
Change-Id: I31eed8806b939a12503bb4ddd8b9dec85f3c3540
CRs-Fixed: 2602888
Since it support PCIe shadow register for QCN7605,
and these shadow register also falls below 512K,
which can be used for IPA write directly without
windowing. So don't use the temporary PCIE_PCIE_SCRATCH_2
for IPA GSI write now, insteadly, passing the correct shadow
register of copy engine 5 to IPA.
Change-Id: Ica3a502b96e98ee6c07c1032760b5dcb512957d8
Add HIF changes for supporting the newly added USB bus type
for Genova.
FW team need athdiag tool to operate FW information. Host
driver need to pass the command and result between athdiag
tool and FW.
Change-Id: I6158a9f8c723a797d39beca09a913c7cb9e10025
CRs-Fixed: 2595515
Allocate a buffer of size 4096 bytes for each buffer
posted to CE2 source/destination ring.
Change-Id: I0beb1e4e87c19508917e8564b441819031be2065
CRs-Fixed: 2619899
QCN7605 has 2 set of shadow registers, WCSS block and PCIe block.
As PCIe shadow register are at power domain boundary, enabling
PCIe shadow register for QCN7605.
Also PCIe shadow register falls below 512KB, no need to use register
windowing which is required to get it access from IPA FW
Change-Id: If18d2d0a3f16f492b3c32449695e70c2b9942375
CRs-Fixed: 2623853
Currently, the IPA GSI can't update the index to copy
engine 5 write index register since such kind of
register address is above 512k, so as a workaround,
we use PCIE_PCIE_SCRATCH_2 to replace copy engine 5
write index register for IPA update the index. And then
WLAN firmware will poll this register to check if this
index update or not, if updtae, WLAN firmware will be
as agent to update the index to real copy engine 5 write
index register, and then the data from IPA to WLAN will
work. Before the real fix is ready, we use this method
for workaround.
Change-Id: I383a7d52f5685b633f1bd44659b11f30231c8ca8
Update CE registers offset during hal srng configuration
and configure CE IRQ for qcac6750.
Change-Id: I4fd3d37783361f0029c7ef80e32425f8790d1250
CRs-Fixed: 2617699
Genoa FW use the hardcode 128 for ce5 destination ring
entries, so change host code to follow up with it.
Change-Id: I1b7e70f8244efc3d3ca3dc659fb3d7687828b9c4
Fixing compilation issue for USB interface on non-
msm platform by adding pld_common.h header file in
if_usb.c which contains cnss pld specific definitions.
Change-Id: I67b3fd29bb21d827618655f337f38beb683a4c41
CRs-Fixed: 2615907
Added new qca5018 hal folder to add ipq5018 specific changes.
This includes interface files to access ipq5018 hal registers.
Change-Id: I7e19dc7c8719fa175695b268dc904fb4521a3330
This is a public API, so move it outside to hif.h file so it can be
used elsewhere as well.
Change-Id: Ic870cf804df69f6d7bb5a792da662759d687e0ed
CRs-Fixed: 2616491
Replace QCA_WIFI_QCA8074_VP with CONFIG_WIFI_EMULATION_WIFI_3_0
since VP platform is not being used anymore.
Most of the parameters present inside QCA_WIFI_QCA8074_VP are related
to emulation timeouts. Hence replacing it with a more meaningful flag.
Change-Id: I22a0e5803e765333947f1613b376dcc6bd25b5af
Some areas in other components are directly calling the kernel api
functions to perform runtime PM no idle operations. Create a new HIF
function to handle runtime PM no idle operations.
Change-Id: I8328bc74ccc8e8acd35d7d73ec4cc21094b8f5b2
CRs-Fixed: 2607721
Enable timer and batch count threshold interrupt for CE1, CE2
and CE5 rings through INI and retrieve the parameters through
psoc handle.
Change-Id: Ifa6cd768ed41ded46cae652ad7c910ffa62f2310
CRs-Fixed: 2593531
Change enable_runtime_pm from bool to uint8_t in correspondence to
changing CFG_INI_BOOL to CFG_INI_UINT for enabling runtime PM.
Change-Id: Ib5031ada43fac864d933cdfee875593f896b2a62
CRs-Fixed: 2603918
Do not get/put the pm_runtime if RPM is not enabled to avoid the WMI
command sending block.
Change-Id: Id6cddc4d5b6322fea063f08a1b641034ba0272d9
CRs-Fixed: 2587797
Add support to track tasklet execution and total time in different
buckets for debugging purposes
Change-Id: Ide459c385b2a44c0f16d05b37879c8b462782d72
CRs-Fixed: 2589199
HIF layer have kernel calls for interrupt registration
which need to be replaced in case of whunt framework,
as interrupt generation will be simulated by framework
itself, hence adding abstraction to call either kernel call
or whunt calls based on platform bus type.
Change-Id: Ife113d6338defa8e693e761992ce3a1bb9524306
CRs-Fixed: 2582523
To support ROME SDIO card, change in HIF SDIO layer. Without CNSS or
CNSS2 module, it can bring up adapter successfully.
Output few logs in SDIO read and write thread, and optimize HIF
SDIO layer logging.
Change-Id: I96ba731a7fa572131aaaec8ab25d9cffc41ec0b2
CRs-Fixed: 2542051
When HIF_CE_DEBUG_DATA_BUF is enabled for some apis when module is
inserted, it throws unknown symbol error, fix them by exporting the
required apis.
Change-Id: Icf6fc40f7df1c463ad7a6f9eff38adcbdf9276b7
CRs-Fixed: 2593859
The htc connect message buffer is not unmapped,
if the firmware does not send wmi ready event to the
host.
Scenario:
- Host sends htc init command.
- The command is queued into the src ring.
- The firmware has crashed before the Copy Engine
could copy the message to the destination ring
- Due to the above point, no copy completion
interrupt is received.
- The host times out during its wait for the wmi
ready event.
- Hence the htc init command buffer stays unmapped
and unfreed.
As a part of the wma ready event missing cleanup,
the htc connect buffer is not unmapped. Fix this
to avoid missing to unmap the buffer.
To avoid a side effect of sending a completion for
HTC connect command, all the commands are freed in
the htc completion handler in case of SSR.
CRs-Fixed: 2512344
Change-Id: I05026b3cbb764197e6df85c41634002d271a50e5
Reduce the number of CEs used in QCN9000 to 6 since it has only
one mac and requires only 6 CEs. CE7 and CE8 are reserved for FW
and not needed to be configured from host
Change-Id: I989ffdb0219e2628bac5536e25c4cb2dbba6b7fb
Do not request interrupt if DISABLE_INTR flag is set in CE flags.
This check is already present in hif_ahb_configure_irq but is missing in
MSI path.
Change-Id: Icabe68298737dc412949484f6d3fdcd8c05910d5
1. Add hif_force_wake_request API to wake the
mhi and umac before reading/writing the memory region
greater than BAR+4K.
2. Add hif_force_wake_release API to release the
PCIE_PCIE_LOCAL_REG_PCIE_SOC_WAKE_PCIE_LOCAL_REG so the
umac can power collapse again at a later point of time.
3. Add pci stats to dump the force wake status.
Change-Id: Ic6d5463ea0cdb28d9144be61da55e43033b53298
CRs-Fixed: 2478052
UMAC reo full condition is seen in slub debug builds in case of
DL throughput traffic. This is due to host process only 64 packets
per NAPI schedule in case of slub debug builds where in case of
perf builds budget is of scale 4 times. Also the time between two
napi schedules is in order of milliseconds which accounts for the
delay of host reo ring processing. So increase the napi budget
scale to 3 times which make sures host process enough packets per
napi schedule.
Change-Id: I3e134f31277a72056f3d7d5433ed1adeefa433fa
CRs-Fixed: 2563595
During system suspending, the target might request wakeup early to the
host. The host will wakeup the system directly to abort current suspend
to avoid mismatching PM state between host & target.
Change-Id: Icf6e58ff24cbe072ef56aa22820432efb2ca1932
CRs-Fixed: 2559306
Remove EPPING_CE_FLAGS_POLL from poll flags so that interrupt is
enabled for pine.
Change-Id: I8271ab47e75fbe254e0c5d745f861edbda4b07ce
CRs-fixed: 2507441
Add debugging infrastructure to record every event posted to reo
command ring. The infrastructure maintains the record of the last
64 events posted to the ring.
Change-Id: Id56fc352050eb664a64b0abb767f3b4a6b4c3aa3
CRs-Fixed: 2552822
Added change to modify ce flags for Pine.
Also made changes in window enable bit
Change-Id: Id080be53d14450cb6d9376fc810177bce26a2869
CRs-fixed: 2507441
