qcacmn: Pass shadow register address for IPA

Since it support PCIe shadow register for QCN7605,
and these shadow register also falls below 512K,
which can be used for IPA write directly without
windowing. So don't use the temporary PCIE_PCIE_SCRATCH_2
for IPA GSI write now, insteadly, passing the correct shadow
register of copy engine 5 to IPA.

Change-Id: Ica3a502b96e98ee6c07c1032760b5dcb512957d8

hif/src/ce/ce_service.c

@@ -1394,7 +1394,28 @@ bool ce_check_rx_pending(struct CE_state *CE_state)
 qdf_export_symbol(ce_check_rx_pending);
 
 #ifdef IPA_OFFLOAD
-#ifdef GENOA_IPA_WORKAROUND
+#ifdef QCN7605_SUPPORT
+static qdf_dma_addr_t ce_ipa_get_wr_index_addr(struct CE_state *CE_state)
+{
+	u_int32_t ctrl_addr = CE_state->ctrl_addr;
+	struct hif_softc *scn = CE_state->scn;
+	qdf_dma_addr_t wr_index_addr;
+
+	wr_index_addr = shadow_sr_wr_ind_addr(scn, ctrl_addr);
+	return wr_index_addr;
+}
+#else
+static qdf_dma_addr_t ce_ipa_get_wr_index_addr(struct CE_state *CE_state)
+{
+	struct hif_softc *scn = CE_state->scn;
+	qdf_dma_addr_t wr_index_addr;
+
+	wr_index_addr = CE_BASE_ADDRESS(CE_state->id) +
+			SR_WR_INDEX_ADDRESS;
+	return wr_index_addr;
+}
+#endif
+
 /**
  * ce_ipa_get_resource() - get uc resource on copyengine
  * @ce: copyengine context
@@ -1443,51 +1464,10 @@ void ce_ipa_get_resource(struct CE_handle *ce,
 	*ce_sr = CE_state->scn->ipa_ce_ring;
 	*ce_sr_ring_size = (uint32_t)(CE_state->src_ring->nentries *
 		sizeof(struct CE_src_desc));
-	/* 0x0002005c is the offset address of PCIE_PCIE_SCRATCH_2 register */
-	*ce_reg_paddr = phy_mem_base + 0x2005C;
+	*ce_reg_paddr = phy_mem_base + ce_ipa_get_wr_index_addr(CE_state);
 
 }
 
-#else
-void ce_ipa_get_resource(struct CE_handle *ce,
-			 qdf_shared_mem_t **ce_sr,
-			 uint32_t *ce_sr_ring_size,
-			 qdf_dma_addr_t *ce_reg_paddr)
-{
-	struct CE_state *CE_state = (struct CE_state *)ce;
-	uint32_t ring_loop;
-	struct CE_src_desc *ce_desc;
-	qdf_dma_addr_t phy_mem_base;
-	struct hif_softc *scn = CE_state->scn;
-
-	if (CE_UNUSED == CE_state->state) {
-		*qdf_mem_get_dma_addr_ptr(scn->qdf_dev,
-			&CE_state->scn->ipa_ce_ring->mem_info) = 0;
-		*ce_sr_ring_size = 0;
-		return;
-	}
-
-	/* Update default value for descriptor */
-	for (ring_loop = 0; ring_loop < CE_state->src_ring->nentries;
-	     ring_loop++) {
-		ce_desc = (struct CE_src_desc *)
-			  ((char *)CE_state->src_ring->base_addr_owner_space +
-			   ring_loop * (sizeof(struct CE_src_desc)));
-		CE_IPA_RING_INIT(ce_desc);
-	}
-
-	/* Get BAR address */
-	hif_read_phy_mem_base(CE_state->scn, &phy_mem_base);
-
-	*ce_sr = CE_state->scn->ipa_ce_ring;
-	*ce_sr_ring_size = (uint32_t)(CE_state->src_ring->nentries *
-		sizeof(struct CE_src_desc));
-	*ce_reg_paddr = phy_mem_base + CE_BASE_ADDRESS(CE_state->id) +
-			SR_WR_INDEX_ADDRESS;
-
-}
-
-#endif
 #endif /* IPA_OFFLOAD */
 
 #ifdef HIF_CE_DEBUG_DATA_BUF