Add support for UCSC block parameters that includes unmult,
IGC/GC modes, CSC coefficients, and clamps.
Change-Id: I3ef4b729e9c973a98d53dc583233bf5e004035fa
Signed-off-by: Alisha Thapaliya <quic_athapali@quicinc.com>
Enabled compilation of msm_drm with mm-drivers components.
Change-Id: Id2f15b314748f9a1a9966625cea98fa4b3855e87
Signed-off-by: Alex Danila <quic_eadanila@quicinc.com>
This change fixes the copyright in gki_pineappledispconf header
to match lost requirements.
Change-Id: Ic0d7dea7bd943509843c4dbbb403cadbbbb587f6
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
This change enables the WB rotation feature support for pineapple target.
Change-Id: Ib222c2b2996a40c72414c6c3a581916b95ebffd6
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
This change adds support for new dynamic QoS mode for WB rotation
which is required to achieve rotation output available at required
rate to meet real time use case. Though traffic shaper can be
disabled in dynamic QoS mode, part of traffic shaper algo to track
WB operating speed is enabled and WB generates creq priority
based on current ouput rate compared to targetted ouput to help
meeting real time use case requirement.
Change-Id: I98c2dcae53f1b175dc49b40238b9da33e95717a6
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
MDSS 10.0.0 HW is capable to rotate input image in WB hardware
block. WB hardware can only perform rotation of clockwise 90 degrees
and this can be used to achieve the required 2D rotation by adding
appropriate FLIP transformation to the SSPP. This change adds required
software support in display driver to excericse input image
rotation through WB block.
Change-Id: Ia5c2fc84eabb68f29d130333316527b60d02cbc7
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
MDSS 10.0.0 HW supports rotation of input image with
writeback HW but output color formats are restricted to
32 bit uncompressed A5X tile formats. This change exposes
the supported WB output color formats to client for WB
rotation usecase.
Change-Id: Ic52e6ee4ab882b7dad6edd0daa91b593afbcae01
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
This change installs required drm properties for writeback
connector to implement rotation with writeback hw in mdss.
Change-Id: I85ed359d06ff4bafee85a4bfa5b8a99774311e60
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
This change adds support to wait on multiple hardware fences by
creating a fence array so each dpu-client only gets signaled until all
the hw fences going to the same ctl-path are signaled. It also
accounts for if a fence is a fence array.
Change-Id: Iba4b1d2b7322aea64dc197ca7655920b79dbb919
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
Add logs to track the read/write line counters
and tear check configuration during key events.
Change-Id: Ife8afecc63a9008a8d9fc746d0ec8579a311b335
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
The register offsets are decremented instead of incrementing during
the logging of registers through the debugfs option. Fix it to be
incremental to help in debugging.
Change-Id: Iefc98c40143554fa7169ff220793431d774f57ce
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
The cwb_enc_mask is set by the wb phys encoder during the validate
phase and this is in-turn used during the commit phase. During
seamless transition cases like poms with cwb, the encoders are
disabled and then enabled back after the validate phase. The cwb
flags are reset during this time leading to issues. Cache the flag
and reapply it during the modeset to avoid this case.
Change-Id: I5df1be18a5e30bb1107dc0f2e87d771a735f1ab6
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Set the boolean property to enable second dedicated
CWB feature on pineapple hardware.
Change-Id: Ibacf0ec327c5d6d803f1fc5211dedb3a591b441a
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
For second dedicated CWB pingpong blocks, the overflow irq needs
to be mapped properly to existing IRQ handlers.
Change-Id: I7630766d1865f7ad7079947185ef4ae629d71f3e
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
Update the hardware blocks and corresponding APIs
to configure new D-CWB data path. Add new hardware
pingpong blocks that are dedicated for second DCWB.
Change-Id: I529c24ac5aa483f30b6c9e7653eb1713c6b8fb8a
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
This change adds a missing break in the switch-case logic.
Change-Id: I6eb1eb9c2532187803c956e590eb5353f3fc9c3d
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
The memblock_free API has been updated to return void. This
change removes the check on return and passes the pointer
address in correctly.
Change-Id: I8b60c8d3c5e3e8c2f94e33015c2c03686a556807
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
This change adds includes for <linux/file.h> required for the
display driver in kernel 5.19.
Change-Id: Ibe5401997b43844b692869ebb6d28faa7bcb7740
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
This change implements the drm_plane_funcs API format_mod_supported
necessary to correctly check if format modifiers are supported.
Change-Id: I39a26f7b053c44ef7577401d88e7cf6934c198f8
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
This change includes linux/delay.h to import the udelay and
usleep_range APIs.
Change-Id: I6ed406cb0f83aebf682420a53b44da72d7ec0456
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
This change updates the include file path for necessary dp
and dsc headers that have moved in upstream kernel.
File path changed in upstream:
include/drm/display/drm_dp_aux_bus.h
include/drm/display/drm_dp_dual_mode_helper.h
include/drm/display/drm_dp.h
include/drm/display/drm_dp_helper.h
include/drm/display/drm_dp_mst_helper.h
include/drm/display/drm_dsc.h
include/drm/display/drm_dsc_helper.h
include/drm/display/drm_hdcp.h
include/drm/display/drm_hdcp_helper.h
include/drm/display/drm_hdmi_helper.h
include/drm/display/drm_scdc.h
include/drm/display/drm_scdc_helper.h
Change-Id: Icb9a227c7464061f68fe60cbda6d93858fa768c5
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
This feature enables using all available bits when ICH
error calculations are made. This improves precision and
image quality when there are more than 8 bits per component.
Change-Id: I851f05418283d0e731332d4069e3b6e57487b9a3
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
This change adds support for INTF TE using 32 bit values and
single update per TE. These features help ensure that during
QSync mode the TE does not overrun in certain late trigger uses.
Change-Id: I893d0cde81320c3f17604694a4d8ee52b29a9425
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
Currently, the driver uses the panel frame count along with
mdp vsync timestamp which can be unreliable if there are any
latencies. This change adds support to use mdp vsync frame
count, if the hardware supports it.
Change-Id: I784d4f4e525212269371a40071bcb912181cba9f
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
This change adds pineapple mdss revision and enables features
based on the hardware capabilities.
Change-Id: I930e1ffd8e070f5bd258e5d3e441a966ade5f760
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
This change adds dsi display ramdump support when DEBUG_FS
is not enabled.
Change-Id: Ic6659a9380acd5eb55a3270d3e3b7016a9cd2bd7
Signed-off-by: Narendra Muppalla <NarendraM@codeaurora.org>
LTM block should be disabled when encoder is being disabled to avoid
display hang when all driver clients have been closed.
Change disables LTM hardware block when encoder is disabled.
Change-Id: I279296b566ab93c302e6166b6fa4b7197c2cc0ab
Signed-off-by: Gopikrishnaiah Anandan <quic_agopik@quicinc.com>
In the current code if there is a switch from DSC to non-DSC
mode, all the DSC blocks attached to the sde_encoder are not
cleaned up properly. Due to this, during virt disable these
DSC blocks are disabled and flushed resulting in underruns
on other ctl paths which might be using them. This change
properly cleans up all the dsc/vdc attached to the sde
encoder to avoid such issues.
Change-Id: Ie644701cbda6b4d056bc7ef30300be96096c5214
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
