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Автор SHA1 Повідомлення Дата
qctecmdr
bc9f90b65c Merge "disp: msm: sde: reset mixers in crtc when ctl datapath switches" 2021-12-09 05:06:37 -08:00
qctecmdr
d9a891d5ff Merge "disp: msm: dsi: set qsync min fps list length to zero" 2021-12-09 05:06:37 -08:00
qctecmdr
d58ff8053f Merge "disp: msm: sde: update vm state atomic check for non-primary usecases" 2021-12-08 23:57:49 -08:00
qctecmdr
f9eb7a143c Merge "disp: msm: sde: reset CTL_UIDLE_ACTIVE register only if uidle is disabled" 2021-12-08 23:57:48 -08:00
Abhijit Kulkarni
fb15930280 disp: msm: sde: avoid race condition at vm release
This change acquires the vm lock before pre-releasing the
dependent drivers. This avoids any race condition on any
parallel async commands transfers scheduled on connector
drivers. Additionally the main irq line is only disabled
after the pre-release to allow any ongoing transfers
to complete.

Change-Id: Ic0bffc93ebb1b69fbd8d1f096b320a86ad84c857
Signed-off-by: Abhijit Kulkarni <quic_kabhijit@quicinc.com>
2021-12-08 12:52:26 -08:00
Mahadevan
e0d90143fd disp: msm: dsi: set qsync min fps list length to zero
In certain usecase where qsync is enabled without qsync
min fps list, incorrect list length might cause issues
while populating modes. This change sets qsync_min_fps
length to zero if its empty which resolves such issues.

Change-Id: I23083d8fd9610665dad63188f5d2db7eb6b23ee1
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
2021-12-08 19:33:12 +05:30
Jayaprakash Madisetty
8b01e6124e disp: msm: sde: reset mixers in crtc when ctl datapath switches
This change reinitializes the sde_crtc->mixers when CTL
datapath switch occurs during mode set and RM allocation
of CTL hw block is changed. This initialization is required
for CTL_LAYER programming to trigger on the new CTL allocated
from RM.

Issue case:
1. Primary Display is using CTL_0 and it is reserved.
2. Secondary Display is using CTL_1. On suspend, RM adds
   CTL_1 into the free list.
3. External Display is powered on, RM allocates CTL_1 hw blk.
4. Secondary Display is powered on, RM allocated CTL_2 hw blk.
5. External Display is suspended/unplugged, RM adds CTL_1 into
   the free list.
6. When any mode_set(say fps switch) occurs on secondary, RM
   allocates new resources and CTL_1 is allocated.

sde_crtc->num_mixers is non zero, so all the layer programming
happens on CTL_2, but CTL_1_FLUSH bits are programmed causing
hw timeout issue.

Change-Id: I5f1f52b7673740c48b249ab4d36e80b7a1d3db96
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
2021-12-08 11:28:43 +05:30
Yashwanth
093d93ed58 disp: msm: sde: update vm state atomic check for non-primary usecases
If vm has already transitioned from primary to trusted,
triggering a wb/secondary display commit will result in
crash since hw is not owned by the vm. This change adds
necessary changes to fail atomic check in such usecases.

Change-Id: Ic9886d479726c27d1072d12304a87f3bf5deeb76
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
2021-12-08 08:44:39 +05:30
Yashwanth
b9b744a123 disp: msm: sde: reset CTL_UIDLE_ACTIVE register only if uidle is disabled
This change sets CTL_UIDLE_ACTIVE register whenever uidle
is enabled and resets it only when uidle is disabled.

Change-Id: I0393d1585df4fdb79a844d04df62ac9eda949232
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
2021-12-07 14:20:33 +05:30
qctecmdr
2a867bb340 Merge "disp: msm: add display config support for parrot" 2021-12-05 04:44:36 -08:00
qctecmdr
d72a4a4f0c Merge "disp: msm: dp: add support for 4nm DP PLL" 2021-12-05 04:44:36 -08:00
qctecmdr
e329cf3904 Merge "disp: msm: dsi: allocate priv info and bit clk list per fps" 2021-12-05 04:44:35 -08:00
Soutrik Mukhopadhyay
aa0eacb522 disp: msm: dp: fixed version check 4nm target
Changes include support to correct the version
check for DP PHY changes for 4nm target.

Change-Id: Ib891d43bd5db10edc4b49a70f7a3b8af073167cd
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
2021-12-03 17:47:25 +05:30
Srihitha Tangudu
f288c1248d disp: msm: add display config support for parrot
Add display config support for compilation on parrot target.

Change-Id: I994b18687187f89b2794a886286280901ca44edb
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
2021-12-01 14:37:16 +05:30
Soutrik Mukhopadhyay
bbc87c5dde disp: msm: dp: add support for 4nm DP PLL
Changes include support for 4nm DP PHY and DP PLL.
Added dp_pll_4nm.c file with register programming
sequences for DP PHY and PLL.

Change-Id: I104cf69964904c9a47a17e75a84df011d7994c9f
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
2021-11-27 09:39:07 +05:30
qctecmdr
79cf605ddc Merge "disp: msm: increase size of sde_kms_info" 2021-11-25 20:20:39 -08:00
Soutrik Mukhopadhyay
2bc4fbcd94 disp: msm: dp: add DP PHY support for 4nm target
Changes include support for specific DP PHY
registers and related code changes for 4nm
target.

Change-Id: I9b349e47ff057421fa465a59e1206fd09f7e367a
Signed-off-by: Soutrik Mukhopadhyay <quic_mukhopad@quicinc.com>
2021-11-24 21:33:45 +05:30
Kashish Jain
c079b51c81 disp: msm: dsi: allocate priv info and bit clk list per fps
Currently, in dsi_display_get_modes, priv_info, rates,
front_porches and pixel_clks_khz memory is allocated for each
timing node and the same memory is copied for each supported fps.
The values of front porches calculated to maintain constant fps for
each bit clk rate gets overwritten with the values for last fps in
the dfps list. But the values of front porches should be different
in case where DFPS and dynamic clock are both supported either by
vfp approach or hfp approach. To fix this, allocate memory
separately for each fps.

Change-Id: Ibf753aa8cca8d77b02b20785b5435f1aba05106e
Signed-off-by: Kashish Jain <kashjain@codeaurora.org>
2021-11-21 23:51:10 -08:00
qctecmdr
ae1d2e9c54 Merge "disp: msm: sde: deprecate idle notify work scheduling" 2021-11-20 00:19:10 -08:00
qctecmdr
80a394d31a Merge "disp: msm: sde: update uidle_db_updates in both enable/disable cases" 2021-11-17 01:00:40 -08:00
qctecmdr
af3b57299d Merge "disp: msm: sde: fix traffic shaper prefill calculations" 2021-11-17 01:00:40 -08:00
qctecmdr
2eaf8739f0 Merge "disp: msm: enable dsc support for 422 with 10bpc and 8bpp" 2021-11-16 14:01:20 -08:00
Raviteja Tamatam
d098764f5b disp: msm: sde: update uidle_db_updates in both enable/disable cases
uidle_db_updates are generated when CTL_x_UIDLE_ACTIVE is set to 1.
It needs to enabled in both uidle enable and disable cases.
CTL_x_UIDLE_ACTIVE is set to 0 only in cases where uidle configuration
is not updated.

Change-Id: If7655e4eae351bac248f0906c473cdfaf93f2b8a
Signed-off-by: Raviteja Tamatam <travitej@codeaurora.org>
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
2021-11-15 13:12:58 -08:00
Manaf Meethalavalappu Pallikunhi
479a5292e6 disp: msm: limit display brightness max cooling device level
Based on panel hardware support, display brightness levels can
be very high value. This high value display brightness cooling
device levels can cause exceeding PAGE_SIZE for cooling device stat
buffer. It leads to buffer failure for cooling device stat feature.

Limit display panel mitigation level max to 255. If hardware
supports more than 255, then scale brightness levels fit
into above limit.

Change-Id: Ieeee4ff2aa5cd884819b30b4fd9839e48ac4d804
Signed-off-by: Manaf Meethalavalappu Pallikunhi <manafm@codeaurora.org>
2021-11-15 05:25:37 -08:00
qctecmdr
61963b0791 Merge "disp: msm: update rsc vsync timeout value dynamic" 2021-11-14 06:03:48 -08:00
qctecmdr
195baab07b Merge "disp: msm: sde: add check for sunlight visibility scale" 2021-11-14 06:03:48 -08:00
Prabhanjan Kandula
8bccb3e212 disp: msm: enable dsc support for 422 with 10bpc and 8bpp
Add DSCv1.2 native 422 format with 10bpc and 8bpp config
and format specific fixed rate control parameter table
entries as per the systems recommended settings.

Change-Id: Ibd1a5203be2c59f4699537a31f9ae6d69bcfe5ab
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
2021-11-11 16:36:55 -08:00
qctecmdr
99f4b07f1d Merge "disp: msm: sde: send event on trusted vm transition" 2021-11-11 14:24:25 -08:00
qctecmdr
6aeec823b3 Merge "disp: msm: dp: clear all dp interrupts before deinit" 2021-11-11 14:24:25 -08:00
qctecmdr
b5da8ebb6a Merge "disp: msm: dp: check for active panels ptr before cleanup" 2021-11-11 10:12:37 -08:00
qctecmdr
d0b2b45c89 Merge "disp: msm: dp: reduce hdcp error level for inactive state" 2021-11-11 10:12:37 -08:00
Yashwanth
a5382aff7e disp: msm: sde: deprecate idle notify work scheduling
This change deprecates idle notify work for video mode
since idle timer will be maintained by userspace.
As part of idle notify work, syscache state is changed from
CACHE_STATE_NORMAL to CACHE_STATE_PRE_CACHE along with
notifying to the userspace. This change removes
CACHE_STATE_PRE_CACHE in the state machine and state is
updated from CACHE_STATE_NORMAL to CACHE_STATE_FRAME_WRITE
whenever the cache property is set.

Change-Id: If3b2c34be954cb625aca76da81fd854c077a8250
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
2021-11-11 11:07:54 +05:30
Rajkumar Subbiah
29534b6d5c disp: msm: dp: clear all dp interrupts before deinit
If there are any uncleared DP interrupts before deinitialing
and turning off the clocks, the interrupt might get stuck at
the MDP level and can't be cleared without turning the DP
clocks back on. To avoid this situation, this change clears
all the interrupts before turning off the clocks.

Change-Id: Id13b102fa81c85f92ae8c1d11ffaf7d5bad5fd12
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
2021-11-10 17:46:31 -05:00
Ping Li
dd2e1fd03f disp: msm: sde: add check for sunlight visibility scale
Add check to clip the sunlight visibility scale to an upper limit of
MAX_SV_BL_SCALE_LEVEL * 4.

Change-Id: I8cc7bf8fba90e115d046ec030983801ce6d93c1d
Signed-off-by: Ping Li <pingli@codeaurora.org>
Signed-off-by: Yuchao Ma <yuchaom@codeaurora.org>
2021-11-10 09:43:35 -08:00
Rajkumar Subbiah
6c8c95f99e disp: msm: dp: add qos vote during hdcp authentication
HDCP authentication has strict timing requirements and if the
display is on static screen during this time, it is possible
that SDE removes the QOS vote when it detects static display,
thereby affecting the hdcp authentication process.

This change adds qos support in dp driver to vote exclusively
for DP. If valid QOS settings are provided in dtsi, then the
driver adds the vote when it starts authentication and removes
the vote when authentication is completed.

Change-Id: I1d8bc098d0857b13fdf1ca089b6dd2d3f381bdb8
Signed-off-by: Rajkumar Subbiah <quic_rsubbia@quicinc.com>
2021-11-09 16:56:58 -05:00
Sandeep Gangadharaiah
1025b3c40a disp: msm: dp: reduce hdcp error level for inactive state
During an HPD, HDCP IRQ handler prints error log and exit
if HDCP state is inactive or authentication failure.
Inactive state is a benign error and auth failure will be
reported by hdcp kernel module. This change will downgrade
this error log to debug log.

Change-Id: I2a64e3c94a6661db70e93d07f5e3608202fe8871
Signed-off-by: Sandeep Gangadharaiah <sandgang@codeaurora.org>
2021-11-08 21:31:43 -05:00
Sandeep Gangadharaiah
ce678e896e disp: msm: dp: check for active panels ptr before cleanup
During a probable race condition where usermode is triggering
a delayed cleanup, this instance would be empty leading to a null
pointer dereference. This change will add protection around this
pointer.

Change-Id: I8e90a1ba3ca925f08678e5fa67616420204edae7
Signed-off-by: Sandeep Gangadharaiah <sandgang@codeaurora.org>
2021-11-08 21:30:33 -05:00
qctecmdr
84973878ad Merge "disp: msm: dsi: Logging Improvement in dsi driver" 2021-11-08 13:26:05 -08:00
Prabhanjan Kandula
6acf9fddfd disp: msm: update rsc vsync timeout value dynamic
Considering requirement for supporting panel refresh rates upto
1Hz current default timeout value is not sufficient. Based on
panel refresh rate update vsync wait timeout value so that
any vsync waits from here on will have adjusted timeout value.

Change-Id: I65af152c4bd3decdd7135a4cc38f54e3bb3d5c92
Signed-off-by: Prabhanjan Kandula <pkandula@codeaurora.org>
2021-11-08 12:17:46 -08:00
Nilaan Gunabalachandran
0ba21c667d disp: msm: increase size of sde_kms_info
With requirements to support an increased number of display modes,
the current size of sde_kms_info is insufficient. This change
increases the sde_kms_info max size.

Change-Id: Ie0f29003732870dad9ce31ee7d484e84f12ba542
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
2021-11-08 14:59:49 -05:00
Yashwanth
50aa3cd210 disp: msm: sde: fix traffic shaper prefill calculations
This change fixes traffic shaper prefill calculations
for prefill count and bytes per clock as per hardware
recommendations in the HPG which are calcualted as below:

ts_ count = ts_end*19200000/fps/(vtotal)

ts_bytes_per_clk = ceil(h_src*v_src*bpp*fps/
			19200000*amortized_pref_rate)

Change-Id: Icc2348421a2124daa3b0056f46d7a6a45021381b
Signed-off-by: Yashwanth <yvulapu@codeaurora.org>
2021-11-08 17:29:22 +05:30
qctecmdr
cb24fd2bc6 Merge "disp: msm: sde: add rev checks for cape target" 2021-11-07 04:30:56 -08:00
qctecmdr
4abbe9ee47 Merge "disp: rsc: update mode-1 threshold config to 1 hz" 2021-11-06 06:25:54 -07:00
qctecmdr
45fd1bf563 Merge "disp: msm: sde: Add spr and demura to handoff features list" 2021-11-05 14:58:29 -07:00
Ritesh Kumar
986c7b1028 disp: msm: dsi: Logging Improvement in dsi driver
This change adds additional logs in dsi driver for
easy debugging of issues related to command transfer.

Change-Id: Ica784bed6c360b2760d6606d625837e23a22410c
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
2021-11-05 02:08:17 -07:00
Ritesh Kumar
13f4082d58 disp: msm: dsi: Fix post cmd tx sequence for read commands
For read commands, wait_for_done() should be called in dsi_message_rx function.
Currently, its being called twice from dsi_message_rx and dsi_ctrl_post_cmd_transfer.
This change adds a check to skip wait_for_done() from dsi_ctrl_post_cmd_transfer.

Change-Id: Icb7ccd0f8dde24c6c26732f7cb92a20bebb26f5d
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
2021-11-05 14:34:58 +05:30
Abhijit Kulkarni
683f6bc6af disp: msm: sde: send event on trusted vm transition
This change sends a notification to user mode after msm_drm
driver releases the mmio and irq resources on trusted vm transition
request. This is required as user mode has no other way to know
when the resources where actually released. User mode driver earlier
relied on retire fence signaling but retire fences are send before
releasing the hw.

Change-Id: Ia218cfcbf398b2de1ad9578fb9baedf348b067df
Signed-off-by: Abhijit Kulkarni <kabhijit@codeaurora.org>
2021-11-04 11:45:25 -07:00
Ritesh Kumar
f2499b50d8 disp: msm: dsi: remove early return from dma_cmd_wait_for_done
In ASYNC wait mode, next command kickoff can happen before previous command ISR execution is
completed in below sequence:

ASYNC command A -> triggered

dsi_ctrl_isr for command A -> fired and executed atomic_set(&dsi_ctrl->dma_irq_trig, 1);

wait_for_done for command A -> returns early as dsi_ctrl->dma_irq_trig is 1

ASYNC Command B -> triggered

wait_for_done for command B -> waiting for cmd_dma_done

dsi_ctrl_isr for command A -> executes complete_all(&dsi_ctrl->irq_info.cmd_dma_done);

wait_for_done for command B -> returns success incorrectly based on complete_all of previous
	command isr and disable_status_interrupt() is not called.

This leads to refcount of dma_done going wrong and dsi_ctrl_isr is not enabled on suspend resume.

To fix this issue, mark command transfer successful only based on complete_all(cmd_dma_done). This
way disable_status_interrupt() will be always called either from dsi_ctrl_isr or wait_for_done().

Change-Id: I0379ea7ff82a1e077b95f6996d11d1722de00936
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
2021-11-04 17:50:11 +05:30
Raviteja Tamatam
f5d5133807 disp: msm: sde: add rev checks for cape target
Add required revision checks from display for
cape target.

Change-Id: Ieb2b0b23462ff122b0090e7c78d8da41fa78fc07
Signed-off-by: Raviteja Tamatam <travitej@codeaurora.org>
2021-11-03 14:25:49 +05:30
Lakshmi Narayana Kalavala
a70e704ef0 disp: msm: sde: Add spr and demura to handoff features list
SPR and Demura modules being disabled when switching back from
Trusted VM to HLOS VM. The change adds the support to restore
the modules to restore to their original state.

Change-Id: I0a843671672179a4bc62da512baf02e911fb50aa
Signed-off-by: Lakshmi Narayana Kalavala <lkalaval@codeaurora.org>
2021-11-02 17:15:56 -07:00