Allow TPG patterns to be displayed on command mode and
video mode panels.
Change-Id: Ie9ba9b404ceb965f8a06d1f19e932dd2e051983b
Signed-off-by: Nisarg Bhavsar <quic_bhavsar@quicinc.com>
Currently we are always initializing PLL registers whenever PLL is
configured. Re-initializing PLL registers during dynamic clock switch in
case of cphy video mode is moving the PLL to some bad state resulting in
display freeze. Avoid this by restricting initialization of PLL registers
to only while turning on the PLL.
Change-Id: I09eacbb37fff4e0e91d226ac08e7d5a2bfbbfe26
Signed-off-by: Srihitha Tangudu <quic_tangudu@quicinc.com>
Reset the wb crop configs from hardware, while disabling
concurrent writeback. This avoids stale configs which
affects the subsequent writeback session.
Change-Id: I4927effd0650bcdca2852a5d72c3e5478683a90f
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Change moves destroying dp audio workqueue outside dp session_lock.
As part of disconnect, USB driver uses atomic notifier which holds
rcu_read_lock and calls into DP disconnect callback which needs
session_lock. If another DP threads holds DP session_lock then
we block RCU operations.
Change-Id: I5d565ca149a3a34ebd5ede4fb662982d87454f16
Signed-off-by: Vara Reddy <quic_varar@quicinc.com>
This change disables hw-fencing for the last commit before
vm transition. This avoids configuration issues if hw-fencing is
disabled in the incoming VM.
Change-Id: I573b7d1665f8cef442168bd0ab83a4b2b6cebbb6
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
During mode validation, DSC book-keeping logic is executed irrespective
of the panel DSC status. If the DSC blocks are available then the
corresponding mode is also set as DSC capable. This step is uncalled for
in a non-DSC panel scenario and might lead to unexpected behavior. This
change checks for panel DSC status before updating DSC book-keeping and
capability for the mode.
Change-Id: I30d6a4d7f3e772b7b13fcca6e318e96372a8becb
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
End section of the display post enable which is supposed
to do the cleanup before exit is also setting DP aux state
as powered on and notifying the connect as successful.
If there is a race condition between connect and disconnect
paths then the code execution would skip to the end section
since display is already disabled. In this case, the DP aux
state would be misleading. This change will set the status
and notify complete only during success case.
Change-Id: I1eca511e042d2dea619bf85fcc28adf9e0cc9536
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
Incorrect debug message is printed when mst con id is set to
the desired conn value. This change skips printing debug
message during this scenario.
Change-Id: Ia7161ff2e7b8fba2da9757360d0c756cbe5ef166
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
Add the missing concurrent writeback output resolution setting,
when destination scaler is enabled with demura tap point.
Additionally, move the dnsc_blur enabled check to the top as
that takes precedence.
Change-Id: Id0e851703ce6e1d8b7caffcdda69d7757222fc59
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Fix UBWC stat error log format to match number of arguments.
Change-Id: I08f1b7a13e370dc7cf3a5a9fc11c089f69e742b5
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
With speculative retire fence, the first commit from HAL depends
on crtc power_on event instead of retire fence signal to unblock
the wait completion. Hence avoid triggering PM suspend/resume if
any of the displays have continuous splash enabled. This will avoid
any state changes in drm_atomic_state and will be inline with
HAL expectation.
Change-Id: I97360e3815651eefdd7e2c1494fa6e882df883b5
Signed-off-by: Jayaprakash Madisetty <quic_jmadiset@quicinc.com>
Print the fence's ctx_id in debug message for timeline reset attempt.
Change-Id: I920105e8e6a088b82fcfeec1be6ba60bac24b02f
Signed-off-by: Grace An <quic_gracan@quicinc.com>
IRQ release needs to be done before mem release as
there can be cases in current implementation where
irq can come just after mem release casuing register
access abort.
Change-Id: If35eef9ae01d5bd3d270aba0bf4f2b8753254a15
Signed-off-by: Raviteja Tamatam <quic_travitej@quicinc.com>
Add check to validate the writeback roi against mode width & height.
When dnsc_blur, destination_scaler, cwb features are not enabled,
the roi should match with mode width & height.
Additionally, add error log for case where dnsc_blur is set without
the HW block reservation.
Change-Id: I9199d5b127eed892ea134f830ecd6f690cb70f77
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Add check in layer mixer to avoid odd values as HW does not
support it.
Change-Id: Ifddd2047c81a016b774712ee52cfceca83374e6d
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
This change sets lm_mask for dp connector based on
number of LMs allocated by RM. This mask will be
used during rm allocation and validation of dcwb
mixers for dp display.
Change-Id: I271af03da560587faf17446471bd6b81bb9e809b
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
This change corrects the conditional check in commit 2859b760a414
("disp: msm: sde: proper allocation of dcwb for LMs") with respect
to DCWB mixer allocation in RM.
Change-Id: I83fd39ed366774f20046b8f9c0e6959116b541ee
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
During dcwb mixer allocation, resource manager allocates
the first available mixer in the free list. In dual display
uses case with 1 1 1 topology if only secondary is running
CWB then, resource manager allocates DCWB0 which leads to wb
timeout due to HW does not have the connection between LM1
and DCWB0. This change allocates proper dcwb for the LMs in RM.
Change-Id: I0c8b04b46ccad5a7d7dd591fbfa3ea0915eccdc6
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
When cwb is triggered on built-in display secondary display
with (1,1,1) topology, improper dcwb_idx value is passed
to pp_dither and CTL registers. This change populates proper
dcwb_idx during pp block dt parsing and passes the same for
programming.
Change-Id: I543eede6f5fd9c2c80799503e3639ea9e89058ca
Signed-off-by: Mahadevan <quic_mahap@quicinc.com>
This change updates atomic check for VM_ACQUIRE transition
only for android VM since in trusted VM, vm_owns_hw is
updated asynchronously. This change fixes atomic check
failures seen with commit ea9696a769d3 ("disp: msm: sde:
update atomic check for VM_REQ_ACQUIRE state").
Change-Id: I951e41490c01b543b591c0bbe2700fd8eea39c78
Signed-off-by: Yashwanth <quic_yvulapu@quicinc.com>
The pages backing the GEM objects are kept pinned in place as
long as they are alive, so they must not be allocated from the
MOVABLE zone. Blocking page migration for too long will cause
the VM subsystem headaches and will outright break CMA, as a
few pinned pages in CMA will lead to failure to find the
required large contiguous regions.
Change-Id: I5eba32fc8a2730eac29668dbd96aaf8f04ac155f
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Git-commit: 0abdba47dc1df708c365421d481734d3f7fecb01
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
Signed-off-by: Patrick Daly <quic_pdaly@quicinc.com>
Signed-off-by: Narendra Muppalla <quic_nmuppall@quicinc.com>
This change adds a wait for input spec fence to bind
before registering for hw fencing wait on it.
Change-Id: I5453547c29672e39a95b91197983075e3b61d1eb
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
Add tx wait for WB display during modeset to avoid unbalanced
IRQ handle.
Change-Id: I18337e2a06fe5ec98d4d6e6d766abbf4ec585703
Signed-off-by: Lei Chen <quic_chenlei@quicinc.com>
