This change adds the include for <drm/drm_edid.h> required
for the display driver in kernel 6.0.
Change-Id: Ie4c765900a1ae13e1fbb56e458109b725b36748d
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
Convert clock operation to byte2 ops to meet DISPCC requirement.
Clock unit is changed from KHZ to HZ. Added link clock parent as
freq table is no longer supported in byte2 ops.
Change-Id: Icf5a595708040e8afefecebe7f371bb832d6673e
Signed-off-by: Sandeep Gangadharaiah <quic_sandgang@quicinc.com>
Pineapple target adds support for 45deg Directional & Corner
Detection features for Qseed6. This change adds support for
enabling these features through ahb & lutdma programming,
and updates the UAPI as well.
Change-Id: I7910d840cc4e5d1a7ce9444a41e189171487dbca
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
This reverts commit 473453a8d9.
This change decouples mm driver and display driver until mm
driver compilation is enabled.
Change-Id: I1b462d059b26242b6b77b0bc6ad990d7dabcb0ac
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
Pass sde_enc to sde_encoder_control_te instead of drm_enc,
as all callers have access to sde_enc.
Change-Id: Ic61b78c9e8d1ab2ed6e371c19a72367efbb6e5ee
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
Change adds support for storing the INTF watchdog timer long term jitter
curve state. The state before collapse is stored in wd_jitter and
restore back during power restore.
Change-Id: Id83b5cc754daea89d7844ab67b38e12199525ff8
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
Added dsi ctrl version 2.8 support for pineapple hardware
Change-Id: If9beb77c53d70d94b498b5b837c26892a4df9089
Signed-off-by: Kirill Shpin <quic_kshpin@quicinc.com>
DPU hardware is being updated to add per ctl offsets for lut dma.
Change adds support for per ctl offsets.
Change-Id: I2ee1d6ba1a53dea20a3f422ccecb33910fbaf361
Signed-off-by: Gopikrishnaiah Anandan <quic_agopik@quicinc.com>
Add support for UCSC block parameters that includes unmult,
IGC/GC modes, CSC coefficients, and clamps.
Change-Id: I3ef4b729e9c973a98d53dc583233bf5e004035fa
Signed-off-by: Alisha Thapaliya <quic_athapali@quicinc.com>
Currently, panel jitter and loss of precision are not
compensated when calculating the trigger window size
for a QSYNC panel. These errors can be signigicant on
panels supporting very slow frame rate (10 Hz).
This change improves fixed point calculation and take
into account panel jitter when calculating the minimum
qsync time period.
Change-Id: Ibe620862afbd853580992fccec09cac8307b92bd
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
Currently, when there is an idle power collapse HW resets
the internal read pointer value to 0. This causes the trigger
window to be out of sync when power is restored until the
next vsync is received.
This change overrides the internal read pointer value to
the maximum qsync timeout value on restore and defers frame
trigger to next vsync.
Change-Id: Ibdad3f8eb367136ee0d766bed10742a281e36b4e
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
The encoder modeset updates all the plane's qos_dirty flag attached
to the crtc to make sure the qos params are updated during seamless
mode-switch cases like fps or resolution switch. But this is not
required for cwb encoder modeset as it does not have any effect on
the planes attached to the main display. Add check to avoid this
reprogramming.
Change-Id: I1ab7a71971b7200a50e6643407327734b1c9cbc5
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Enabled compilation of msm_drm with mm-drivers components.
Change-Id: Id2f15b314748f9a1a9966625cea98fa4b3855e87
Signed-off-by: Alex Danila <quic_eadanila@quicinc.com>
Pineapple target adds support for writeback contributing to
fal status. This removes the need to signal fal10 veto in those
usecases. In addition, it is no longer needed to program uidle
active per ctl path.
Change-Id: I5e3509fa6399d212563322d51eba04c38a41e9b8
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
This change fixes the copyright in gki_pineappledispconf header
to match lost requirements.
Change-Id: Ic0d7dea7bd943509843c4dbbb403cadbbbb587f6
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
This change enables the WB rotation feature support for pineapple target.
Change-Id: Ib222c2b2996a40c72414c6c3a581916b95ebffd6
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
This change adds support for new dynamic QoS mode for WB rotation
which is required to achieve rotation output available at required
rate to meet real time use case. Though traffic shaper can be
disabled in dynamic QoS mode, part of traffic shaper algo to track
WB operating speed is enabled and WB generates creq priority
based on current ouput rate compared to targetted ouput to help
meeting real time use case requirement.
Change-Id: I98c2dcae53f1b175dc49b40238b9da33e95717a6
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
MDSS 10.0.0 HW is capable to rotate input image in WB hardware
block. WB hardware can only perform rotation of clockwise 90 degrees
and this can be used to achieve the required 2D rotation by adding
appropriate FLIP transformation to the SSPP. This change adds required
software support in display driver to excericse input image
rotation through WB block.
Change-Id: Ia5c2fc84eabb68f29d130333316527b60d02cbc7
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
MDSS 10.0.0 HW supports rotation of input image with
writeback HW but output color formats are restricted to
32 bit uncompressed A5X tile formats. This change exposes
the supported WB output color formats to client for WB
rotation usecase.
Change-Id: Ic52e6ee4ab882b7dad6edd0daa91b593afbcae01
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
This change installs required drm properties for writeback
connector to implement rotation with writeback hw in mdss.
Change-Id: I85ed359d06ff4bafee85a4bfa5b8a99774311e60
Signed-off-by: Prabhanjan Kandula <quic_pkandula@quicinc.com>
This change adds support to wait on multiple hardware fences by
creating a fence array so each dpu-client only gets signaled until all
the hw fences going to the same ctl-path are signaled. It also
accounts for if a fence is a fence array.
Change-Id: Iba4b1d2b7322aea64dc197ca7655920b79dbb919
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
Add logs to track the read/write line counters
and tear check configuration during key events.
Change-Id: Ife8afecc63a9008a8d9fc746d0ec8579a311b335
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
The register offsets are decremented instead of incrementing during
the logging of registers through the debugfs option. Fix it to be
incremental to help in debugging.
Change-Id: Iefc98c40143554fa7169ff220793431d774f57ce
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
The cwb_enc_mask is set by the wb phys encoder during the validate
phase and this is in-turn used during the commit phase. During
seamless transition cases like poms with cwb, the encoders are
disabled and then enabled back after the validate phase. The cwb
flags are reset during this time leading to issues. Cache the flag
and reapply it during the modeset to avoid this case.
Change-Id: I5df1be18a5e30bb1107dc0f2e87d771a735f1ab6
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Set the boolean property to enable second dedicated
CWB feature on pineapple hardware.
Change-Id: Ibacf0ec327c5d6d803f1fc5211dedb3a591b441a
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
For second dedicated CWB pingpong blocks, the overflow irq needs
to be mapped properly to existing IRQ handlers.
Change-Id: I7630766d1865f7ad7079947185ef4ae629d71f3e
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
Update the hardware blocks and corresponding APIs
to configure new D-CWB data path. Add new hardware
pingpong blocks that are dedicated for second DCWB.
Change-Id: I529c24ac5aa483f30b6c9e7653eb1713c6b8fb8a
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
