Testing of the SPR feature shows IPC restore frames where partial update
programming is not applied. This is a result of the pre-IPC cached ROI
region being used for filtering of CRTC ROI changes.
Update the CRTC cached ROI logic to clear the cached ROI on IPC events.
This ensures color processing partial update logic handles the post IPC
frame with a clean state.
Change-Id: I4e337bd150d02e4c8934ca04c0d632d5ad71dd5d
Signed-off-by: Christopher Braga <quic_cbraga@quicinc.com>
Add property to parse and select the ddr string based
on the detected ddr type.
Change-Id: I012b10e31a21a7a1a0e279df119e9803e2d5a0ce
Signed-off-by: Akash Gajjar <quic_agajjar@quicinc.com>
Change swaps right mixer flag when swapping mixer.
Histogram IRQ is registered to unexpected mixer
index if both mixers' right mixer flag set as false.
Change-Id: I0243d70129dc0c3bff24cabc8877c626101acd83
Signed-off-by: Renchao Liu <quic_rencliu@quicinc.com>
Provide spr_roi region for spr over fetch in partial update.
Support different the roi size of connector and crtc.
Change-Id: Ic78a20badcafefd353a97532281dae26e5a772de
Signed-off-by: Qing Huang <quic_huangq@quicinc.com>
Demura backlight value will be updated based on the backlight event
in the driver. Make HFC gains programmable based on backlight value.
Signed-off-by: Mitika Dodiya <quic_mdodiya@quicinc.com>
Change-Id: I74e9aa2c274eedb473095c5eafef194d6a6f1d94
Fence error handling for wb and cwb retire fence.
Signal the retire fence for the fence error frame.
Change-Id: I0f73195c50edab4b8aefb58cea342214be87584c
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
Add framework for display submodules like PP, DSI, DP to register
for fence error and call the client callback funtion when fence
error occurs.
Change-Id: I70cc6b01907177e6c4238c4398fe2c085a000322
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
Sw fence error handling addresses following:
a. out of order handling
- For cmd panel, signal the release fence and retire fence once
sw fence error detected.
- For vid panel, signal the fence error frame release fence and
retire fence once sw fence error detected, hold the release
fence of last good frame till next good frame.
b. avoid BW decrease vote
c. lut dma reset
d. cancel kickoff
Change-Id: Ic496c532a26d80e0ef0074624ef6ace01c4ab2f0
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
Handle out of order dma fence signalling and propagation of fence
error. Out of order fence signaling is required only in Video mode.
For example, in case of N, N+1, N+2 frames where N, N+2 are good
frames and N+1 is frame with fence error. The release fence signal
sequence in video mode would be N+1, N, N+2.
Change-Id: I8b6f88cfeee945e28571b765f24ffea22fad23b8
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
Register callback function to hw fence driver and implement the
callback funtion.
As part of fence error handling, address out of ordering of HW
fences, SW override for release fence signal and handle BW voting
in both cmd and video mode.
Change-Id: I22902762b4cc09a5f5a20cf0dd01fc336a0f0cb4
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
Add a new property CRTC_PROP_HANDLE_FENCE_ERROR for userspace
to enable or disable fence error handling.
Change-Id: I72370f405c5299c603b0d673720c28a68c00807a
Signed-off-by: GG Hou <quic_renjhou@quicinc.com>
Propagate error in case the number of active displays is greater
than 1, in dual display scenario to fail the validate.
Change-Id: I04250af8d7a6b0c290132abbaed2ed8e5e311a4f
Signed-off-by: Raviteja Tamatam <quic_travitej@quicinc.com>
Current implementation we apply the color properties when atomic begin
is called and mark features as dirty if crtc is not enabled.
For some of the non double buffered features in video mode we will
see a corruption. Change removes marking color properties as dirty
based on crtc on/off.
Change-Id: I4d93b14627d2bc06fcbca3ea9538a4baedb00e56
Signed-off-by: Lakshmi Narayana Kalavala <quic_lkalaval@quicinc.com>
When the vblank event overflow error log occurs due to an inability
to handle incoming vblanks, it is posisble to continuously flood
with error print logs. This could cause the CPU to become further
blocked and creates a cycle of failed callbacks and error logging.
This change changes the overflow log in the crtc event thread to
rate limited.
Change-Id: Ie2d77689c8fa989cf3a294f973851b7dacef098b
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
If the event thread worker processing vblank_notify_work is
scheduled out while holding spinlock to process the ctl-done
interrupt, it will result in a deadlock as the
frame_event_callback requires the same spinlock.
This change updates vblank notify work to use spin lock irqsave &
irqrestore to ensure we don't hit this case.
Change-Id: I96bcb3b21bf9426016f5b3ae43f7d1f8581a8483
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
clear cached rectangles when PU ROI is set to avoid incorrect
cached rois when two subsequent state duplications occur due
to timing. This will lead to commit N and commit N+1 to have
same cached ROIs as commit N-1. This results in issues when
commit N-1 is PU, N is full frame and N+1 is PU with same
ROI as N-1.
Change-Id: I3bb9390e500d327e703e41d64f7aaae5e5f1b4f2
Signed-off-by: Anjaneya Prasad Musunuri <quic_aprasad@quicinc.com>
When precise vsync timestamp feature is enabled, move the vblank
signaling from interrupt context to event thread. This helps in
freeing up the interrupt context soon. The precise vsync timestamp
feature along with DRM hooks to get the vblank timestamp will get
the correct timestamp though the event thread is scheduled later.
Change-Id: I77002913f222ff422b6118f9fc952533065c07aa
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Starting with HW-Fencing, the frames hw kickoff
can take longer to trigger, given that HW will wait for the
input fences signal. Therefore, this change increments
the time-outs to wait up to ~10 secs, which corresponds
to the current input dma-fences timeout. This ~10secs
wait is given in intervals, where the dma-fence is also
checked, so in case that the client producer of the fence
signals the dma-fence, but misses the hw-fence signaling,
Display driver can handle this case and do a sw-override
to start the fetching of the incoming frame without waiting
for the input hw-fence ipc signal.
Change-Id: I6fcacbbaa79ca9847da616bd52efdda4bb8fccae
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
This change adds debug changes to dump the input fences during a
commit done timeout, when input hw-fences are enabled.
Change-Id: Ia778d3d73ab8ee795613587da70ef9bebb7c73ca
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
This change adds support for enabling the system cache
slices with staling. This allows back to back static display
cache usecases to self evict prior to using cache.
Change-Id: Iea71da26a8f7a450822624305dc20a3bab323d4b
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
Current display driver sets the hw-fences as valid even when
the speculative fence is empty. Avoid this issue by doing a
positive check and only create hw-fences if all the fences in
the speculative fence are valid.
Change-Id: Iec9636641ac9146eb651be08615e2478994c2508
Signed-off-by: Ingrid Gallardo <quic_ingridg@quicinc.com>
Move print message from error to debug for a failure that is not fatal
but can be expected when a crtc doesn't have a hw ctl, in this case
driver will handle the output fence as a sw-fence.
Change-Id: I908135dce4336b0c9ec3fa388dc9211c6df97f68
Signed-off-by: Ingrid Gallardo <quic_ingridg@quicinc.com>
Change adds support for storing the INTF watchdog timer long term jitter
curve state. The state before collapse is stored in wd_jitter and
restore back during power restore.
Change-Id: Id83b5cc754daea89d7844ab67b38e12199525ff8
Signed-off-by: Shamika Joshi <quic_shamjosh@quicinc.com>
The encoder modeset updates all the plane's qos_dirty flag attached
to the crtc to make sure the qos params are updated during seamless
mode-switch cases like fps or resolution switch. But this is not
required for cwb encoder modeset as it does not have any effect on
the planes attached to the main display. Add check to avoid this
reprogramming.
Change-Id: I1ab7a71971b7200a50e6643407327734b1c9cbc5
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
This change adds includes for <linux/file.h> required for the
display driver in kernel 5.19.
Change-Id: Ibe5401997b43844b692869ebb6d28faa7bcb7740
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
Move frame data stats collection/notification during frame-done and
retire fence sysfs notification to event thread. This will free up
some interrupt time.
Change-Id: I2648ac4287ce8712e9a059edd408a59753aa6d32
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Use with the new connector state during validation phase for
checking the 3d-merge topology, since this is the state that
needs to be validated.
Change-Id: Ie212f948affa4dc439ef508363bac6713e560006
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
MDSS 9.0.0 supports 10 pipes, so modify the max_planes
accordingly. This is used for the frame_data transfer
between user/kernel and since its a new feature added
there is no backward compatibility that needs to be handled
for this uapi change. Add corresponding bound check during
the usage.
Change-Id: I0853fcc55395855d798f2c1b03cf9bf7b4bd3c96
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Add validation during crtc_atomic_check to have crtc width as
multiple of 4 when dualpipe 3d-mux is enabled and multiple of 8
when quadpipe 3d-mux is enabled. This ensures each layer mixer
is having an even width.
Change-Id: I5dc173c1b0349430a8e12a7b1c9440c7854e7ecd
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
This change converts the ubwc stats roi into a blob property. This
allows for the roi data structure to be passed into kernel.
Change-Id: I4b30dcc16bcbd152428861444ff321add860942f
Signed-off-by: Nilaan Gunabalachandran <quic_ngunabal@quicinc.com>
Use pointer and allocate dynamic memory for msm_mode_info
in _sde_crtc_check_rois instead of object to reduce the
stack memory size.
Change-Id: Ida8fc7e2b94e19b3c791dcda55a465a4107ef976
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Signed-off-by: Jeykumar Sankaran <quic_jeykumar@quicinc.com>
This change disables hw-fencing for the last commit before
vm transition. This avoids configuration issues if hw-fencing is
disabled in the incoming VM.
Change-Id: I573b7d1665f8cef442168bd0ab83a4b2b6cebbb6
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
Add check in layer mixer to avoid odd values as HW does not
support it.
Change-Id: Ifddd2047c81a016b774712ee52cfceca83374e6d
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
This change adds a wait for input spec fence to bind
before registering for hw fencing wait on it.
Change-Id: I5453547c29672e39a95b91197983075e3b61d1eb
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
When destination scaler feature is enabled along with demura,
the crtc w/h will be lesser than the deumra layer w/h as it is
based on the panel w/h. Remove the invalid validation of
demura layers against crtc w/h to allow this usecase.
Change-Id: I5afd0407382a1bce458c97fcf8d571f5e7c0774f
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Add crtc checks to ensure the crtc width is always even number,
so there is no loss while dividing by num_mixers. Add checks in
dnsc_blur to ensure the src is always greater than the dest.
Change-Id: I876f19aa20857dc9ed2649c9cb7569348e7d5fd3
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
Log the vblank timestamp during vblank callback. This will be
useful in calculating the precise difference between the vsync
while debugging. As part of the change, remove the vblank
counter logging in sde_crtc as it floods the logs with 4 entries
for each vblank request.
Change-Id: I6b532ad657581fb2a34318541acbd81a44858819
Signed-off-by: Veera Sundaram Sankaran <quic_veeras@quicinc.com>
This change adds support for triggering output
hw fence upon programmable line count.
Change-Id: Ie4b8252e4f9a448a8c11d17696b9bb0ded81b04b
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
This change disables hw_fences when a mode switch
from video to command mode or command to video mode
is ongoing.
Change-Id: I6f99226b59b381c6d2ff34a85753f8608080f546
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
Starting mdss 9.0, dpu supports triggering
the frame fetch through hw-fencing. This change
adds support for this hw-fence feature.
Change-Id: Icc7d0b69fc2a51103d14612f5ac89b44a47ed826
Signed-off-by: Ingrid Gallardo <quic_ingridg@quicinc.com>
Signed-off-by: Christina Oliveira <quic_coliveir@quicinc.com>
This change collects the OPR, MISR values. If the values are
different than the previous then notify to client with custom event.
Change-Id: I2546439be1f665d90e6505d65283d28096bf7cdd
Signed-off-by: Akshay Ashtunkar <quic_akshayaa@quicinc.com>
Toggle LLCC SCID for each consecutive LLCC write
operations and force read allocate when NSE bit
set.
Change-Id: Ice473cb126b627056b7346f142bc84c120e05f0b
Signed-off-by: Amine Najahi <quic_anajahi@quicinc.com>
